Electronics and Electrical Engineering Laboratory ... · Some of these projects are supported by...

THE ELECTRONICS AND ELECTRICALENGINEERING LABORATORY

One of NIST’s seven Measurement and Standards Laborato-ries, EEEL conducts research, provides measurement services,and helps set standards in support of: the fundamental electronictechnologies of semiconductors, magnetics, and superconduc-tors; information and communications technologies, such asfiber optics, photonics, microwaves, electronic displays, andelectronics manufacturing supply chain collaboration; forensicsand security measurement instrumentation; fundamental andpractical physical standards and measurement services forelectrical quantities; maintaining the quality and integrity ofelectrical power systems; and the development of nanoscaleand microelectromechanical devices. EEEL provides support tolaw enforcement, corrections, and criminal justice agencies,including homeland security.

EEEL consists of four programmatic divisions and two matrix-managed offices:

Semiconductor Electronics Division

Optoelectronics Division

Quantum Electrical Metrology Division

Electromagnetics Division

Office of Microelectronics Programs

Office of Law Enforcement Standards

This document describes the technical programs of the Semi-conductor Electronics Division. Similar documents describingthe other Divisions and Offices are available. Contact NIST/EEEL, 100 Bureau Drive, MS 8100, Gaithersburg, MD 20899-8100, Telephone: (301) 975-2220, On the Web:www.eeel.nist.gov

Cover caption: (clockwise from lower left) an IBM 200 mm EDRAM Wafer (photo by Tom Way,courtesy of International Business Machines Corporation, unauthorized use not permitted); aCMOS microhotplate-based conductance-type gas sensor; an HRTEM cross section of a structure,showing four of the six reference features, optimized for calibration to the structure’s siliconlattice; and fluorescence images of a microfluidic device.

ELECTRONICS AND ELECTRICALENGINEERING LABORATORY

SEMICONDUCTORELECTRONICSDIVISIONPROGRAMS, ACTIVITIES, ANDACCOMPLISHMENTS

NISTIR 7181

January 2005

U.S. DEPARTMENT OF COMMERCEDonald L. Evans, Secretary

Technology AdministrationPhillip J. Bond, Under Secretary for Technology

National Institute of Standards and TechnologyHratch G. Semerjian, Acting Director

Any mention of commercial products is for information only; it does not imply recommenda-tion or endorsement by the National Institute of Standards and Technology nor does it implythat the products mentioned are necessarily the best available for the purpose.

Semiconductor Electronics Division iii

CONTENTS

Welcome ................................................................................................................................. ivMission ....................................................................................................................................viVision ......................................................................................................................................viValues .....................................................................................................................................viGoals .......................................................................................................................................viSemiconductors: Backbone of the Electronic/Digital Revolution ......................................... viiSemiconductor Electronics Division Organization ................................................................. ixElectrical Test Structure Metrology ........................................................................................ 1Metrology for System-on-a-Chip (SoC) ................................................................................. 6Power Semiconductor Device and Thermal Metrology ......................................................... 9MicroElectroMechanical Systems ........................................................................................ 13Nanoelectronic Device Metrology ........................................................................................ 19Electronic Materials Characterization ................................................................................... 24Advanced MOS Device Reliability and Characterization .................................................... 29Infrastructure for Integrated Electronics Design & Manufacturing ..................................... 32Knowledge Facilitation .......................................................................................................... 35Major Facilities / Laboratories .............................................................................................. 37Microfabrication Process Facility ......................................................................................... 38NIST Advanced Measurement Laboratory Nanofabrication Facility ................................... 41National Research Council (NRC) Post-Doctoral Opportunities ......................................... 42Division Highlights ................................................................................................................ 46Uncertainties of CD Reference Features Significantly Reduced ......................................... 46SED Researcher Develops Novel 3D XML Browser/Editor ............................................... 47SED Writes First MEMS Standards ..................................................................................... 48New Microfluidic DNA Analysis System for Forensics Applications Demonstrated .......... 49Patterning PDMS Surfaces with Microfluidic Networks ProvidesFoundation for Bioelectronics ............................................................................................... 50SED Leadership Produces Unique Standard on Time-Dependent Breakdownof Ultra-Thin Gate Dielectrics .............................................................................................. 51Congressman Wolf Visits MEMS Laboratory ...................................................................... 52SED Leads Major Semiconductor Metrology Conference Series ........................................ 53NIST’s Gaithersburg, Maryland, Campus and Surrounding Area ......................................... 54

iv Electronics and Electrical Engineering Laboratory

David G. Seiler,Division Chief

WELCOME

The Semiconductor Electronics Division (SED) provides leadership in developing the semicon-ductor measurement infrastructure essential to improving U.S. economic competitiveness. Itprovides necessary measurements, physical standards, and supporting data and technology;associated generic technology; and fundamental research results to industry, government, andacademia. The primary mission of the Division is to provide the measurement infrastructure toU.S. industry for mainstream silicon CMOS (complementary metal-oxide semiconductor) tech-nology. The Division’s programs also respond to industry measurement needs related toMicroElectroMechanical Systems (MEMS), power electronics, and various sub-areas ofnanotechnology including nanoelectronics, nanocharacterization, nanobiotechnology, and plasticelectronics.

The Division has extensive interactions with individual companies, industry organizations, andprofessional societies; these activities enable the development of a research agenda responsiveto the needs of industry. Active participation in industry roadmapping, such as the Semiconduc-tor Industry Association’s International Technology Roadmap for Semiconductors, and stan-dards activities, such as committee work for the American Society for Testing and Materials, ispracticed by the Division to prioritize and establish programs with the highest potential impact.The Division widely disseminates the results of its research, especially in the areas of standard-ized test methods and Standard Reference Materials (SRMs), through a variety of channels:publications, software, conferences and workshops, and participation in standards organizationsand consortia. The Division also actively seeks industrial, academic, and non-profit researchpartners to work with collaboratively on projects of mutual benefit.

The Division, with a staff of about 80 including full-time and part-time employees as well asguest researchers, post-doctoral associates, and contractors, is based in Gaithersburg, Mary-land. The Division is one of four divisions within the Electronics and Electrical EngineeringLaboratory at NIST. The Division’s technical activities are organized into three groups: theEnabling Devices and ICs Group, the CMOS and Novel Devices Group, and the ElectronicInformation Group. The Division assists industry by providing tools such as SRMs, test chips,standard reference data, and software that support the needed measurement infrastructure.Division personnel visit industrial sites, host a variety of visitors, and make available tutorialmaterial on an as-needed basis. We also are active in conference and workshop activities thatdirectly benefit the industry.

A broad array of activities that serve the semiconductor industry is currently underway in theDivision. The staff of the SED addresses projects ranging from materials qualification to teststructures for integrated circuits. Some of these projects are supported by the NIST NationalSemiconductor Metrology Program (NSMP), which is managed by the Electronics and Electri-cal Engineering Laboratory’s Office of Microelectronics Programs. For more information onthe NSMP, please visit their Web site at www.eeel.nist.gov/omp.

The Division, in cooperation with the National Research Council (NRC), offers competitiveawards for post-doctoral research for U.S. citizens in a variety of technical fields related to thesemiconductor electronics industry. For additional details, including field descriptions and quali-fication guidelines, please see page 42.

The technical programs, their goals, technical strategies, activities, and accomplishments de-scribed here for each Division project clearly demonstrate the impact of the SED’s leadershipand effective service as it continues to respond to the needs of industry and to contribute to thescientific and engineering communities.

“Industry views SED’s

contributions as unique

and essential to effi-

ciently providing mea-

surement techniques

and standards.”

NRC Panel Report, AnAssessment of the NationalInstitute of Standards andTechnology Measurement andStandards Laboratories:Fiscal Year 2003

Semiconductor Electronics Division v

Please take an opportunity to visit our Division website at www.eeel.nist.gov/812/. In additionto providing further details on our Division and up-to-date project information, our website hasinteractive tutorials on the Hall effect (www.eeel.nist.gov/812/hall.html) and MEMS standardtest structures based on e-standards (www.eeel.nist.gov/812/test-structures/). Please also besure visit the Systems Integration for Manufacturing Applications website (www.nist.gov/sima)on product data exchange standards.

Thank you for your interest in our Division and its technical programs! I welcome your com-ments and suggestions. Feel free to e-mail me at [email protected].

David G. SeilerDivision Chief

Semiconductor Electronics Division Staff

For additional information, contact:

Division/Office Telephone: 301-975-2054Division/Office Facsimile: 301-975-6021On the Web: www.eeel.nist.gov/812/

vi Electronics and Electrical Engineering Laboratory

MISSION

The Semiconductor Electronics Division provides technical leadership to industry, government,and academia in research and development of the semiconductor measurement and softwareinfrastructure needs essential to the silicon microelectronics industry, advanced semiconductormaterials technologies, and advanced electronic devices based upon molecular or quantumstructures.

VISION

The Semiconductor Electronics Division strives to be recognized as a dynamic, world-classresource for semiconductor measurements, data, models, software, and standards focused onenhancing U.S. technological competitiveness in the world market.

VALUES

The Semiconductor Electronics Division values its commitment to identify and meet crucialmeasurement technology needs. The Division values its collaboration with all segments of thesemiconductor community. It strives for integrity, excellence, objectivity, responsiveness, andcreativity, while maximizing and utilizing the potential of its employees.

GOALS

The Division will:

# Aggressively pursue and achieve select metrology needs as identified in the InternationalTechnology Roadmap for Semiconductors for mainstream silicon.

# Develop new and improved process-monitoring tools, methodologies, and data for the moreefficient manufacture of silicon and compound-semiconductor devices.

# Support novel research that has high potential for providing breakthroughs in materials,process, devices, and measurement technologies for the semiconductor industry.

“The nature of the

vision’s purpose is not

only to achieve a mean-

ingful strategic or

company goal, but also

to build a dedicated

community…”

Jay A. Conger, The BraveNew World of LeadershipTraining, IEEE Eng. Mgmt.Review (1996)

Semiconductor Electronics Division vii

SEMICONDUCTORS: BACKBONE OF THEELECTRONIC/DIGITAL REVOLUTION

For the past 20 years, the personal computer reigned supreme as the driver of semiconductor industrygrowth. But new leadership is emerging. The communications revolution, perhaps the defining socialand economic transition of our time, is fueled by the ever smaller, ever cheaper, ever faster invention ofthe chip industry. The explosive demands of the wireless, broadband Internet and optical networkingindustries have crowned the communications chip as the dominant end market for semiconductors.

# Information technology (IT) continues to be the primary driver of the U.S. economy, and U.S. semi-conductor companies are leading the charge. American chipmakers now supply nearly half of theworld’s chips.

# U.S. chipmakers add more value to the national economy than any other industry.# For 50 years, the semiconductor industry has provided the bricks and mortar that built the modern

world. The exciting expansion in semiconductor applications means our job has only just begun andthat our industry’s greatest growth lies ahead.

# Personal communications devices will become so functional as to be indispensable, cars will be saferand more fuel-efficient, the quality of education will improve, chips implanted in our bodies will tellour doctor we’re sick before we register symptoms. Eventually silicon and biology will converge,and the biocomputer will seem no more novel than today’s laptop. As Forbes ASAP Editor MichaelMalone has noted, “the microprocessor is the defining invention of the electronic age, the inventorof inventions.”

- adapted from the Semiconductor Industry Association (SIA)2001 Annual Report, pp. 2–5.

Semiconductors, transistors, and their applications represent one of the greatest scientific and techno-logical breakthroughs of the twentieth century. Consider their far reaching influence on our society ingeneral and our daily lives. Can you imagine life without them? Semiconductors are pervasive in themicroelectronic components used in computers, entertainment equipment, automotive electronics, medi-cal instrumentation, telecommunications, space technology, television, radio, cell phones, and manyother information technologies. Every hospital, school, factory, car, airplane, office, bank, and householdcontains transistors, microprocessors, and other semiconductor devices.

These breakthroughs are possible because of the miniaturization of the transistor dimensions, whichallows the construction of compact systems with tremendous computing power and memory. Miniatur-ization, in turn, is possible because of the perfection of fabrication techniques that allow the integrationof circuits and thus the production of chips containing millions of elements per square centimeter. Thefoundation stone of this complex technology is silicon. Meeting the demands for these large-scale,complex, integrated circuits (ICs) continues to require technological advances in materials, processing,circuit design, characterization, testing, and standards.

The semiconductor electronics industry is outstripping the measurement capability needed for maintain-ing and improving U.S. international competitiveness. Important factors affected include product perfor-mance, price, quality, compatibility, and time to market. The Semiconductor Electronics Division providesthe measurement capability needed to support the efforts of U.S. industry to improve its competitive-ness. In order to support this effort, the Division also engages in technology development and funda-mental research, making the findings available to industry.

The Division focuses the largest part of its resources on the development and delivery of measurementcapability for two principal reasons: measurement capability has a very high impact on U.S. industrybecause it helps manufacturers address many of the challenges they face in realizing competitive prod-ucts in the marketplace, and NIST is the official lead U.S. Government agency for measurements.

The Division focuses on developing measurement capability that is beyond the reach of the broad rangeof individual companies. Companies seek NIST’s help for several reasons:

“This year the semicon-

ductor industry will

manufacture about 60

million transistors for

every man, woman and

child on earth. By 2008,

chipmakers will be

producing 1 billion

transistors or more per

year. Transistors

improve our lives in

countless ways—they

make cars safer and

more fuel-efficient, they

enable personal commu-

nication devices, they

promote medical break-

throughs and they

improve the quality of

education.”

Building Blocks forInnovation, SIA AnnualReport 2002, p. 17

viii Electronics and Electrical Engineering Laboratory

# The companies need NIST’s special technical capability for measurement development.# The companies need NIST’s acknowledged impartiality for diagnosing a measurement problem af-

fecting the industry broadly or for achieving adoption of a solution across the industry.# The companies cannot develop the measurement capability needed by the industry broadly because

they cannot individually capture the returns of the cost of development.# Industry’s quality standards require that key measurements be traceable to the national measure-

ment reference standards that NIST maintains. This is a requirement of growing importance in exportmarkets.

The Division continues to interact and collaborate with a wide variety of companies, consortia [such asInternational Semiconductor Manufacturing Technology (ISMT), Semiconductor Equipment and Mate-rials International (SEMI), and the Semiconductor Research Corporation (SRC)], academia, and othergovernment labs to accomplish its mission. Specific details are given in the project descriptions thatfollow. Work in the Division results in extensive outputs or deliverables that cover knowledge andimprovements in physical understanding, test methods and measurements, Standard Reference Materi-als (SRMs), Standard Reference Data (SRD) sets, standards, test structures and test chips, software,measurement accuracy and traceability, publications and reports, patents and Cooperative Research andDevelopment Agreements (CRADAs), round robins, data and models, talks and short courses, companyvisits, conferences and workshops, consortia participation, and various activities and leadership roles oncommittees and working groups.

Division staff serve the semiconductor community in leadership roles on standards committees such asAmerican Society for Testing and Materials (ASTM) and Electronic Industries Alliance (EIA) / JointElectron Device Engineering Council (JEDEC), societies such as IEEE, ECS, and APS, and numeroussemiconductor conferences/workshops. Many test methods and standards have been developed andwritten over the years by NIST staff for ASTM and EIA/JEDEC, including ones for resistivity, oxygen insilicon, thin dielectrics, electromigration, and device characterization. Staff serve on various TechnicalWorking Groups to help put together the International Technology Roadmap for Semiconductors (ITRS).These groups are Process Integration, Devices, and Structures; Assembly and Packaging; Lithography;Interconnect; Front End Processes; and RF and Analog Mixed Signal. The ITRS provides targets forequipment, material, and software suppliers; provides targets for researchers; and serves as a commonreference for the semiconductor industry.

The Division also has impacted the semiconductor community by producing a number of SRMs. To date,over 2,800 SRMs have been sold and distributed for resistivity, oxygen in silicon, and optical thicknessby ellipsometry. Hundreds of companies throughout the world have purchased these SRMs to maintainand improve their measurement capabilities.

For the future, the Division has identified nanotechnology and its various sub-areas, includingnanoelectronics, nanocharacterization, nanobiotechnology, and plastic electronics, as emerging areas ofresearch to address.

“The semiconductor industry is rapidly reaching a point in its evolution where its ability to buildsmaller nodes will encounter serious difficulties in the form of quantum effects and atomic levelstatistical fluctuations … nanotechnology will both help keep CMOS scaling on track andenable new materials/technology platforms that satisfy market needs better than CMOS … ascurrent lithography methods reach their limit, the tools used in the development, manufacture,and testing of CMOS will increasingly be based on nanotechnology.”

- from L. Gasman, “Why Nanotechnology Is So Important for the Semiconductor Industry,”NanoMarkets White Paper, p. 2.

“Another success

occurred in the develop-

ment of standards for

measuring the shrinking

line widths that charac-

terize semiconductor

products. Because

industry alone cannot

develop these new

standards of measure-

ment, the National

Institute of Standards

and Technology (NIST) is

overseeing the process.”

SIA Annual Report 2004,p. 30.

Semiconductor Electronics Division ix

SEMICONDUCTOR ELECTRONICS DIVISIONORGANIZATION

DIVISION OFFICE (812.00)2054 SEILER, David G., Chief2054 GUARIGLIA, Lori A., Secretary4514 COOK, Sharon W., AO

2079 BENNETT, Herbert S., NIST Fellow2097 HARMAN, George G., Scientist Emeritus2050 SECULA, Erik M., Editor

ENABLING DEVICES AND ICS GROUP(812.05)2068 BLACKBURN, David L. (GL)2052 WILKES, Jane, Secretary

ELECTRICAL TEST STRUCTURE METROLOGY

2072 CRESSWELL, Michael W. (PL)5026 ALLEN, Richard A.8193 MURABITO, Christine E.2234 SCHAFFT, Harry A. (CNR)2182 YARIMBIYIK, Emre (GR)

METROLOGY FOR SYSTEM-ON-A-CHIP

2071 HEFNER, Allen R., Jr. (PL)5420 AFRIDI, Muhammad Y. (CNR)2069 BERNING, David W.2236 ELLENWOOD, Colleen E.5484 GEIST, Jon (CNR)6757 SALCEDO, Javier (GR)6757 VARMA, Ankush (GR)

POWER DEVICE AND THERMAL METROLOGY

2071 HEFNER, Allen R., Jr. (PL)8777 AKUFFO, Adwoa (CNR)2081 DUONG, Tam (CNR)2236 ELLENWOOD, Colleen E.8776 HERNANDEZ, Madelaine (CNR)

MICROELECTROMECHANICAL SYSTEMS

2070 GAITAN, Michael (PL)5484 GEIST, Jon (CNR)4796 HONG, Jennifer (CNR)4739 HUANG, John (S)4710 JAHN, Andreas (GR)4110 MacARTHUR, Daniel (S)2049 MARSHALL, Janet C.2052 McGRAY, Craig (PD)6367 MIJARES, Geraldine I.2045 MORGAN, Nicole (PD)2492 NABLO, Brian (PD)6347 POLK, Brian5466 REYES-HERNANDEZ, Darwin2305 SHAH, Jayna (GR)3095 SUNDARESAN, Siddarth (GR)

Legend:

AO = Administrative OfficerCNR = ContractorFA = Focus AreaFL = Focus Area LeaderFM = Facility ManagerGL = Group LeaderGR = Guest ResearcherPD = PostDoctoral

AppointmentPL = Project LeaderS = Student

Telephone numbers are:(301) 975-XXXX (replaceXXXX with the four-digitextension as indicated)

WIRE BONDING TO CU/LOW-κ SEMICONDUCTORDEVICES (FA)2097 HARMAN, George G. (FL)

CMOS AND NOVEL DEVICES GROUP(812.06)4723 VOGEL, Eric M. (GL)2053 St. CLAIR, Melissa, Secretary

NANOELECTRONIC DEVICE METROLOGY

2082 RICHTER, Curt A. (PL)2078 EDELSTEIN, Monica D.2233 HACKER, Christina2087 KIRILLOV, Oleg8755 KOO, Sang-Mo (GR)3241 LI, Qiliang (CNR)5291 RAMACHANDRAN, Ganesh (CNR)2247 SUEHLE, John S.4723 VOGEL, Eric M.3377 WANG, Wenyong

ELECTRONIC MATERIALS CHARACTERIZATION

2089 KOPANSKI, Joseph J. (PL)5974 AMIRTHARAJ, Paul (GR)2084 CHANDLER-HOROWITZ, Deane2060 EHRSTEIN, James R.2088 JELIAZKOV, Stoyan (CNR)3241 LITTLER, Chris (GR)2044 NGUYEN, Nhan V.2048 PARK, Seong Eun (GR)2067 THURBER, W. Robert (GR)

ADVANCED MOS DEVICE RELIABILITY ANDCHARACTERIZATION

2247 SUEHLE, John S. (PL)2078 EDELSTEIN, Monica D.8687 HEH, Da-Wei (GR)8755 KOO, Sang-Mo (GR)4723 VOGEL, Eric M.2111 ZHU, Baozhong (GR)

THEORETICAL SOLID-STATE PHYSICS FORSEMICONDUCTORS (FA)2079 BENNETT, Herbert S. (FL)

x Electronics and Electrical Engineering Laboratory

NIST AML NANOFABRICATION FACILITY &SED MICROFABRICATION FACILITY

2699 HAJDAJ, Russell (FM)2242 BUCK, Laurence M.5623 OWEN, James C.2095 KESWANI, Vinay (CNR)2096 ROPPOLO, Richard

ELECTRONIC INFORMATION GROUP(812.07)3644 BRADY, Kevin G. (GL)2053 St. CLAIR, Melissa, Secretary

INFRASTRUCTURE FOR INTEGRATED ELECTRONICSDESIGN AND MANUFACTURING

4284 MESSINA, John (PL)8778 ARONOFF, Matthew4951 BABOUD, Julien (GR)5108 BERTON, Dominique (GR)3644 BRADY, Kevin G.4229 DEVAULX, Frederic (GR)2432 GRIESSER, Art8581 KHALILI, Neda (S)3263 KOSTICK, Jennifer A.5319 LI, Ya-Shian3246 MOORE, David (GR)3956 SIMMON, Eric5319 SMITH, Nathan (S)

KNOWLEDGE FACILITATION

3263 KOSTICK, Jennifer A. (PL)4479 MEYER, Mariana (S)8747 NEWTON, Meridel (S)

Legend:

AO = Administrative OfficerCNR = ContractorFA = Focus AreaFL = Focus Area LeaderFM = Facility ManagerGL = Group LeaderGR = Guest ResearcherPD = PostDoctoral

AppointmentPL = Project LeaderS = Student

Telephone numbers are:(301) 975-XXXX (replaceXXXX with the four-digitextension as indicated)

Semiconductor Electronics Division 1

ELECTRICAL TEST STRUCTURE METROLOGY

GOALS

Develop test-structure based metrology utilizingelectrical and other techniques: characterize theefficacy of interconnect materials, with emphasison ultra-high-density copper interconnects; ap-ply MEMS-based silicon-patterning techniques tothe fabrication of test structures for critical dimen-sion (CD) and overlay extraction by optical, elec-trical, or other methods; and contribute to stan-dards organizations supporting the extension ofmetrology standards to copper interconnect.

HRTEM cross section of a CD test structure, com-prised of six reference features optimized for calibra-tion to the structure’s silicon lattice.

Technical Contact:Michael W. Cresswell

Staff-Years (FY 2004):3.5 professionals1.5 guest researchers

CUSTOMER NEEDS

In order to meet new clock-frequency demands,research by the semiconductor industry has fo-cused on lower-resistance interconnect materials.The primary material replacing aluminum as an in-terconnect material is copper because of its nomi-nally low resistance properties and its improvedreliability characteristics. For example, Intel’smost-recently announced fabrication process willfeature transistors having 35 nm gate length, whichwill be the smallest and highest-performing comple-mentary metal oxide semiconductor (CMOS) tran-sistors in high-volume production. The processintegrates eight copper interconnect layers thatincrease the signal speed inside the chip and re-duce chip power consumption. Intel will continueto use copper interconnects for several more tech-nology nodes. However, there is concern that the

projected benefits of copper may not map into in-terconnect features with dimensions projected bythe International Technology Roadmap for Semi-conductors (ITRS) because relatively little researchhas been reported on the limiting physics of elec-tron transport in ultra-narrow metal conductors.

Interconnect fabrication processes involve a se-quence of up to several tens of lithographic opera-tions, each requiring close alignment of the pat-terned resist to features that have been etched af-ter the previous such operation. Successful manu-facturing typically requires alignment accuraciesin the low several nanometers range. The demandfor accurate alignment is increasingly challengingnot only for the lithographic tool manufacturersand users, but also for the metrologists contribut-ing to the process-control infrastructure. For ex-ample, the ITRS, which specifies the overlay re-quirements for each technology node (DRAM half-pitch), specifies 3.3 nm for the 2005 / 90 nm nodedecreasing to 1.6 nm for the 2010 / 45 nm node.Thus the metrology challenge to which this projectproposes to contribute is the verification of me-trology tool performance. Overlay quality is thecloseness to zero of the overlay vector, which tra-ditionally has been measured by optical metrologytools. At earlier lithography nodes, these toolshave performed adequately. However, at smallerlithography nodes, corrections called shifts haveincreased in size relative to the measured overlay.These shifts are extracted from the wafer-tool in-teraction and applied to local measurements of theoverlay vector. As design rules have further de-creased to the sub-tenth micrometer region, a newchallenge has arisen from the fact that the metrol-ogy is fundamentally optical in nature. In general,the local value of the measured optical overlay,even when corrected for shifts, does not ad-equately match the local value of the interconnectsystem’s performance. The problem is that electri-cal overlay is the functionally relevant quantityfrom the viewpoint of circuit performance. We planto use a test structure patented by project staffthat provides the relationship between the opti-cally-extracted overlay and the electrical overlaythereby enabling established overlay metrologytooling to be applied to the latest generations ofscaled interconnect systems.

The emerging metrology known as optical-diffraction process (ODP) control scatterometrytranslates broadband light, diffracted from an on-wafer grating patterned into the resist or film, into

2 Electronics and Electrical Engineering Laboratory

accurate profiles of the grating’s features fromwhich key parameters, such as CD, can beextracted. Whereas currently favored metrologytools such as CD scanning electron microscopesrequire a vacuum wafer environment, opticalscatterometry does not and is fast and non-invasive. The possibilities of ODP extend tocharacterizing the sidewall angle and height ofcritical features. Until physical standards areavailable, the full promise of ODP controlscatterometry may not be met.

The ITRS has warned that the photomask industryis beginning to trail the requirements of thesemiconductor manufacturers, especially withregard to CD metrology. Co-development of anadequate photomask CD-metrology infrastructureis essential to support the technical andmanufacturing needs of optical lithography below100 nm. At the present time, there is no establishedtechnique that meets the stated requirements.Optical transmission microscopy has been theprimary metrology method used by photomaskmakers and has the advantage of traceability, butthis technique is not readily available to photomaskusers. Whereas International SEMATECH (ISMT)is developing an atomic force microscopy (AFM)implementation through the use of carbon nano-tubes as robust measurement tips, this approachcould prove costly and may be fundamentally tooslow for full-mask inspection. In addition, AFM isinherently slow and requires contacting the surfaceof the photomask, which can be a cause ofcontamination. Scanning electron microscopy(SEM), although increasingly used for CDmeasurements on photomasks, is limited bycharging of the quartz substrate. On the otherhand, electrical metrology has no known lower CDlimits and could be contamination free except forthe fact that it is a contact metrology with inherentparticulate hazards. Interestingly, no referencesto scatterometry for mask CD-control have beenreported, and it seems that this is one applicationwhere ODP metrology could offer unique benefits.

TECHNICAL STRATEGY

Challenges associated with advanced interconnectinclude the understanding of charge transport invery narrow features. The charge transport is af-fected by the interaction of the charge carriers withgrain boundaries and sidewalls. When the size ofeither the grains or lines is significantly larger thanthe mean free path of the electrons, the conductiv-ity of the wires is similar to that of bulk. However,when these dimensions are less than or equal to

the mean free path, the conductivity is expected toincrease significantly. There are two “features” ofconventional copper interconnect systems thatcomplicate any experiments. The first feature isthe barrier layer that is needed to keep the copperfrom diffusing into the surrounding insulator andsilicon layers. This barrier layer is usually com-prised of a metal, such as tantalum, which is a poorconductor. The second feature is that theplanarization in the damascene patterning processcan lead to dishing or erosion, which leads to thesheet resistance being a very non-linear functionof dimension. Decoupling the contributions to ameasured sheet resistance of these two effects isdifficult, if not impossible.

In this project, we are taking several approachesto address these issues: The first approach is todevelop a model from which the sheet resistancecan be calculated for an arbitrary set of dimen-sions, grain sizes, and scattering coefficients. Theresults from this model will be compared with mea-surements of patterned and unpatterned copperfilms at a range of temperatures. To simplify analy-sis of the material, we will initially measure copperfilms with no barrier layer and later extend the mea-surements to films with barrier layers.

A new challenge in overlay metrology is emergingas a consequence of scaling. The problem is that aplanar definition of overlay does not provide forfunctionally relevant electrical overlay which hasthree-dimensional qualities. On the other hand, anelectrically readable overlay test-structure has beenproposed by us earlier. It requires a two-level metalinterconnect process and will be the first time thatthe concept, for which NIST holds several patents,will have been reduced to practice. A key elementof the test structure is the combination of astandard overlay frame-in-frame target, appendedto an electrically testable component. Thecomposite test structure has multiple elements,each having staggered built-in overlays. The latter’sfunction is to enable the identification, by electricaltesting, of the as-replicated cell that has zeroelectrical overlay, which can then be used as acalibration artifact for normal optical, SEM, or AFMmetrology tools by providing corrections to suchsystems that are based on functionally relevantbehavior of the fabricated patterns. In other words,the test structure addresses the problem thatoverlay extraction by optical means is challengedby the complex interaction of errors known aswafer-induced shift and tool-induced shift. Itseparates these errors and allows for theircorrection. It is fabricated on production wafers


just as are other test structures that are inspectedby fabrication-line metrology tools. However, afterfabrication and optical and electrical testing, itserves as a means of calibrating the optical toolsthat are used to monitor overlay on that particularfabrication line. Its fundamental attribute is that itenables the user to identify the critical relationshipbetween the readings of his/her conventionaloptical metrology tools during inspection ofproduct wafers and the “functionally relevant”overlay properties of the interconnect systemunder fabrication.

The project will incorporate a “Mask ECD”(Electrical Critical Dimension) task that would buildon our previous experience working with a majorU.S. mask supplier to the semiconductor industry.In that work, we devised a direct means ofcomparing measurements of features made on themask with the replicated features transferred fromthe mask to the wafer. We plan to take this work tothe implementation stage with an industry partner.In addition, we will explore the feasibility ofextracting CDs from electrical test data made onan alternating aperture phase-shift mask. Otherworkers in test-structure metrology also haveclaimed that such electrical measurements havethe potential to be both faster and more repeatablethan optical or CD-SEM methods and provide themotivation for continued study of this approach.Two exciting extensions of mask metrology usingneither SEM nor optical tools are beingconsidered. One extension is non-contact ECD,which would draw heavily on knowledge andexperience of staff in EEEL’s Boulder, Colorado,site and may result in a collaborative activityexploring the development of a microwave sensorspecifically for the mask-CD metrology application.The second extension to our mask CD metrologyapproach is scatterometry. The application ofscatterometry to mask-CD metrology wouldprovide a powerful tool for mask CD-control.

There also is a need for standards, especiallyrelated to interconnects. In this project, we willcontinue to participate in JEDEC and SEMIstandards committees with special emphasis onthose relating to interconnect reliability andprocess control.

DELIVERABLE: Draft and submit manuscript onsurface-dominated conduction-electron scattering incopper films and patterned features. Developprocess for patterning recesses in silicon wafers toaccommodate patterned chips for copper-seeding,electro-deposition, and CMP planarization. CompleteL-EDIT CAD for mask to facilitate comparison of CDsextracted electrically by ODP scatterometry from thesame features.

DELIVERABLE: Develop process for seed-layerdeposition on SCCDRM chips. Make initial electricalmeasurements on a selection of SCCDRM features.Prepare draft standard on ECD extraction for reviewby SEMI.

DELIVERABLE: Complete CMP processing of firstcopper-interconnect test wafers and initiatefabrication of overlay test-structure wafers. MakeECD and scatterometry-CD (probably in collaborationwith a scatterometry CD tool manufacturer)measurements on scatterometry test-structures.Prepare draft of paper on modulating current throughSCCDRM features by electrical or other means.

DELIVERABLE: Report on initial electricalmeasurements on first copper-interconnect testwafers as the latter become available fromfabrication. Make ODP measurements on electricalscatterometer test structures. Complete fabrication offirst lot of electrical-overlay test structures.

SEM image of the new test structure. (Lengths of thelines shown are approximately 10 µm, and the widthsrange from about 45 nm to 210 nm.)

ACCOMPLISHMENTS

# Delivered to ISMT, in collaboration withNIST’s Manufacturing Engineering Laboratory(MEL) and Information Technology Laboratory(ITL), ISMT, and VLSI Standards, 10 chipscontaining NIST calibrated CD reference features.These chips, which have been distributed toISMTs 10 member companies, including Intel, IBM,TI, AMD, and Freescale/Motorola, were deliveredwith sub-100 nm CDs and combined uncertaintiesless than 5 nm. The improvement in uncertaintyresulted from the implementation of a new type ofHRTEM-target test structure, the extensive use ofSEM inspection to identify targets with superiorCD uniformity, and the use of advanced AFM toserve as the transfer metrology. Commercialization


of these reference features is being considered byVLSI Standards.

Example of AFM transfer calibration from a singleHRTEM target.

# Introduced a new HRTEM test structure target.This target contains six features with a distributionof drawn linewidths, positioned in such a way asto allow for HRTEM measurement of all six linesfrom a single sample preparation process, the mosttime-consuming and costly part of HRTEM.HRTEM provides the essential absolute primarymeasurement of CD, since it is traceable to theknown spacing of the lattice planes of mono-crystalline silicon. This new target is also optimizedfor AFM imaging which, for these chips, providedthe transfer calibration since HRTEM imagingdestroys the chips.

# Developed, in collaboration with NIST’s MELand ITL, a measurement and data analysisprocedure to minimize the expanded uncertaintyassociated with the CD reference features deliveredto ISMT. The expanded uncertainty is derivedstatistically from the calibration function, whichenables tracing the AFM measurements to thesilicon lattice-plane spacing using HRTEMimaging. The previous generation of referencematerials, which was delivered in 2001 and usedelectrical CD as the transfer calibration, haduncertainties of approximately 14 nm. The secondgeneration units distributed to the ISMT membercompanies have CDs as low as 45 nm anduncertainties, based on statistical analysesperformed by personnel of NIST’s StatisticalEngineering Division, of between 1.5 nm and 3 nm.This decrease in uncertainty is of major importanceto the end-user of these reference features.

Besides the advances represented by the noveldesign of the described test structure, and the roleplayed by NIST in leading the development of

world-class three-dimensional AFM metrology atISMT facilities in Austin, two other innovationswere implemented to help this project-team’smembers achieve the remarkable reduction in CDuncertainty. The first was the installation andmaintenance of a database to archive and rankseveral thousand SEM images of candidatefeatures according to nanoscale CD uniformity.The second was the introduction of ultrasonicallyagitated patterning etches which are believed tohave made at least some contribution to the featureuniformity, which in turn is essential for a low-uncertainty product. The third was devising ascheme for reliably extracting the lattice-planecounts from ultra-high-magnification electron-transmission phase-contrast images of referencefeatures’ cross sections. Finally, the contributionsin statistical analysis made by our partner in ITLplayed a critical role in enabling us to concludethis phase of the project with such spectacularresults.

# Distributed to the ISMT member companies,as well as archiving at ISMT, a Technology-Transfer Document containing all essential detailsof the final phase of the SCCDRM program; itsNovember 2004 delivery served as the completionof the SCCDRM program.

# Participated in completion of the JEDECJESD33B standards for measuring and using thetemperature coefficient of resistance to measurethe temperature of aluminum and copperinterconnect lines. Participating in the revision ofthe JEDEC JESD87 and JEDEC JEP139 standards.Each is being revised to make them applicable tocopper as well as aluminum lines.

FY OUTPUTS

COLLABORATIONS

International SEMATECH, Development of SEM imagingand AFM CD-profile extraction

NIST ITL, Traceability statistics and procedures

NIST MEL, AFM CD-profile extraction

VLSI Standards, Substrate implant and anneal specifications,photo lithography and hard-mask engineering solutions

Accurel Systems, Design of HRTEM targets and formula-tion of appropriate imaging procedures

University of Edinburgh, United Kingdom, Advanced cop-per interconnect


STANDARDS COMMITTEE PARTICIPATION

Electrical Test Structures Task Force, Co-chair (RichardA. Allen)

SEMI International Standards Micro-lithographyCommittee, member (Richard A. Allen)

RECENT PUBLICATIONS

N. Guillaume, W. K. Kahn, R. A. Allen, M. W. Cresswell,M. E. Zaghloul, “Application of Conformal MappingApproximation Techniques: Parallel Conductors of FiniteDimensions,” IEEE Transactions on Microwave Theoryand Techniques, Vol. 53, No. 3, pp. 812-821 (01-JUNE-2004)

N. Guillaume, R. A. Allen, M. W. Cresswell, M. Lahti, L.W. Linholm, M. E. Zaghloul, “Non-contact ElectricalCD Metrology Sensor for Chrome Photomasks Featuringa Low Temperature Co-fired Ceramic Technology,” IEEETrans. on Semiconductor Manufacturing, Vol. 17, No. 1,pp. 25-34 (01-MAY-2004)

R. A. Allen, M. W. Cresswell, L. W. Linholm, “Junction-Isolated Electrical Test Structures for Critical DimensionCalibration Standards,” IEEE Trans. SemiconductorManufacturing, Vol. 17, No. 2, pp. 79-83 (01-MAY-2004)

R. A. Allen, R. I. Patel, M. W. Cresswell, C. E. Murabito,B. Park, M. D. Edelstein, L. W. Linholm, “RecentDevelopments in Producing Test-structures for Use asCritical Dimension Reference Materials,” ICMTS IEEEInternational Conference on Microelectronic TestStructures, March 22-25, 2004, Awaji, Japan, pp. 35-40(01-MARCH-2004)

R. A. Allen, M. W. Cresswell, C. E. Murabito, R. Dixson,E.H. Bogardus, “Critical Dimension Calibration Standardsfor ULSI Metrology,” Characterization and Metrologyfor ULSI Technology: 2003, International Conferenceon Characterization and Metrology for ULSI Technology,March 24-28, 2003, Austin, Texas, pp. 421-428 (30-SEPT.-2003)

R. A. Allen, B. A. am Ende, M. W. Cresswell, C. E. Murabito,T. J. Headley, W. F. Guthrie, L. W. Linholm, C. H.Ellenwood, E.H. Bogardus, “Test Structures for ReferencingElectrical Linewidth Measurements to Silicon LatticeParameters Using HRTEM,” IEEE Transactions onSemiconductor Manufacturing, Vol. 16, No. 2, pp. 239-248 (01-MAY-2003)

R. A. Allen, M. W. Cresswell, L. W. Linholm, “Junction-Isolated Electrical Test Structures for Critical DimensionCalibration Standards,” 2003 ICMTS IEEE InternationalConference on Microelectronic Test Structures, March17-20, 2003, Monterey, California, pp. 3-7 (31-MARCH-2003)

J. von Hagen, H. A. Schafft, “Temperature DeterminationMethods on Copper Material for Highly AcceleratedElectromigration Tests (e.g. , SWEAT),” 2002 IEEEInternational Integrated Reliability Workshop FinalReport, 2002 Integrated Reliability Workshop, Oct. 21-24, 2002, Lake Tahoe, California, pp. 45-49 (01-FEB.-2003)

H. A. Schafft, J. R. Lloyd, “Electromigration DiscussionGroup Summary,” 2002 IEEE International IntegratedReliability Workshop Report, 2002 IEEE InternationalIntegrated Reliability Workshop, Oct. 21-24, 2002, LakeTahoe, California, pp. 204-206 (01-FEB.-2003)

H. A. Schafft, L. M. Head, J. Gill, T. D. Sullivan, “EarlyReliability Assessment Using Deep Censoring,”Microelectronics Reliability, Vol. 2003, No. 43, 16 pp.(01-JAN.-2003)

N. Guillaume, M. Lahti, M. W. Cresswell, R. A. Allen, L.W. Linholm, M. E. Zaghloul, “Non-contact ElectricalCritical Dimensions Metrology Sensor for ChromePhotomasks,” Proc. Intl. Soc. for Optical Engineering(SPIE), 21st Annual BACUS Symposium on PhotomaskTechnology, Oct. 02-05, 2001, Monterey, California,Vol. 4562, pp. 822-829 (01-OCT.-2002)


METROLOGY FOR SYSTEM-ON-A-CHIP (SOC)GOALS

The goal of the project is to develop solutions tokey metrology issues confronting the semiconduc-tor System-on-a-Chip (SoC) industry. These in-clude development of measurement methods andstandards for characterizing embedded-sensor (ES)virtual components (ES-VCs), a critical class ofbuilding blocks from which SoCs are developed.The goal of this project is to promote and supportthe development of hardware and software stan-dards for specifying ES-VCs compatible with theSoC integration methodology used for digital ICdesign.

This NIST effort will enable ES-VCs to be includedin SoC computer-aided design (CAD) libraries andenable integration of ES-VCs with the existingdigital VCs used ubiquitously by industry todesign large ICs. The methods and standardsdeveloped as a result of this work will be essentialfor the realization of integrated, smart, low-cost,homeland security and environmental sensorsystems.

One focus is on delivering standards to facilitatethe incorporation of multi-technology (MT) VCs,including MEMS-based VCs, into SoCs. Theproject activities include: multi-technologyhardware description language (HDL) modeldevelopment, VC interface standards, synthesisand scaling standards for ES-VCs compatible withdigital methodologies, and testing standards andverification standards. The NIST MEMS-basedintegrated gas-sensing VC will be used as a testbed to demonstrate the viability of these standards.In addition, the demonstration of general purposegas-sensing VC methodologies will be used tofacilitate the adoption of these MT-VCs into newhomeland security and industrial applications.

CUSTOMER NEEDS

The driving force in today’s semiconductor indus-try is the need to maintain a rate of performanceimprovement of 2x every two years in high-perfor-mance components. Historically, these improve-ments have relied exclusively on advances madeby semiconductor miniaturization technology. The2003 International Technology Roadmap for Semi-conductors (ITRS) suggested that, “innovationsin circuit design and architecture will be needed todesign chips with both the desired performanceand power dissipation.” Achievement of this ad-vancement in circuit and system design techniques

is increasingly becoming dependent on integrat-ing multiple technologies into a single chip referredto as System-on-a-Chip (SoC). The design chal-lenges for SoC devices will be overcome with theuse of platform-based design approaches thatemphasize design reuse (e.g., the development ofES-VCs that can be used as cost-effective build-ing blocks for SoC devices).

The direct customers for this infrastructure buildingwill be the makers of system design software,companies manufacturing ES-SoCs, and systemsdesigners.

An October 20, 2003, article entitled “SoCCreation Requires Rules” written by Thomas L.Anderson, EE Times, states “While EDA vendorsmay provide detailed instructions andmethodology guides for their specific tools, therehas not been much industry activity inestablishing more general rules, guidelines andbest practices.”

TECHNICAL STRATEGY

1. To develop ES-VCs for SoC design methodologysuccessfully, the first step in this multi-stepprocess is to develop the ability to produce theES-VC devices via a standard CMOS compatibleprocess. To demonstrate this capability we havechosen a MEMS microhotplate-based ES-VC,including operational amplifiers, decoders, and ananalog-to-digital converter (ADC) to process thedata.

DELIVERABLE: Develop post processing technologythat will enable the microhotplate to scale to standardsubmicron mixed signal IC foundry processes.

2. The second step in making the ES-VC is to makeit compatible with the digital SoC designmethodology. This approach will require the ES-VC to have digital interface circuitry and to haveDesign-for-Test (DFT) and Built-In-Self-Test (BIST)functionality features. To facilitate this approachwe will develop methodologies and standards foradding digital shells to ES-VCs and demonstratethem on the gas sensor VC described above.

DELIVERABLE: Develop methodologies for designingdigital interface shells, develop DFT and BISTfunctionality for ES-VCs, and demonstrate theirviability via the NIST microhotplate gas sensortechnology.

3. The predominant design approach used byindustry for SoC devices is top-down design. This

Technical Contact:Allen R. Hefner, Jr.

Staff-Years (FY 2004):.75 professional

1.75 guest researchers


requires that high-level HDL models exist for theVCs that are candidates for use in any particularsystem of interest. Compared to those for digitalVCs, the methodology and standards fordeveloping high-level models for ES-VCs are atbest poorly developed. To address this need, high-level models are being developed for ES-VCsusing Analog and Digital HDLs, andmethodologies are being developed to validate themodels.

DELIVERABLE: Develop methodologies and standardsfor developing high-level models for ES-VCs anddemonstrate their viability via the NIST micro hotplategas sensor technology.

4. After the high-level simulation of the system inthe top-down design process is successfully com-pleted, the next step is to synthesize the individu-al VCs. Compared to those for digital VCs, themethodology and standards for ES-VC synthesisare at best poorly developed. To address the needfor synthesizing ES-VCs, we are developing stan-dards and metrologies for a non-digital synthesislike process that is compatible with digital synthe-sis. This process is based upon libraries of exist-ing designs and the device design equations.

DELIVERABLE: Develop Gas Sensor SoC systemarchitecture utilizing the ES-VC and synthesizesystem design demonstrating viability of ES-SoCmethodology.

5. The testability of ES-VCs represents anothersignificant challenge since standards and meth-odologies for non-digital circuits do not exist. Themost promising approach to address testability isto use BIST techniques. To facilitate this approach,we will develop methodologies and standards foradding BIST to ES-VCs and interface them via thedigital shell.

DELIVERABLE: Develop test bed for evaluation of gassensor VC built-in self test function demonstratingDFT requirements for ES-SoC design methodology.

ACCOMPLISHMENTS

# A monolithic micro-gas-sensor system wasdesigned and fabricated in a standard CMOS pro-cess. The gas-sensor system incorporated an ar-ray of four microhotplate-based gas-sensing struc-tures. The system utilized a thin film of tin oxide(SnO2) as a sensing material. The interface circuit-ry on the chip has digital decoders to select eachelement of the sensing array and an operationalamplifier to monitor the change in conductance ofthe film. The chip is post-processed to create mi-crohotplates using bulk micro-machining tech-niques. Detection of gas concentrations in the

100 parts-per-billion range was achieved. This rep-resents a factor of 100 improvement in sensitivitycompared to existing MEMS-based microhotplategas sensors.

Micrograph of gas-sensor system to be used asdemonstration vehicle.

Layout of the four element gas sensor VC with analog-to-digital control.

# A monolithic CMOS four element gas sensorVC was designed and submitted for fabrication.The design includes both analog and digitalintegrated circuits. The digital part of the circuithas an 8-bit analog-to-digital converter (ADC). Theobjective of the design is to make it compatiblewith the SoC design methodology.

# The four element gas sensor VC was electri-cally characterized. The performance of the 8-bitADC superceded the gas sensor VC design re-quirements.


Layout of the four element gas sensor VC withelectrostatic discharge (ESD) protection circuitry.

New microhotplate test structures layout.

# An initial design of a four element gas sensorVC with electrostatic discharge (ESD) protectionwas implemented in 1.5 micron standard CMOStechnology.

# New microhotplate test structures were de-signed and fabricated to improve thermal efficien-cy and their feasibility to be fabricated in the CMOSsub-micron technology.

FY OUTPUTS

COLLABORATIONS

University of Maryland, Metrology for multi-technologySystem-on-a-Chip (SoC)

RECENT PUBLICATIONS

M. Y. Afridi, A. R. Hefner Jr., D. W. Berning, C. H.Ellenwood, A. Varma, B. Jacob, S. Semancik, “MEMS-based Embedded Sensor Virtual Components for SoC,” SolidState Electronics, Vol. 48, pp. 1777-1781 (24-JUN-2004)

M. Y. Afridi, A. R. Hefner Jr., D. W. Berning, C. H. Ellen-wood, A. Varma, B. Jacob, S. Semancik, “MEMS-basedEmbedded Sensor Virtual Components for SoC,” 2003International Semiconductor Device Research Symposium,pp. 500-501 (25-NOV-2003)

M. Y. Afridi, J. S. Suehle, M. E. Zaghloul, D. W. Berning,A. R. Hefner Jr., R. E. Cavicchi, S. Semancik, C. B.Montgomery, C. J. Taylor, “A Monolithic CMOSMicrohotplate-based Gas Sensor System,” IEEE SensorsJournal, Vol. 2, No. 6, pp. 644-655 (01-DEC-2002)


POWER SEMICONDUCTOR DEVICE AND THERMALMETROLOGYGOALS

The goals of the project are to (1) develop electricaland thermal measurement methods and equipmentin support of the development and application ofadvanced power semiconductor devices and (2)develop advanced thermal measurements forcharacterizing integrated circuits (ICs) and devices.

David Berning measuring silicon carbide diodes usingNIST-developed, specialized equipment. CopyrightRobert Rathe

Technical Contact:Allen R. Hefner, Jr.

Staff-Years (FY 2004):2.25 professionals3.25 guest researchers

“In 2004, Dr. Calvin

Carter of Cree Inc.

received the US National

Medal of Technology

from President George

W. Bush for: ‘his excep-

tional contributions to the

development of Silicon

Carbide wafers, leading

to new industries in wide

band-gap semiconduc-

tors and enabling other

new industries in … more

efficient/compact power

supplies, and higher

efficiency power distribu-

tion/transmission

systems.’”

CUSTOMER NEEDS

There are significant technical requirements formore efficient, higher voltage power semiconductordevices. The application needs range from moreefficient power supplies for computers andconsumer appliances, to electric automobile powerconverters, to more efficient long distance highvoltage power transmission. Rapid technicaladvances are occurring in the development of newpower semiconductor materials and designs toaddress these needs. With the introduction ofthese new materials and designs comes newrequirements for characterizing the performanceand reliability of the fabricated devices.

The most exciting, and potentially revolutionary,development in this area is the rapid progress inthe development of wide band-gap semiconductormaterials for power semiconductor devices. Wideband-gap semiconductors such as silicon-carbide(SiC) have long been envisioned as the material of

choice for next-generation power devices. Recentadvances in single crystal SiC and fabricationtechnology have ushered in a new era of wideband-gap power semiconductor devices. This hasled to the introduction of SiC power Schottky diodeproducts in the 400 V to 1200 V range and led tothe development of High-Voltage, High-Frequency(HV-HF) power devices with 10 kV, 15 kHz powerswitching capability.

Several industry and government programs arecurrently underway to accelerate the developmentand application insertion of SiC powersemiconductor devices. The goal of the DARPAWide-Band-gap Semiconductor Technology HighPower Electronics Program (WBST-HPE) is todevelop half-bridge modules with 15 kV, 110 A,20 kHz capability in the next few years. Theemergence of HV-HF devices with such capabilityis expected to revolutionize utility and militarypower distribution and conversion by extendingthe use of Pulse Width Modulation (PWM)technology, with its superior efficiency and controlcapability, to high voltage applications.

The Electric Power Research Institute (EPRI) alsoidentified the benefits of HV-HF semiconductortechnology, which include advanced distributionautomation using solid-state distributiontransformers with significant new functionalcapabilities and power quality enhancements. Inaddition, HV-HF power devices are an enablingtechnology for alternative energy sources andstorage systems. The emergence of HV-HF powerdevices presents unique challenges in metrologyand specification of device electrical and thermalrequirements.

While overcoming thermal limitations has alwaysbeen at the forefront of power semiconductortechnology, this has only come to the fore recentlyin CMOS-based microelectronic circuits. The majorissues include: (1) power levels in CPUs havereached the same levels as in power devices; (2)power density nonuniformities are leading to hotspots in microprocessors as well as power ICs; (3)new materials with different thermal properties arebeing introduced; (4) many new and futuretechnologies (e.g., SOI, 3-D integration) tend toisolate power dissipating elements thermally; and(5) shrinking dimensions and increasing frequencyof ICs are causing significant power dissipation in


the interconnects. In order to address these issues,reliable methods for measuring the temperaturedistribution in ICs and power devices are required.

TECHNICAL STRATEGY

The strategy is to support the measurement infra-structure of the semiconductor industry by devel-oping and evaluating measurement methods andtechniques where suitable ones do not exist forcharacterizing critical electrical and thermal prop-erties of devices and ICs. This includes electrical,thermal, and safe operating limit characterization,establishing performance metrics, and developingmethods for extracting device model parametersto aid in application insertion. NIST is taking alead role in developing the device metrology andperformance metrics necessary for both the DAR-PA and EPRI efforts and the new industries envi-sioned by these programs. NIST is also pioneer-ing electrical and thermal measurement methodsfor HV-HF devices and advanced thermal metrolo-gy for high density ICs.

PERFORMANCE, RELIABILITY, ANDAPPLICATION CHARACTERIZATION FORDARPA-WBST-HPE DEVICES ANDMODULE PACKAGES

A major driving force spearheading the develop-ment of HV-HF power devices is the ongoingDARPA WBST-HPE program focused on devel-oping the technology deemed necessary to en-able Solid State Power Substations (SSPS) for fu-ture Navy warships. Current distribution ap-proaches being considered for the next genera-tion of aircraft carriers and destroyers employ a13.8 kV AC power distribution that is stepped downto 450 V AC by using large (6 ton and 10 m3) 2.7MVA transformers. Substantial benefits in powerquality enhancement, advanced functionality, size,and weight are anticipated by replacing this trans-former with an all solid state design. NIST playeda key role in WBST-HPE Phase 1 and has beenselected to be the exclusive device and packageevaluation and metrology lab for the $50 M Phase2-3 program for 2005 through 2008.

METROLOGY FOR MAPPING SIC POWERBIPOLAR DEVICE DEGRADATION

Although significant progress has been made inimproving the quality of the SiC starting materialand the fabricated devices, a major concern forbipolar structures is an observed degradation inthe electrical characteristics over time. The degra-dation occurs from latent defects such as Basel

“[The Project] …

continues to lead

industry needs by

providing state-of-the-art

capability for the

measurement of unique

power device character-

istics at critical operating

conditions.”

NRC Panel Report, AnAssessment of the NationalInstitute of Standards andTechnology Measurementand Standards Laboratories:Fiscal Year 2003

Plane Dislocations that result in the formation andgrowth of stacking faults activated by excess car-rier recombination. The defects cause severe cur-rent nonuniformities to occur, resulting in on-statevoltage, switching, and thermal performance deg-radation.

DELIVERABLE: Develop automated stress anddegradation monitoring systems to assess degradationof SiC devices after 10,000 hours of operation.

DELIVERABLE: Utilize NIST one-of-a-kind high speedthermal image measurements to characterize SiCpower diode conduction uniformity performancebefore and after stress conditions and correlateresults with light emission stacking faultmeasurements (with NRL).

METROLOGY FOR NONDESTRUCTIVESWITCHING FAILURE

Power devices undergo their greatest electro-ther-mal stress under switching conditions. There area number of known catastrophic failure mechanismsthat occur as a device is switched off with an in-ductive load. NIST has developed a nondestruc-tive system to test for the failure limits under in-ductive switching, has done extensive research onSi device failure limits, and will extend that work toinclude SiC power devices.

DELIVERABLE: Perform unclamped inductiveswitching measurements for SiC MOSFETs and IGBTsproduced by DARPA WBG program.

CIRCUIT SIMULATOR MODELS FOR SICPOWER SWITCHING DEVICES

Parameter extraction is a critical component in de-veloping and using device models in circuit andsystem simulations and in establishing perfor-mance benchmarks for new device technologies.For new devices, not only must new models bedeveloped, but methods must be modified and newones developed for extracting the parameters forthe models.

DELIVERABLE: Utilize NIST IMPACT model parameterextraction tools to characterize SiC power MOSFETsand IGBTs introduced by the DARPA WBST-HPEprogram.

DEVELOP THERMAL METROLOGY FORPOWER SEMICONDUCTOR PACKAGE ANDCOOLING SYSTEM

The cooling systems for power electronic devicesand modules are often quite sophisticated andcomplex. In evaluating the efficiency and effec-tiveness of cooling systems, it is critical to be ableto measure the temperature of a packaged chipaccurately during actual operation. This means


that temperature measurement methods are need-ed that use a chip electrical parameter as the ther-mometer. Also, validated electro-thermal devicemodels are needed to speed the system design.New HV-HS semiconductor devices present newpackaging challenges and technologies that mustbe evaluated for high temperature performance,die attack voiding, and thermal cycling capability.

DELIVERABLE: Perform thermal cycling and thermalshock experiments on DARPA WBST-HPE programdevices. Use unique NIST high current IGBT TSPsystem and high speed thermal imaging system toidentify die attach and DBC integrity before and afterthermal stress.

HIGH-SPEED THERMAL IMAGEMICROSCOPY FOR ON-CHIP TEMPERATURE

A limitation of commercially available infrared (IR)thermal imaging systems is their inability to makehigh speed transient measurements. NIST hasmodified a commercial IR system to be able to makesuch high speed temperature maps of a devicesurface with a better than 1 µs time resolution anda spatial resolution of about 15 µm to 20 µm.Current work involves enhancing the performanceand applicability of this unique test method andexploring the potential for addressing criticalmetrology issues in advanced digital integratedcircuits and power devices.

DELIVERABLE: Develop procedure for coating chipswith thin high emissivity paint and characterize theperformance for high speed IR thermal metrology.

DELIVERABLE: Apply high speed thermal imagingsystem to characterize the performance of advanceddigital integrated circuits including dynamic thermalperformance enhancement (with UMD).

ACCOMPLISHMENTS

# Extended capabilities of IMPACT parameterextraction software. The capabilities of theparameter extraction software, IMPACT, wereextended to include MOSFETS (in addition toIGBTs) and three polytypes of SiC material (inaddition to Si). This was done in collaboration withthe University of Puerto Rico, Mayaguez, and twoSURF (Summer Undergraduate Research Fellow)students.

# High voltage curve tracer and reverserecovery systems. The development of a 25 kVvariable pulse width curve tracer for both 2 and 3terminal devices was completed. Safety protectionand an interlock system have been tested andqualified. A high voltage reverse recovery testsystem with 3 kV, 15 A capability was alsodeveloped. These systems are critical components

in the SiC power semiconductor device metrologytasks.

# Chip temperature measurements for powermultichip modules. Developed test system andprocedures for thermal characterization ofIntegrated Power Electronic Module (IPEM) anddeveloped electro-thermal model and validation forIPEM. Applied this new measurement andmodeling method to commercial high power IGBThalf bridge module, commercial six pack IGBTmodule, and prototype NSF Center for PowerElectronic Systems IPEM.

# High speed transient infrared thermalimaging system. The high-speed transient imagingcapability has been extended to include a burstmethod. This feature has been found to be veryuseful in measuring current uniformity of SiC powerdevices before and after degradation withoutdegrading the device during the measurement.

# Played a major role in planning andevaluating progress of DARPA Wide BandgapPower Device program. Developed the metrology,measured device deliverables to government fromDARPA contractors, and used NIST data toprovide assessment of program to DARPA director.

# Initiated new program with EPRI to developsolid state power distribution transformers usingultra high voltage semiconductor devices. Thegoal is to replace all existing power distributiontransforms with Intelligent Universal Transformersthat provide better control of the power grid,provide power factor correction at point of use,improve power quality, and enable plug-and-playinsertion of alternate energy sources. NIST aidedin mapping existing power semiconductortechnologies for this application and inestablishing an EPRI road map for development ofultra-high-voltage semiconductor devices.

# Played a major role in initiating andplanning a new DARPA/Navy SiC shipboardpower distribution program. The programinvolves insertion of power distributiontechnologies enabled by ultra-high-voltagesemiconductor devices into next generation moreelectric Navel carrier, destroyer, and submarineplatforms.

# Completed development of SiC powerMOSFET model and completed development ofIMPACT extraction tools for SiC power devicemodel parameter extraction. Performed parameterextraction for SiC MOSFETs produced by DARPAWBG program and validated simulations.


FY OUTPUTS

COLLABORATIONS

Avanti Inc., Parameter extraction for IGBT librarycomponent models

Avanti Inc./University of Arkansas, SiC power devicemodeling

Avanti Inc./UPRM, Characterization and modeling ofelectronic packages for thermal model library componentmodels

NIST Division 812, Electronic Materials CharacterizationProject/Advanced MOS Device Reliability andCharacterization Project, Benchmarks for quantum-mechanical device simulation

NIST/CREE, Development of SiC MOSFET electro-thermal model

Participants for DARPA contract (including NRL, ARL,Virginia Tech, CREE, University of Arkansas, Rockwell,etc.), Wide bandgap power device program

Rockwell Science Center/NIST, Development of SiCtransistor models

University of Maryland, Metrology for multi-technologySystem-on-a-Chip (SoC)

Virginia Polytechnic Institute and State University, SiCpower device utilization

EXTERNAL RECOGNITION

Allen R. Hefner, elected IEEE Fellow “for contributionsto the theory and modeling of power semiconductordevices”

RECENT PUBLICATIONS

R. Singh, A. R. Hefner Jr., “Reliability of SiC MOSDevices,” Journal of Solid-state Electronics, Vol. 48, No.10-11, pp. 1717-1720 (24-JUNE-2004)

T. R. McNutt, A. R. Hefner Jr., A. Mantooth, J. Duliere,D. W. Berning, R. Singh, “Silicon Carbide PiN and MergedPiN Schottky Power Diode Models Implemented in theSaber Circuit Simulator,” IEEE Trans. Power Electronics,Vol. 19, No. 3, pp. 573-581 (01-MAY-2004)

D. W. Berning, J. V. Reichl, A. R. Hefner Jr., M. Hernandez,C. H. Ellenwood, J. Lai, “High Speed IGBT ModuleTransient Thermal Response Measurements for ModelValidation,” Proc., IEEE Industry Applications Society(IAS) Annual Meeting, Oct. 12-16, 2003, Salt Lake City,Utah, pp. 1826-1832 (12-OCT.-2003)

X. Huang, P. Elton, J. Lai, A. R. Hefner Jr., D. W. Berning,S. Chen, T. Nehl, “EMI Characterization with ParasiticModeling for a Permanent Magnet Motor Drive,” Proc.,IEEE Industry Applications Society (IAS) Annual Meeting,Oct. 12-16, 2003, Salt Lake City, Utah, pp. 416-423(12-OCT.-2003)

T. R. McNutt, A. R. Hefner Jr., A. Mantooth, D. W.Berning, S. Ryu, “Silicon Carbide Power MOSFET Modeland Parameter Extraction Sequence,” Proc., PowerElectronics Specialist Conference, Power ElectronicsSpecialist Conference, Acapulco, Mexico, 10 p. (11-JUNE-2003)

R. Singh, K. G. Irvine, D. C. Capell, J. T. Richmond, D. W.Berning, A. R. Hefner Jr., J. W. Palmour, “Large Area,Ultra-high Voltage 4H-SiC PiN Rectifiers,” IEEE Trans.Electron Devices, Vol. 49, No. 12, pp. 2308-2316 (01-DEC.-2002)

R. Singh, D. C. Capell, A. R. Hefner Jr., J. Lai, J. W.Palmour, “High-Power 4H-SiC JBS Rectifiers,” IEEETrans. Electron Dev., Vol. 49, No. 11, pp. 2054-2063(01-NOV.-2002)

J. J. Rodriguez, J. V. Reichl, Z. R. Parrilla, A. R. Hefner Jr.,D. W. Berning, M. Velez-Reyes, J. Lai, “ThermalComponent Models for Electro-Thermal Analysis ofMultichip Power Modules,” Proc., 2002 IEEE IndustryApplication Society, IEEE Industrial Applications SocietyMeeting, Oct. 13-18, 2002, Pittsburgh, Pennsylvania,pp. 234-241 (24-OCT.-2002)



Technical Contact:Michael Gaitan

Staff-Years (FY 2004):4.5 professionals1.0 post doc4.75 guest researchers

GOALS

The MicroElectroMechanical Systems (MEMS)Project works to apply micro and nanofabricationtechnologies (MNT) to advance the state of theart of single molecule measurements, single cellmeasurements, and DNA separations for forensicapplications. In addition, we support domesticand international MEMS standardization byworking with standards groups to develop andprovide the MEMS industry with test structures,test methods, measurement standards, andstandard manufacturing practices.

CUSTOMER NEEDS

MEMS technology continues to mature, resultingin growing opportunities for U.S. industry, whichin turn results in an increasing need for measure-ment standards and also for new opportunities forresearch. Our project aligns its new efforts withNIST’s core mission and with NIST’s strategic fo-cus areas in biosystems and health, and nano-technology. As a result, the MEMS Project hasdeveloped four main focus areas: single moleculemeasurements, bioelectronics, DNA separationsfor forensic applications, and MEMS standardiza-tion.

SINGLE MOLECULE MANIPULATION ANDMEASUREMENT

The biotechnology and healthcare industries re-quire measurements of large sample arrays as partof their combinatorial approach to disease recog-nition and drug development. For example, manu-facturers of technologies such as DNA and pro-tein arrays are striving to make larger arrays thatcan more efficiently support larger combinatorialmeasurements. As the size of the sensors is de-creased, the sample size (and hence the number ofmolecules in the sample) also decreases. Sincebiological molecules are expected to have varia-tion in their behavior, a question arises concern-ing whether the statistical variation of biologicalmolecules will affect the accuracy of those mea-surements; e.g., is there a minimum sample sizethat is required to yield a result that is comparableto traditional ensemble measurements. The abili-ty to measure the structure and function of singlebiomolecules will yield the statistical behavior oftheir large populations.

BIOELECTRONICS

Our vision of bioelectronics is interfacing integrat-ed circuit technologies to biological systems. Ex-periments in cell biology have been virtually un-changed for many decades, involving manual han-dling of cell culture flasks, changing the cell media(feeding the cells), exposing the cell culture to acompound of interest, and observing cell responseand viability using a microscope. For this reason,cell biology experiments are typically very timeconsuming and labor intensive. Recently, the trendhas been to conduct studies that involve largearrays of small cell cultures by automating thesesteps as much as possible using robotic instru-mentation, but the experiments are still essentiallythe same. A true paradigm shift is to utilize micro-and nanofabrication technologies to perform theseexperiments on single cells or small cell clusters incontinuous flow microfluidic systems with inte-grated microsensors and MEMS.

Prototype 16 channel device for DNA fingerprinting.


DNA SEPARATIONS FOR FORENSICAPPLICATIONS

The Department of Justice recognizes an urgentneed to improve the efficiency, speed, and accura-cy of DNA testing in order to alleviate a growingbacklog of forensic DNA testing for criminal cas-es. Results of DNA testing have become a criticalcomponent of criminal investigations and are of-ten used as evidence in court proceedings. NISThas played a key role in the validation and stan-dardization of forensic DNA testing protocols overthe past decade that has facilitated a growing ac-ceptance of this type of analysis for criminal in-vestigations.

Microfluidic technology is a promising alternativeto current capillary-based techniques due to itsgreat potential to miniaturize, simplify, integrate,automate, and multiplex the analysis with higherthroughput and speed. This technology has al-ready shown that it is the next revolution in DNAtechnology, with analysis often complete in tenpercent of the time required for more traditionalcapillary technology. Although DNA analysissystems based on microfluidics technology havebeen recently commercialized, these systems donot meet the specific needs of the forensic com-munity due to poor separation resolution of therelatively long fragments (on the order of 100 bpsto 400 bps) as well as incompatibility with the stan-dard test procedures.

MEASUREMENTS AND STANDARDS FORMEMSMEMS is a rapidly growing technology with aforecasted annual growth rate that exceeds that ofthe semiconductor electronics industry as a whole.Manufacturers of MEMS products, such asacceleration sensors for automotive air bags anddeformable mirror displays for video projection,are producing these devices in Integrated Circuit(IC) manufacturing lines. This integration of mixedtechnologies is part of the semiconductorindustry’s revolution toward “system-on-a-chip.”System-on-a-chip links the functionality of the IC(an information processor) with informationgathering (sensing the environment) and actuation(acting on decisions). New test structures, testmethods, and standards are required for devicecharacterization to improve manufacturing anddesign.

In support for the need of measurement standardsfor MEMS, the project is working with ASTM TaskGroup E08.05.03 on Structural Films for MEMS and

Electronic Applications. This task group has un-dertaken sponsorship of a round robin experimentfor measuring in-plane length, residual strain, andstrain gradient. MEMS test structures used inthese experiments are designed and then fabricatedon a test chip that is passed among participatinglaboratories. These dimensional and film proper-ties are important to the fabrication of MEMS de-vices. Participation in the ASTM Task Group givesNIST a leadership role in the development of mea-surement standards for the industry.

The MEMS Project is also working with SEMI’snew MEMS Materials Characterization Task Forceto develop standardization for MEMS technology.Our prime effort with this group is working tosupport the development of compact models forMEMS devices that can accurately simulate theirresponse in advanced circuit simulators.

MEMS test structures have applications tomeasuring the mechanical properties of thin filmsin ICs, a need identified in the InternationalTechnology Roadmap for Semiconductors. As ICdevices continue to shrink, thermo-mechanicalstress in the thin films that interconnect them is anever-increasing reliability concern. Current state-of-the-art IC technology uses five or moreinterconnect layers with aspect ratios (height/width) that can exceed 1.8. Despite the increasingnumber of interconnect layers in IC technology,existing stress determination and modeling studieshave been limited to single level metallization, withfew exceptions. This is due, in large part, to thelack of experimental techniques for measuring strainin narrow line widths (less than 10 µm) and inmultilayer structures.

MEMS-based IC test structures allow, for the firsttime, the measurement of strain in multilayerstructures in fully fabricated ICs. Thesemeasurements can be used to characterize themechanical stress in these multilayer films. Resultscan then be used to verify finite element models ofthe stress in the films and to correlate mechanicalstress data with reliability testing. MEMS-basedtest structures being developed in this project offernew ways to characterize the mechanical stress inmultilayer films.

TECHNICAL STRATEGY

NanoBioTechnology is a new and rapidly growingfield that is focused on the development of nano-technology for biomedical research and applica-tions. The Semiconductor Electronics Divisionsees a new opportunity for the application of nano-


fabrication methods to create structures to probebiological systems at the single cell and singlemolecule level. The top-down nanofabricationmethods that have been developed by the semi-conductor electronics industry can be coupled withbottom-up self-assembly techniques to create newtools to probe life’s processes. We believe thatthe ability to measure the behavior of individualcells or biological molecules, which are tradition-ally characterized by ensemble measurements, willprovide fundamentally new information about howthose biological processes work. We have threemain focus areas in our nanobiotechnology ef-fort: Single Molecule Manipulation and Measure-ment (SM3), where we seek to develop new toolsto probe the structure of DNA electronically andoptical methods to characterize the structure andconformations of proteins; Bioelectronics, wherewe seek to sense single cell behavior electrochem-ically; and DNA separations for forensic applica-tions, where we seek to develop a plastic-basedmicrofluidic device that will decrease the time toperform a separation at a lowered cost. Our workis carried out with multidisciplinary teams that spanlaboratories within NIST and the National Insti-tutes of Health.

SINGLE MOLECULE MANIPULATION ANDMEASUREMENT

The semiconductor electronics industry hasdriven the development of fabrication tools thatare capable of patterning structures that are smallerthan cellular dimensions (i.e., on the order of100 nm). In combination with micromachiningmethods developed by MEMS research, it ispossible to create three-dimensional structuresthat are commensurate with the size ofbiomolecules. We will utilize nanofabricationmethods and enhanced surface coatings todevelop novel solid-state structures for the controland manipulation of single biomolecules. Thesemethods will be based on electrofluidic,electromechanical, optical, and magnetic transportof biomolecules in confined nanometer-scaleenvironments.

Interactions of single molecules with nanoscalemechanical structures, restriction elements, andother single molecules will be probed by electron-ic, electromechanical, and optical techniques. Theeffort will result in a well-characterized SM3 plat-form integrated with AFM, FRET (FluorescenceResonance Energy Transfer), optical microscopy,and electronics, thereby enabling a wide varietyof single-molecules studies. DNA structure deter-mination will be performed by directly interrogat-

ing ordered bases as they are threaded through awell-characterized nanopore.

DELIVERABLE: Develop a platform that integratesnanometer-scale fluidic restrictions, fluidic networks,switches, and workstations that support theelectronic and optical control and measurement ofsingle molecules of DNA and RNA.

BIOELECTRONICS

Recent scientific reports describe the ability tostimulate electronically and probe single cellactivity and to transport, sort, and position singlecells. These capabilities have resulted in significantadvances in biological sciences and medicine. Anexcellent example is patch clamp technology thathas revolutionized the field of electrophysiology.Advances in microfabrication methods haverecently led to the development of patch clamparrays and other automated on-chip techniques;however, the widespread adoption of more complexintegrated systems for biologically relevantmeasurements continues to face technologicalhurdles. These include complicated materialsintegration issues (maintaining a biocompatibleenvironment for cells within the in vitromeasurement systems, developing stable and drift-free electrodes for accurate measurements, invariedbuffer solutions, etc.), the difficulty of accuratelydetermining the electrical/electromagneticresponse of integrated electronic/MEMS/fluidicsystems, and issues related to reproduciblefabrication of integrated devices. By addressingthese critical measurement infrastructure needs,NIST will accelerate the development of powerfulnew bioelectronic platforms and techniques.

Our technical approach is to integrate microelec-tronic, MEMS, and microfluidic systems with cellsin order to achieve a new level of control over theelectronic/biological interfaces under study. Wewill develop methods to adhere and grow cells indefined patterns in a biological hybrid in vitroenvironment that incorporates microelectronic cir-cuits, both electrochemical and RF, to stimulateand sense cell activity. Microchannel networkswill be used to transport the biological specimensto exact locations and to deliver precise amountsof chemicals or drugs to the local cellular environ-ment. These techniques will allow us to apply pre-cise electrical, electromagnetic, and chemical stim-ulation to the cells and to measure their metabolic,electrical, and physiological responses. We willfocus our initial research efforts on the study ofretinal (neuronal) cells and will later progress toother cell systems.


DELIVERABLE: Develop an array of micro-electrochemical cells and methods to pattern cells onthe array for single-cell electrochemicalmeasurements.

DNA SEPARATIONS FOR FORENSICAPPLICATIONS

Our team will draw on our extensive expertise inmicrofluidics, microfabrication, DNA separations,as well as state-of-the-art optics and detection tobuild a prototype system that can be used as amodel to demonstrate the advantages of applyingthese latest technologies for forensic identifica-tion. There are two overall requirements that mustbe satisfied to meet the needs of the Departmentof Justice: (1) development of a reliable, easy-to-use, high-throughput, microfluidics-based systemthat is smaller and faster than capillary-based tech-niques; and (2) validation of the system that wouldsupport the adoption of this technology by thejudicial system.

DELIVERABLE: Develop a breadboard microfluidicforensic DNA separation system for demonstration toforensic scientists.

MEASUREMENTS AND STANDARDS

The MEMS technical community, composed ofcompanies, universities, and government labora-tories, has developed many types of test struc-tures to characterize the fabrication process anddevice performance. The MEMS Project plays anactive role in ASTM Task Group E08.05.03 on Struc-tural Films for MEMS and Electronic Applicationsand in SEMI’s MEMS Materials CharacterizationTask Force to supply the community with stan-dardized test methods.

DELIVERABLE: Complete the round robin experimentfor in-plane length, residual strain, and strain gradientmeasurement standards to determine the precisionand bias of these measurements; incorporate theseresults in the ASTM MEMS standards for balloting.

IC INTERCONNECT CHARACTERIZATION

Micro-machining techniques, test structures, andtest methods are being developed to characterizethe stress, elastic modulus, and adhesion proper-ties in the thin films comprising ICs. These teststructures are fabricated in the standard IC pro-cess on fully fabricated ICs. Fixed-fixed beam andcantilever test structures with and without inter-connect layers are micro-machined in the fully pro-cessed IC. Measurements of deflection of buck-led beams give information on the strain in eachlayer. Measurements of mechanical resonance giveinformation on the elastic modulus of the films.

These test structures can also be integrated withmicro heating elements for accelerated testing.

DELIVERABLE: Develop a method based on the use ofan optical vibrometer to measure the resonantfrequencies of the various cantilevers in a CMOSprocess in order to extract the elastic modulus of thethin films with a higher degree of accuracy.

ACCOMPLISHMENTS

# Method to formulate liposome nano-cells (ornano-vials). A method has been developed to formliposome nano-vials in a continuous flow system.Microfluidics is used to elicit control over the spon-taneous self-assembly of liposomes from a solu-tion of dissolved phospholipids. In this work, wehydrodynamically focus a stream of lipid tinctureat a microchannel cross-junction between two aque-ous buffer streams. In a typical procedure, isopro-pyl alcohol (IPA) containing the dissolved lipidsplus a fluorescent dye (DiIC18) flows through thecenter inlet channel, and an aqueous phosphatebuffered saline solution flows through the two sideinlet channels. DiIC18 is a membrane-intercalatingdye that exhibits enhanced fluorescence whentrapped in a lipid membrane as compared to thefluorescence of the dissolved dye. The flow ratesof the IPA and buffer channels are adjusted to con-trol the degree of hydrodynamic focusing and thewidth of the center stream, thus controlling theIPA/buffer dilution process.

# Method to adhere retinal cells onmicropatterned polyelectrolyte multilayer (PEM)lines adsorbed on poly(dimethylsiloxane)(PDMS) surfaces using microfluidic networks.PEMs were patterned on flat, oxidized PDMSsurfaces by sequentially flowing polyions througha microchannel network that was placed in contactwith the PDMS surface. Polyethyleneimine (PEI)and poly(allylamine hydrochloride) (PAH) were thepolyions used as the top layer cellular adhesionmaterial. The microfluidic network was lifted offafter the patterning was completed and retinal cellswere seeded on the PEM/PDMS surfaces. Thetraditional practice of using blocking agents toprevent the adhesion of cells on unpatterned areaswas avoided by allowing the PDMS surface toreturn to its uncharged state after the patterningwas completed. The adhesion of rat retinal cells onthe patterned PEMs was observed 5 h afterseeding. Cell viability and morphology on thepatterned PEMs were assayed. These materialsproved to be nontoxic to the cells used in this studyregardless of the number of stacked PEM layers.Phalloidin staining of the cytoskeleton revealed


no apparent morphological differences in retinalcells compared with those plated on polystyreneor the larger regions of PEI and PAH; however,cells were relatively more elongated when culturedon the PEM lines. Cell-to-cell communicationbetween cells on adjacent PEM lines was observedas interconnecting tubes containing actin that werea few hundred nanometers in diameter and up to55 µm in length. This approach provides a simple,fast, and inexpensive method of patterning cellsonto micrometer-scale features.

# Method to create nanofluidic restrictions byelectroplating silver on micrometer scale pores.Electrodeposition of silver was investigated as afabrication tool for constricting large (103 µm2) viasin silicon substrates while leaving a small openingin the center of the via. Silver reduction fromammoniacal silver nitrate was studied at electrodesof novel geometry (i.e., the edge of the vias) withrespect to reduction potential, reduction pulsetype, and pulse duration. A variety of crystalnucleation and growth patterns was observed andcharacterized by scanning electron microscopy. Itwas found that electroplated silver occluded thevias to leave open areas of less than 1 µm2. Suchocclusions might be used as restrictions inmicrofluidics systems, forming a type of solid-statemicropore or nanopore.

# Cantilever test structures and an analysis toextract the elastic modulus from the measurementof their mechanical resonance were developed.These test structures are from IC thin films in fullyfabricated Complementary Metal-Oxide Semicon-ductor (CMOS) ICs. A test chip containing thenew cantilever test structure designs was fabri-cated on a commercial CMOS foundry throughthe MOSIS service. The test structures are siliconmicro-machined as a post process in order to re-lease them mechanically. These test structurescomplement the doubly clamped beam test struc-tures that have been developed and used to mea-sure the strain in CMOS films. The combinationof data from strain measurements and elastic mod-ulus measurements will enable the measurementof thin-film stress. Proof-of-concept thickness,resonant frequency, and Young’s modulus valueshave been obtained on three processing runs.

# Seven laboratories participated/areparticipating in the web-based ASTM length andstrain round robin experiment. This experimentis planned to be completed this coming year.Repeatability data has been obtained and, oncethe remaining reproducibility data are submittedto the round robin, the draft precision and bias

statements for the three standards can becompleted and the standards submitted forballoting. The MEMS terminology is also expectedto be balloted this coming year.

# NIST was awarded a patent on the inventionof a new type of accelerometer. The convectiveaccelerometer, as it is named in the patent, oper-ates on the principle that hot air rises. This devicediffers from the traditional MEMS-based acceler-ometers in that its operation is not based on asolid proof mass. The device consists of micro-heating elements and thermocouple sensorsseparated by a gap and placed in differential con-figurations. Thermocouple sensors measure thetemperature difference between the two sides ofthe microheater caused by the effect of accelera-tion on free convection in the surrounding gas.The devices show a small error in linearity of<0.5 % under tilt conditions from -90 °C to 90 °C,and <1.6 % under acceleration from 0 g to 8 g. Thesensitivity of the devices is a linear function ofheater power (temperature). A sensitivity of20 µV/g to 30 µV/g was measured for operatingpower between 35 mW and 45 mW. This inven-tion is a spin-off of research on MicromachinedPassive Microwave Components in CMOS Tech-nology that was sponsored by the U.S. Navy.

FY OUTPUTS

COLLABORATIONS

National Eye Institute of NIH, S. Patricia Becerra,Patterning neural (retinal) cells on surfaces to improvethe understanding and treatment of diseases associatedwith vision

Instrumentation Research and Development Group ofNIH, Paul Smith and Tom Pohida, Development ofoptical detection methods for forensic DNA separations

National Cancer Institute of NIH, David Robert, Liposomenano-vials for cancer detection and treatment

ASTM Task Group E08.05.03, Structural Films for MEMSand Electronic Applications

SEMI’s MEMS Materials Characterization Task Force

NIST Division 831, John Kasianowicz, Nano-pores forelectronic measurements of DNA structure

NIST Division 844, Lori Goldner and Angela Hight-Walker, Single molecule nano-vials

NIST Division 842, Kris Helmerson, Single molecule nano-vials

NIST Division 839, Laurie Locascio and Wyatt Vreelnad,Liposome Nanovials

University of Maryland/Georgia Tech, Measuring andmodeling bonding temperature rise



ASTM Task Group E08.05.03, round robin in progress todetermine the precision and bias of the 3 recently publishedMEMS standards (Janet C. Marshall)

SEMI’s MEMS Materials Characterization Task Force,working on bringing forward compact models for MEMSdevices for standardization (Janet C. Marshall)


Elected chair of the International Micromachine Summitto be held in Dallas, TX, in May 2005 (Michael Gaitan)

RECENT PUBLICATIONS

M. Gaitan, “Nanotechnology in Integrative Systems:Introduction to Integrative Systems,” Nanoscale Scienceand Technology, Kluwer Academic Press, pp. 373-388(17-AUG.-2004)

B. J. Polk, M. Bernard, J. J. Kasianowicz, M. Misakian,M. Gaitan, “Micro-Electroplating Silver on Sharp Edgesfor Fabrication of Solid-State Nanopores,” Journal of theElectrochemical Society, Vol. 151, No. 9, pp. C559-C566(11-AUG.-2004)

J. C. Marshall, E. M. Secula, J. Huang, “Round Robin forStandardization of MEMS Length and StrainMeasurements,” SEMI Technology Symposium:Innovations in Semiconductor Manufacturing, Jul 12-14, 2004, San Francisco, California, (12-JULY-2004)

D. R. Reyes, E. Perruccio, S. P. Becerra, L. E. Locascio,M. Gaitan, “Patterning Retinal Cells on PolyelectrolyteMultilayers,” The 7th International Conference onMiniaturized Chemical and BioChemical Analysis Systems(µTAS 2003), Oct 05-09, 2003, Squaw Valley, California,pp. 713-716 (18-FEB.-2004)

M. Gaitan, “Overview on CMOS MEMS FabricationTechniques and Applications,” Proceedings of 2001IMAPS, 2001 IMAPS, Oct 09-11, 2001, Baltimore,Maryland, pp. 1-6, (01-NOV.-2001)

S. Shuman, M. Gaitan, Y.K. Joshi, G.G. Harman, “WireBond Temperature Sensor,” Proceedings of 2001 IMAPS,2001 IMAPS, Oct 09-11, 2001, Baltimore, Maryland,pp. 344-349, (01-NOV.-2001)


NANOELECTRONIC DEVICE METROLOGY

GOALS

The overall goal of the Nanoelectronic DeviceMetrology (NEDM) Project is to develop the me-trology that will help enable new nanotechnolo-gies (such as Si-based quantum devices, molecu-lar electronics, and organic thin-film transistors)to supplement and/or supplant conventional Com-plementary Metal Oxide Semiconductor (CMOS)devices. This involves determining the criticalmetrology needs for these exploratory technolo-gies. One specific goal is to develop test struc-tures and methods to measure the electrical prop-erties of small ensembles of molecules reliably.Another targeted goal is to develop the precisemetrology and characterization methods requiredfor the systematic characterization of Si-basednanoelectronic devices. A third goal is to developan integrated and interdisciplinary suite of sophis-ticated measurement capabilities to enable corre-lations between organic electronic device perfor-mance and the structure, properties, and chemis-try of critical materials and interfaces.

Technical Contact:Curt A. Richter

Staff-Years (FY 2004):3.5 professionals0.5 technician3.5 guest researchers

Curt Richter loads a molecular electronic sample forelectrical characterization. Copyright Robert Rathe

CUSTOMER NEEDS

The CMOS FET (Field Effect Transistor), which isthe current basis of ULSI (Ultra-Large-Scale Inte-gration) circuits, is beginning to show fundamen-tal limits associated with the laws of quantum me-chanics and the limitations of fabrication tech-niques. The SIA’s International TechnologyRoadmap for Semiconductors (ITRS) shows noknown solutions in the short term for a variety oftechnological requirements including gate dielec-tric, gate leakage, and junction depth. Therefore,

it is expected that entirely new device structuresand computational paradigms will be required toaugment and/or replace standard planar CMOSdevices. Two promising beyond-CMOS technolo-gies that each take a very different fabrication ap-proach are molecular electronics and Si-basedquantum electronic devices. Molecular electron-ics is based upon bottom-up fabrication paradigms,while Si-based nanoelectronics are based upon thelogical continuation of the top-down fabricationapproaches utilized in CMOS manufacturing.These two approaches bracket the possible manu-facturing techniques that will be used to make fu-ture nanoelectronic devices. In addition, electronicdevices fabricated with organic materials form adramatically emerging technology targeting appli-cations (such as printable large-area displays,wearable electronics, paper-like electronic news-papers, low-cost photovoltaic cells, ubiquitousintegrated sensors, and radio-frequency identifi-cation tags) that are challenging to implement inconventional CMOS.

Molecular electronics (ME) is a field that manypredict will have important technological impactson the computational and communication systemsof the future. In ME systems, molecules performthe functions of electronic components. Researchand development for silicon-based nanoelectron-ics (e.g., Si-nanowire FETs, Si-based RTDs [reso-nant tunneling diodes], and silicon quantum dots)for the post-CMOS era are currently of interestdue to their inherent compatibility with CMOS tech-nology. Organic electronics is beginning to revo-lutionize the future of integrated circuits throughthe development of new applications that lever-age advantages in low-cost, high volume manu-facturing, nontraditional substrates, and designedfunctionality.

The NEDM Project is concerned with fundamen-tal research related to possible future devices thatwill replace or augment standard CMOS technolo-gy. In order to ensure that our research is techni-cally relevant, we plan to align ourselves with re-search alluded to in the SIA’s Roadmap and othersimilar semiconductor industry organizations anddocuments as well as that described by the Micro-electronics Advanced Research Corporation(MARCO).

The industry for these emerging nanoelectronicdevices will require reference data, standards,precision measurement methods, and standardized

“…there is no particular

reason why Moore’s law

should continue to hold:

it is a law of human

ingenuity, not of nature.

At some point, Moore’s

law will break down. The

question is when?”

Seth Lloyd, d’ArbeloffLaboratory for InformationSystems and Technology,Massachusetts Institute ofTechnology


test structures and associated measurementprotocols to develop into a viable commercialtechnology. The ultimate objective of this projectis to provide the measurement infrastructure toaid this development. Through strong ties withindustry leaders and cutting-edge researchers, weare accelerating the pace of our program andfocusing our research on the most relevanttechnologies.

TECHNICAL STRATEGY

The NEDM Project investigates and is develop-ing metrology for three specific areas of nanotech-nology: (1) Si-based quantum electronics, (2) mo-lecular electronics, and (3) organic electronics.

The focus of the Si-based nanoelectronics is thephysical and electrical metrology of the basicbuilding blocks of silicon quantum electronicdevices (e.g., quantum layers, wires, and dots ofsilicon surrounded by silicon dioxide). Byidentifying and addressing the critical metrologyissues associated with these basic building blocks,the basis of metrology for future Si-based ULSInanotechnology will be defined.

Electrically measuring molecules: the concept.

A major goal is to fabricate single quantum dotsand wires with controllable size. These will beused to establish the relationship between the keyfabrication conditions, physical properties (suchas the geometry of the quantum-dot and the tun-neling barrier), and final electrical properties ofthese floating silicon devices (i.e., metal-oxide-silicon-oxide-silicon [MOSOS] devices). Produc-

tion of MOSOS capacitor structures is an interme-diate step en route to this end goal. This researchwill provide the information necessary to help iden-tify and address the necessary electrical and phys-ical characterization methodologies.

DELIVERABLE: Complete systematic investigation ofcarrier mobility in Si-nanowire FETs nanofabricatedfrom SOI wafers.

In molecular electronics, our major objectives area NIST standard suite of molecular test structuresand a fundamental understanding of chargetransport through molecules and molecularensembles.

We are developing robust molecular test structuresin order to use them to measure the electrical prop-erties of molecules. Specifically, we are develop-ing nanofabricated test-structures for assessingthe electrical properties and reliability of moletronicmolecules. These in-house test structures andprototypical ME devices obtained from leadingresearchers outside of NIST are thoroughly as-sessed to determine if they are viable test vehi-cles. In addition to the complexity of the nanofab-rication of test structures, the challenges associ-ated with measuring the electrical properties (suchas current-voltage and capacitance-voltage asfunctions of temperature and applied fields) ofthese small molecular ensembles are daunting. Themeasured electrical properties will be correlatedwith systematic characterization studies by a vari-ety of advanced analytical probes and the resultsused in the validation of predictive theoreticalmodels.

DELIVERABLE: Complete a documented NIST standardsuite of molecular electronic test structures.

Two of the most critical elements to forming a suc-cessful ME device structure are the formations ofa high-quality molecular monolayer and a top-met-al/molecule interface. The NEDM is investigatingways to improve the characterization and controlof these top and bottom molecular interfaces. Todo this, the NEDM is optimizing self-assembly ofmolecular films onto both metals such as gold anddirectly onto Si surfaces. The direct attachment oforganic molecules to the silicon surface is of in-creasing importance for emerging molecular elec-tronics applications as devices incorporating mol-ecules chemically bonded to silicon are amenableto integration with existing Si processing tech-niques. In order to determine optimal top-metalli-zation techniques, we are developing new charac-terization approaches to determine metal/molecu-lar interactions. Empirically, new deposition tech-


niques and new top-metals (such as organic con-ductors) are being assessed to determine their vi-ability as top metal contacts.

DELIVERABLE: Assess and improve methods forsolution-based direct attachment of organic moleculesto Si.

DELIVERABLE: Develop and demonstrate FTIR-basedtechnique to characterize top-metal/molecularinterfaces. Investigate initial metal/moleculeinterfaces.

The current state of organic electronics is analo-gous to the early stages of the silicon semicon-ductor industry, with the concurrent developmentof multiple material platforms and processes, nostandardization of measurements between labora-tories, and a lack of diagnostic probes, tools, andmethods necessary to address critical technolog-ical challenges. A principal goal of the new organ-ic electronics task is to determine experimentallythe correlation between device performance andthe structure, properties, and chemistry of criticalmaterials and interfaces. The first step is to devel-op a preliminary set of test structures, fabricationtechniques, and measurement methodologies tocharacterize the electrical properties of OFETS (or-ganic field effect transistors) systematically.

DELIVERABLE: Design initial OFET test structure suiteand fabricate prototypical organic devices. Preparereport.

Developing the metrology for “beyond-CMOS”nanoelectronic devices is a challenging andmultidisciplinary task; therefore, it is important tobe teamed with strong collaborators. The Si-basednanoelectronics team works closely with scientistsin the Quantum Electrical Metrology Division aswell as researchers at NTT. The ME staff is part ofa NIST Competence Project on MolecularElectronics with the Chemical Science andTechnology Laboratory (CSTL). CSTL providesmany of the molecules we use, provides insightsinto SAM formation, performs precise structuralcharacterization, and performs advanced quantumchemistry theoretical analysis. In addition, theME team is working with various companies,universities, and government laboratories (e.g.,Hewlett-Packard, Yale University, University ofTexas at Dallas, Naval Research Labs). A new (forFY 2005) NIST Competence Project on OrganicElectronics has been established, forming a teamof scientists from the NEDM, the Materials Scienceand Engineering Laboratory (MSEL), and CSTL.This combination of interdisciplinary talent willallow the electrical behavior of organic FETs to becorrelated with the results of unique, state-of-the-

art physical characterization methods in order toform a better understanding of the fundamentalmechanisms that are determining final deviceperformance in this new category of devices.

Si nanowire field-effect transistor.

ACCOMPLISHMENTS

# Joint NIST/HP Research Progresses TowardCritical Molecular Electronics Measurements.Research at the NEDM and Hewlett Packard (HP)Laboratories is progressing toward reliable meth-ods for measuring the electrical behavior of mo-lecular electronic devices, an emerging nanotech-nology eyed for future integrated circuits. By us-ing a crossbar test structure consisting of a mo-lecular monolayer sandwiched between a series ofperpendicular metal wires, collaborators at sepa-rate facilities recorded nearly identical electricalmeasurements. This step, along with others takento eliminate potential sources of error, ensures thatthe measured behavior is directly attributable tothe device and not the experimental set up. Elec-trical (current-voltage, or IV) measurements ofcrossbar devices containing eicosanoic acid ex-hibit a controllable, two-state switching behaviorthat is due to the presence of the molecular layer.However, the molecular monolayer is not the solecause. Rather, the switch-like behavior most likelyarises from the interaction of the molecules withthe electrodes. This example illustrates that theproperties of molecular electronic devices are


often determined not by the molecule alone, butby the entire device that consists of both the mol-ecules and the attachment electrodes. This two-state behavior was independently measured in twoseparate laboratories, indicating that it is not ameasurement artifact and illustrating that thesedevices are robust enough to ship via conven-tional methods and remain active. In addition to IVmeasurements, what well may be the first capaci-tance-voltage (CV) measurements of molecularmonolayer-based devices were taken at NIST.These CV curves also show two-state behavior.

# Improved Methods to Attach Long-ChainAliphatic Molecules to Silicon Developed. Dr.Christina Hacker and colleagues have developedan improved solution-based method for the directattachment of long-chain aliphatic molecules toSi. In this method, ultraviolet (UV) radiation isused to assist the attachment of alcohols to thehydrogen-terminated Si(111) surface to formmolecular monolayers successfully. To investigatethe quality of these organic monolayers, they werephysically and chemically characterized withinfrared spectroscopy, spectroscopic ellipsometry,and contact angle measurements. The electricalproperties of these organic films were probed byusing IV and CV measurements obtained from ametal-organic-silicon test structure fabricated bypost-monolayer metal deposition. The effect ofdiffering alkane chain length on the electricalproperties was investigated, and the CVs are inagreement with traditional theory for a metal-insulator-semiconductor.

# Enhanced Inversion Mobility in SiliconNanowire Field Effect Transistors Demonstrated.Dr. Sang-Mo Koo and colleagues have demonstrat-ed that silicon nanowire (SiNW) field effect tran-sistors (FETs) fabricated by a standard ‘top-down’approach exhibit substantially enhanced transportperformance. A systematic study on the inversionelectron transport properties of SiNWs with dif-ferent channel geometries has shown that a SiNWdevice exhibits enhanced inversion channel cur-rent density: the extracted electron inversion mo-bility of the 20 nm width nanowire channel(1000 cm2/Vs) is found to be 2 times higher thanthat of the reference MOSFET of large dimension(W >1 µm). The enhancement is attributed to thepossible suppression of inter-valley phonon scat-tering due to strain in SiNW caused by the oxida-tion process. As the feature sizes of FETs arescaled downward, the semiconductor industry isworking to meet the increasing challenges of nanos-cale devices that are smaller and yet can be manu-

factured with minimal deviation from today’s stan-dard manufacturing processes. These resultsstrongly suggest that lithographically fabricatedSiNW FETs, which are compatible with Si ULSItechnology, can bring about significant perfor-mance benefits in nanoscale electronics, preserv-ing the basic silicon technology infrastructureupon which current industry relies.

# Molecular Electronic Test Structure (METS)Assessment Methodology. An effective testprotocol was developed for METS to ensure thatelectrical results can be attributed to the moleculesand are not an artifact of the test structure itself.Current-voltage curves were obtained for deviceswith no molecules and for devices containing long-chain alkanethiols (such as octadecanethiol).These two limits, a conducting short and aninsulating film in the nanopore, respectively,characterize the METSs and allow the propertiesof conducting molecules of interest to be measuredreliably. In addition to applying this methodologyto the METSs being fabricated in the NEDMProject, we apply these techniques to investigateMETSs of other researchers. For example, we havecharacterized Si3N4-based nanopore devices in acollaboration with Yale University (M. A. Reed)and crossbar type devices in collaboration withHewlett-Packard.

nano-Bucket molecular electronic test structure.

# Development of nano-Bucket FabricationProcesses. Individual nano-Bucket devices havebeen fabricated successfully from nanopores(down to ~30 nm in diameter) etched through boththermally-grown SiO2 and dielectrics deposited viachemical-vapor deposition (CVD) techniques. Themost promising of these techniques relies on CVDdielectrics and an organic conductor to form a topcontact to the molecular monolayer. This vehiclehas been assessed and easily passed the no-


molecule criterion (as a dead short) and the no-nanopore criterion (as a no-leakage open circuit).

# Establishing Infrastructure for the Nanoelec-tronic Device Metrology Project. In FY 2002, theNanoelectronic Device Metrology Project wasestablished. Extensive plans were developed andfunding was acquired for this project. There arethree areas of infrastructure that have been im-proved: personnel, equipment, and funding. Inaddition to the joint CSTL/EEEL Molecular Elec-tronics Competence (started FY 2001) and fund-ing from the National Nanotechnology Initiative(started mid-year FY 2001), the NEDM Project waspart of two recently funded ATP Intramural Awards:“The Missing Plateau: Confined Silicon Devicesfor ULSI Nanotechnology,” (EEEL/MSEL) and“Model-Guided Screening of Electrically-ActiveMolecules for Nanoelectronics” (CSTL/EEEL). InFY 2005, new funding will begin from DARPA andthe MSEL/EEEL/CSTL Organic Electronics Com-petence.

# Personnel. Since the project was formed in2001, two new full-time researchers have joinedNIST and the NEDM Project. Oleg A. Kirillov(Rochester Institute of Technology [RIT]) washired as a processing engineer. Dr. Christina Hack-er (U. Wisconsin at Madison) was hired on afterworking in the NEDM Project as a post-doctoralcandidate through the NRC Research AssociateProgram. At the start of FY 2005, three postdoc-toral guest researchers will be working in theNEDM; Dr. Wenyong Wang (Yale University) willconcentrate on electrical characterization of MEdevices while Drs. Sang-Mo Koo and QiLiang Li(NCSU) will concentrate on Si-nanoelectronic de-vice structures. Dr. Jin-Wan Park (Seoul NationalUniversity) and Dr. Jin-Ping Han (Yale University)both left during FY 2004 after working with us fortwo years each as guest researchers.

FY OUTPUTS

COLLABORATIONS

Hewlett-Packard, R. Stanley Williams, Interfaceproperties of molecular electronic test structures

Naval Research Laboratories, James Kushmerick,Molecular test structure assessment

NIST Division 817, Dr. Neil Zimmerman, Metrology fornanoelectronic devices

NIST Division 837, Dr. L. Richter, Opticalcharacterization of molecular and organic interfaces

NIST Division 837, John Henry Scott, High-resolutionTEM studies of molecular test structures

NIST Divisions 836, 837, 838, Dr. Roger van Zee et al.,Molecular Electronics Competence Project

NIST Division 854, Dr. Eric Lin et al., Organic ElectronicsCompetence Project

NTT, Akira Fujiwara, Si-nanowire metrology

The Pennsylvania State University, Prof. T. Mayer,Molecular electronics

Yale University, Prof. M. A. Reed, Robust molecularelectronic test structures


Elevated to IEEE Senior Member status (Curt A. Richter)

RECENT PUBLICATIONS

J. Han, S. Koo, C. A. Richter, E. M. Vogel, “Influence ofBuffer Layer Thickness on Memory Effects of SrBi2Ta2O9/SiN/Si Structures,” Appl. Phys. Lett., Vol. 85, No. 8, pp.1439-1441 (23-AUG.-2004)

L. J. Richter, C. S. Yang, P. T. Wilson, C. Hacker, R. D.van Zee, J. J. Stapleton, D. L. Allara, J. M. Tour, “OpticalCharacterization of Oligo(phenylene-ethynlyene) Self-Assembled Monolayers on Gold,” J. Phys. Chem. B., Vol.108, No. 33, pp. 12547-12559 (19-AUG.-2004)

C. Hacker, J. D. Batteas, J. C. Garno, M. Marquez, C. A.Richter, L. J. Richter, R. D. van Zee, C. D. Zangmeister,“Structure and Chemical Characterization of Self-Assembled Mono-Fluoro-Substituted Oligo(phenylene-ethynlyene) Monolayers on Gold,” Langmuir, Vol. 20,No. 15, pp. 6195-6205 (22-JUNE-2004)

C. A. Richter, C. Hacker, L. J. Richter, E. M. Vogel,“Molecular Devices Formed by Direct MonolayerAttachment to Silicon,” Solid State Electronics, Vol. 48,pp. 1747-1752 (17-JUNE-2004)

C. A. Richter, C. Hacker, L. J. Richter, “Molecular DevicesFormed by Direct Monolayer Attachment to Silicon,”Proceedings of the International Semiconductor DeviceResearch Symposium, 2003 International SemiconductorDevice Research Symposium, Dec 10-12, 2003,Washington, District of Columbia, pp. 417-418 (10-DEC.-2003)

C. A. Richter, C. Hacker, L. J. Richter, “ElectricalCharacterization of Molecular Monolayers Formed byDirect Attachment to Si,” Workbook of the IEEESemiconductor Interface Specialist Conference, IEEESemiconductor Interface Specialist Conference, Dec 04-06, 2003, Arlington, Virginia, pp. P15-1-P15-2 (04-DEC.-2003)

C. A. Richter, D. R. Stewart, “Metrology for MolecularElectronics,” GOMAC Digest of Technical Papers,GOMACTech 2003, Mar 31, 2003 to Apr 03, 2003,Tampa, Florida, Vol. 28, pp. 281-284 (31-MARCH-2003)

C. A. Richter, J. S. Suehle, M. D. Edelstein, O. Kirillov, R.D. van Zee, “Molecular Electronic Test Structures,”Bulletin of the American Physical Society, Vol. 47, No. 1,pp. 285-285 (01-MARCH-2002)

Y. J. Cho, N. V. Nguyen, C. A. Richter, J. R. Ehrstein, B.H. Lee, J. C. Lee, “Spectroscopic EllipsometryCharacterization of High-κ Dielectric HfO2 Thin Filmsand the High-Temperature Annealing on Their OpticalProperties,” Applied Physics Letters, Vol. 80, No. 7, pp.1249-1251 (18-FEB.-2002)


ELECTRONIC MATERIALS CHARACTERIZATION

Technical Contact:Joseph J. Kopanski

Staff-Years (FY 2004):4 professionals3 guest researchers

NIST custom-built high accuracy ellipsometer.

GOALS

The goal of this project is to develop new or im-proved measurements, models, reference data, andmeasurement traceability mechanisms for selectsilicon CMOS front-end process technologies.Major focus is placed on metrology requirementsfor high-κ gate stacks (the bottom interface, thehigh-κ dielectric, the top interface, and the gatemetal) and ultra-shallow junctions as detailed inthe International Technical Roadmap for Semicon-ductors (ITRS). Additional work is undertaken aspossible on low-κ materials, polymers, silicon-on-insulator (confined silicon), strained silicon-ger-manium, and compound semiconductors.

CUSTOMER NEEDS

Front end processing requires the growth,deposition, etching, and doping of high quality,uniform, defect-free films. These films may beinsulators, conductors, or semiconductors. The2003 ITRS near-term (through 2009) difficultchallenges for front end processes include:metrology issues associated with gate dielectricfilm thickness and gate stack electrical andmaterials characterization, introduction of metalgate electrodes with appropriate workfunctions,and metrology issues associated with 2D dopantprofiling.

Scaling is driving a continuous decrease in thegate dielectric film thickness. An effective oxidethickness of 1.0 nm with process control toleranceneeds of less than 0.1 nm is being projected for the0.1 µm CMOS technology node in 2006, droppingto 0.8 nm or less by 2010. For effective gatedielectric thicknesses below 2.0 nm, SiO2 will bereplaced, initially by oxynitride or oxide/nitride

stacks, and then by either metal-oxides orcompounds such as metal-silicates. Spectroscopicellipsometry (SE) is expected to continue as apreferred measurement for process monitoring offuture gate dielectric films. Integrated Circuit (IC)fabrication metrology needs: (1) improved methodsto determine film thickness; (2) techniques todetermine the composition of films and theinterfaces between them; (3) an improvedunderstanding of the relationship betweenphysical, electrical, and optical determination offilm properties; and (4) mechanisms for traceabilityof measurements to NIST.

Since source/drain dopant profiles are a criticalfactor determining the performance of a transistor,dopant profiling has always been needed by thesilicon IC industry. As transistors are scaled toever-smaller dimensions, the variation of dopantprofiles in two- and three-dimensions also beginsto influence device operation. ScanningCapacitance Microscopy (SCM) is a strongcontender to provide two-dimensional carrierprofiles. Structural and elemental analysis atdevice dimensions (for example 3D dopantprofiling) is identified in the ITRS as one of thechallenges beyond 2009. Two- and preferablythree-dimensional dopant profiling, activateddopant profiles, and related TCAD modeling anddefect profiles are necessary for developing newdoping technology.

TECHNICAL STRATEGY

The Electronic Materials Characterization (EMC)project conducts research on front-end processtopics for next-generation silicon ICs and also ona few beyond the roadmap technologies. Projectstaff are working with International SEMATECH,IC companies, SRC university staff, and other NISTresearchers in the following focus areas:

STRUCTURAL AND OPTICAL MODELS FORELLIPSOMETRY

We seek to develop spectroscopic ellipsometry (SE)measurement metrology and models required forhigh-κ materials and have them in place and ontime for their introduction into standard fabrica-tion processes. A custom-built, high-accuracy el-lipsometer (see above figure) with a spectral rangeof 1.5 eV to 6.2 eV and a commercial vacuum ultra-violet (VUV) ellipsometer, which extends the spec-tral range to 9.5 eV, are available for this task. Projectstaff are optically characterizing advanced oxyni-


trides, oxide/nitride stacks, and more complex com-pounds, such as hafnium silicon oxynitride andhafnium-aluminum silicate. Since many of thesematerials have bandgaps just below 6 eV, the mea-surement range obtainable with the VUV ellipsom-eter enables the investigation of processing relat-ed structure in the index of refraction, which showsup in the absorbing region above the bandgapenergy. Project work is directed at determiningpreferred structural models, spectroscopic indexof refraction values, or preferred optical disper-sion functions for each of these film systems, andthe variability of these parameters due to differ-ences in fabrication processes. Work is also di-rected at extracting accurate bandgap values andinterpreting the processing related structure foundin the dielectric function. Analysis has been doneprimarily with software developed at NIST for SE,which allows the addition of the latest publishedor custom-developed optical response models foreach material system investigated.

Soft X-ray photoelectron spectroscopy spectra ofHfSiO and HfSiON thin films, which gives informationabout the valence band edge, but not about the fullband-gap. Inclusion of nitrogen into the silicatenetwork decreases the valence band offset (about 1.6eV, top panel) by introducing states in the gap. A shiftin the O2p edge is also observed. In the lower panel,the aligned spectrum is shown along with the calcu-lated difference spectrum, which shows the states dueto nitrogen.

DELIVERABLE: Determine the optical properties oftechnologically relevant high-κ thin films (ZrO2, HfAlO,and Hf-based alloys) and their optical bandgaps byusing VUV spectroscopic ellipsometry.

RELATION BETWEEN THE OPTICAL,ELECTRICAL, AND PHYSICALMEASUREMENTS OF HIGH-κκκκκ MATERIALPROPERTIES

We seek to develop fundamental understandingof the physical properties of high-κ dielectric filmsvia comparison of structural, optical, and electricalcharacterization. These multimethod studies utilizetechniques such as transmission electronmicroscopy (TEM), soft X-ray photoemission(SXPS), X-ray absorption spectroscopy (XAS),grazing incidence angle X-ray diffraction (GIXRD),capacitance-voltage (C-V) and current-voltage(I-V) analysis, as well as SE, reflectivity, and FTIR-ATR.

DELIVERABLE: Determine the crystal structure ofhigh-κ dielectric films by physical techniques anddemonstrate the relevance of the crystalline phase toelectrical properties and other important materialproperties.

Thin films of nominally the same compositionprepared by different methods can have quitedifferent physical and electrical properties and maybe in metastable states. The crystalline phase ofvarious high-κ dielectric films can depend on filmthickness, stress, grain-size, and impurities. Thedegree of crystallinity, interface roughness,chemical homogeneity, and stoichiometry can havea direct effect on the dielectric properties and theleakage current across such dielectric layers.Strain, interface properties, and the effects ofsurface contamination species can also haveimportant effects. The figure (see left) illustratesthe use of XPS (as part of a study including SEand XAS measurements as well) to determineeffects of the oxygen and nitrogen on the electricalproperties of HfSiO and HfSiON films. SE is usedto determine the dielectric function, XPS yieldsinformation about the valence band edge, and XAScan be used to determine the O:N ratio.

DELIVERABLE: Complete a systematic study of thevalence band offsets of hafnium-based high-κdielectric films. (The valence band offset is a criticalparameter in determining leakage and powerdissipation for a given dielectric composition.)

METROLOGY FOR METAL GATES

Channel autodoping associated with boron out-diffusion from the polysilicon gate and polysilicondepletion will eventually require the phase out of


dual-doped polysilicon gate material. Workfunction, resistivity, and compatibility with CMOStechnology are key parameters for new candidategate electrode materials. Different materials maybe needed for the PMOS and NMOS transistorgates to achieve acceptable threshold voltages.Eventual introduction of single-gate, fully-depletedultra thin body SOI devices with intrinsic channelswill change the optimal values of the gate workfunction, suggesting that tunable workfunctionsystems are of high importance.

DELIVERABLE: Develop test structures andmeasurement capabilities to measure with highaccuracy the metal gate work function and barrierheight. Determine the differences in work functionmeasurements from Scanning Kelvin ProbeMicroscopy (SKPM), Internal Photoemission (IPE), andMOS capacitor flatband voltage as a function of oxidethickness.

METROLOGY FOR ULTRA-SHALLOWJUNCTIONS

We have developed tools that enable scanningcapacitance microscopes to function as two-dimensional dopant profiling tools. This work isdivided into three tasks. Task 1 is to develop SCMmeasurement methodologies. Best measurementpractices are being determined via collaborativeprojects with industrial users and research into thephysics of the silicon surface preparation. Task 2is to develop theoretical models of the SCM. Thefocus of our modeling effort has been to develop2-D and 3-D finite-element solutions of Poisson’sequation for the SCM geometry. Task 3 is theinterpretation of SCM data and technology transfer.Our expertise with interpreting SCM images isbeing transferred to industry through our softwareprogram FASTC2D. The program features an easyto use interface, rapid profile extraction, andoperation in a Windows environment. The figure(see left) shows an extension of the SCMmeasurement that uses a pulsed laser and preciselysynchronized SCM measurements of the inducedcapacitance transient to obtain a local measurementof carrier lifetime with spatial resolution limited onlyby the carrier diffusion length.

DELIVERABLE: Demonstrate SCM-measured dopantprofiles with improved spatial resolution through useof sample beveling and refined data interpretation.

WIDE BANDGAP MATERIALS

Emerging wide bandgap (WBG) semiconductormaterials, such as Gallium Nitride and Silicon Car-bide, are capable of unique high-frequency, high-power, and high-temperature applications. As op-posed to silicon, the materials technologies forWBG are relatively immature, with correspondinggreater materials characterization needs. Solutionof WBG materials based problems is the key toachieving device performance, yield, and reliabili-ty. We are developing three techniques that willprovide information about WBG material qualityand uniformity on both the wafer and device scale.Surface PhotoVoltage Spectroscopy is being usedto measure diffusion length in GaN and SiC wa-fers. Diffusion length is an important indicator ofcrystalline quality for electrical applications, andthe wafer-level uniformity of diffusion lengthwould make for a non-destructive means of accesswafer uniformity. Scanning Capacitance Micros-copy and Scanning Spreading Resistance Micros-copy are being used to measure quantitative dopantprofiles in GaN and SiC, and are being used as amethod for defect analysis. Wafer-level resistivity

(a) dC/dV curves between the SCM tip and silicon witha thin oxide layer, measured with the AFM laser onand with the AFM laser off. (b) Transient capacitancesignal measured as a function of time. The laserpower intensity (dashed line) is used to synchronize thetransient with the change in illumination. The carrierlifetime is estimated from an exponential fit to themeasured transient.

SILICON OPTICAL CONSTANTS ANDADVANCED SILICON MATERIALS

The project also conducts research into materialsneeded to extend CMOS beyond its current andconventional implementation. As part of this work,project members are using SE and RamanScattering to characterize silicon-on-insulatormaterials, strained silicon, and other materials forconfined silicon applications. We also have aneffort to characterize silicon compatible lightemitters and detectors.

DELIVERABLE: Determine the structural qualities ofSilicon on Insulator by SE and Raman Scattering.


mapping with a lithographic contact array provideswafer- and chip-level uniformity maps of substrateresistivity. Resistivity mapping also provides mea-surement of metal-semiconductor contact resis-tivity as a function of substrate doping.

DELIVERABLE: Demonstrate quantitative SCM-baseddopant profiling and resistivity mapping of GaN andother wide bandgap semiconductors.

ACCOMPLISHMENTS

# Completed participation in an international,multimethod investigation of the ability to mea-sure the thickness of very thin SiO2 films traceableto the SI unit of length. Participants included rep-resentatives from five national laboratories. Spec-troscopic and single-wavelength ellipsometrymeasurements were contributed by project mem-bers. Results, analyzed by the sponsoring labora-tory, the United Kingdom’s National PhysicalLaboratory (NPL), were sufficiently encouragingto prompt the planning of a formal “key compari-son.”

# SE measurements and data analyses on twoseries of ZrO2 in collaboration with the Universityof Minnesota and Stanford University showedthat: (i) optical bandgap and the dielectric func-tion of ZrO2 increase with increasing film thick-ness; (ii) optical bandgap and the dielectric func-tion of ZrO2 increase when annealed at high-tem-peratures; and (iii) ZrO2 phase changes from theamorphous state to the tetragonal polycrystallinestate when the film thickness is greater than 80 Åor the film is annealed at a temperature above~ 600 °C.

# Completed an extensive set of SE, SXPS, in-verse photoemission, and TEM measurements ona specially designed set of SiO2, SiON, HfO2, Hf-SiO2, and HfSiON films. This study investigatedthe effects of compositional components, particu-larly Hafnium and Nitrogen, on the dielectric func-tion, band-gap, band offsets, and near band-edgedensity of states, as well as our ability to deter-mine nitrogen concentration from ellipsometrymeasurements.

# Completed a set of SE, SXPS, internal photo-emission, and Rutherford backscattering measure-ments on a family of HfTiO samples with varyingcompositional ratios; measurements were takenboth before anneal and after anneal at three differ-ent temperatures. This material system, whichpotentially has a high enough dielectric constantfor use as a 0.5 nm equivalent oxide thickness(EOT) dielectric, is believed to undergo some un-

usual structural changes when composition iswithin a narrow window around a 50:50 ratio ofHfO2:TiO2 and the films are annealed at a tempera-ture above about 700 °C. Under these conditions,the material appears to become a compound andcrystallizes, which gives it the high dielectric con-stant.

# Completed comparison of oxide thicknessdetermination methods of 2 nm SiO2 films byEllipsometry, C-V, and HRTEM/STEM. Determinedthat the dominant uncertainty in ellipsometer-basedthickness (due to choice of optical model and bestoptical constants for the silicon substrate and theoxide film) was less than the uncertainty in C-Vbased thickness (due to differences resulting fromavailable Q-M corrections for 2-D quantization ofstates in the silicon substrate and poly-layerdepletion). However, the largest overall uncertaintyresults from the uncertainty of HRTEM-basedthickness (approximately ±0.2 nm).

# Completed SE measurement and analysis fora set of hafnium aluminate films grown by AtomicLayer Chemical Vapor Deposition. Combined withHRTEM, RBS, and NRA measurements, the opticalbandgaps and composition dependence of thesefilms were determined and shown to vary withaluminum content in the films.

# Prototyped measurement techniques neededto characterize candidate gate metals for nextgeneration CMOS with high-κ gate dielectrics.Fabricated test structures and extracted workfunction values using the flatband voltage as afunction of oxide thickness method, ScanningKelvin Probe Microscopy (SKPM), and InversePhoto Emission (IPE). A mask set containing avariety of test structures with which to calibrateand compare these measurement methods has beendesigned and procured. The test structurescontain up to four levels of different interleavedmetal layers, MOS capacitors, and sheet resistors.

# From SE and Raman scattering data, we haveshown that the SmartCut SOI wafers contain slightstructural defects in the SOI layer. These defectsmanifest a slightly different dielectric function usedfor the SOI layer in the SE data analysis and theobservation of a weak extra feature at 495 cm-1 inRaman spectrum that is not observed in the spectraof device quality crystalline silicon substrates.

# Implemented optical pumping and voltagespectroscopy of SCM for local measurement ofcarrier lifetime. Using a pulsed laser and preciselysynchronized SCM measurements of the inducedcapacitance transient, local carrier lifetime can be


measured with spatial resolution limited only bythe carrier diffusion length.

# Measured, for the first time, diffusion lengthof GaN using the Surface PhotoVoltage technique.Presented data at the Materials Research Society8th Wide-Bandgap III-Nitride Workshop and at the2004 American Physical Society March Meeting.

# Certified and transferred to sales inventory160 sets of 3 different silicon resistivity StandardReference Materials (SRMs). This brings to a totalof just over 3000 the number of individually certifiedsingle-wafer and multi-piece sets of resistivity-based SRMs that have been put in stock over thelifetime of this activity.

COLLABORATIONS

Arizona State University, Candi Cook, Photoreflectancemeasurements of Ge:Sn:Si samples

Army Research Lab, SEDD, Kenneth Jones, GaN and SiCdevice, process, and material characterization

IBM, E. Gusev

International SEMATECH, P. Y. Hung, SE of high-κdielectrics

NIST, 836 Process Measurements Division, J. Maslar andRoger van Zee, Molecular electronic thin film (SAM films)

NIST, 837, T. Jach and D. Simons

NIST, 852, I. Levin and L. Robins

NIST, 855, A. Davydov

Northrop-Grumman, J. Giagante, Boron and Aluminumimplanted SiC for dopant profiling with SCM and SSRM

Northrop Grumman Corp., Advanced TechnologyLaboratories, Anthony Margarella, Oxynitride filmcharacterization

Pennsylvania State University, Prof. R. Collins, SEmodeling

Rutgers University, E. Garfunkel and R. Bartynski

Stanford University, P. J. McIntyre

Texas Instruments Inc., Drs. J. Chambers and M. Visokay

UCLA, Prof. J. Chang

University of Delaware, Prof. R. Opila

University of Minnesota, Prof. Campbell

RECENT PUBLICATIONS

Y. D. Hong, T. Y. Yeow, W. K. Chim, K. M. Wong, J. J.Kopanski, “Influence of Interface Traps and SurfaceMobility Degradation on Scanning Capacitance Micros-copy Measurement,” IEEE Trans. Electron Devices, Vol.51, No. 9, pp. 1496-1503 (01-SEPT.-2004)

D. B. Migas, L. Miglio, M. Rebien, W. Henrion, P. Stauss,A. Birdwell, A. V. Davydov, V. L. Shaposhnikov, V. E.Borisenko, “Structural, Electronic and Optical Properties

of B-(Fe1-xCo2 )Si2,” Phys. Rev. B, Vol. 69, pp. 115204-1-115204-7 (11-MARCH-2004)

A. Birdwell, T. J. Shaffner, D. Chandler-Horowitz, G. H.Buh, W. Henrion, M. Rebien, P. Stauss, G. Behr, L.Malikova, F. H. Pollak, C. L. Littler, R. Glosser, S. Collins,“Excitonic Transitions in B-FeSi2 Epitaxial Films andSingle Crystals,” J. Appl. Phys., Vol. 95, No. 5, pp. 2441-2447 (01-MARCH-2004)

J. F. Marchiando, J. J. Kopanski, “On Calculating ScanningCapacitance Microscopy Data for a Dopant Profile inSemiconductors,” J. Vac. Sci. Technol., Vol. 22, No. 1, pp.411-416 (01-FEB.-2004)

G. H. Buh, C. Tran, J. J. Kopanski, “PSPICE Analysis ofa Scanning Capacitance Microscope Sensor,” J. VacuumSci. Technol. B, Vol. 22, No. 1, pp. 417-421 (01-FEB.-2004)

J. J. Kopanski, J. F. Marchiando, B. G. Rennex, D. S.Simons, Q. Chau, “Towards Reproducible SCM ImageInterpretation,” J. Vacuum Sci. Technol. B, Vol. 22, No.1, pp. 399-405 (01-FEB.-2004)

T. Jach, J. A. Dura, N. V. Nguyen, J. Swider, G. Cappello,C. A. Richter, “Comparative Thickness Measurements ofSiO2 /Si Films for Thicknesses Less than 10 nm,” Surf.Interface Anal., Vol. 36, No. 1, pp. 23-29 (01-JAN.-2004)

J. R. Ehrstein, C. A. Richter, D. Chandler-Horowitz, E.M. Vogel, D. R. Ricks, C. Young, S. Spencer, S. Shah, D.Maher, B. C. Foran, A. C. Diebold, P. Hung, “ThicknessEvaluation for 2nm SiO2 Films, a Comparison ofEllipsometric, Capacitance-Voltage and HRTEMMeasurements,” Characterization and Metrology for ULSITechnology: 2003, 2003 International Conference onCharacterization and Metrology for ULSI Technology,Mar 24-28, 2003, Austin, Texas, No. 331, 336 pp. (30-SEPT.-2003)

D. Chandler-Horowitz, N. V. Nguyen, J. R. Ehrstein, “As-sessment of Ultra-thin SiO2 Film Thickness MeasurementPrecision by Ellipsometry,” Characterization and Metrol-ogy for ULSI Technology: 2003, 2003 InternationalConference on Characterization and Metrology for ULSITechnology, Austin, Texas, pp. 326-330 (30-SEPT.-2003)

N. V. Nguyen, J. Han, J. S. Kim, Y.J. Cho, W. Zhu, Z. Luo,T. Ma, “Optical properties of Jet-Vapor-Deposited TiAlOand HfAlO Determined by Vacuum UltravioletSpectroscopic Ellipsometry,” Characterization andMetrology for ULSI Technology: 2003, InternationalConference on Characterization and Metrology for ULSITechnology, Mar 24-28, 2003, Austin, Texas, pp. 181-185 (30-SEPT.-2003)

G. H. Buh, J. J. Kopanski, “Atomic Force MicroscopeLaser Illumination Effects on a Sample and Its Applicationfor Transient Spectroscopy,” Appl. Phys. Lett., Vol. 83,No. 12, pp. 2486-2488 (23-SEPT.-2003)

G. H. Buh, J. J. Kopanski, J. F. Marchiando, A. Birdwell, Y.Kuk, “Factors Influencing the Capacitance-voltageCharacteristics Measured by the Scanning CapacitanceMicroscope,” J. Appl. Phys., Vol. 94, No. 4, pp. 2680-2685 (15-AUG.-2003)


ADVANCED MOS DEVICE RELIABILITY ANDCHARACTERIZATION

GOALS

The goal of this project is to provide electrical andreliability measurement techniques, data, physi-cal models, and fundamental understanding forultra-thin silicon dioxide and alternate gate dielec-trics in future Metal Oxide Semiconductor (MOS)devices. The project aims to increase the under-standing of the relationship between the gate di-electric material/interface properties and deviceelectrical and reliability measurements.

The project’s newly renovated laboratory space.

CUSTOMER NEEDS

The MOSFET (Metal Oxide Field Effect Transis-tor), which is the current basis of ULSI (Ultra-Large-Scale Integration) circuits, is beginning toshow fundamental limits associated with the lawsof quantum mechanics and the limitations of fabri-cation techniques. The evolving decrease of thegate dielectric film thickness to an oxide-equiva-lent value of 2 nm is identified as a critical front-end technology issue in the SIA’s InternationalTechnology Roadmap for Semiconductors (ITRS)with effective thickness values of 1.4 nm, or less,being projected in 2004, dropping to 0.8 nm or lessby 2010. For effective gate dielectric thicknessesbelow ~ 2.0 nm, SiO2 must be replaced, initially byoxynitrides or oxide/nitride stacks, and then byeither metal-oxides or compounds such as metal-silicates.

Due to increased power consumption, intrinsicdevice reliability, and circuit instabilities associat-ed with SiO2 of this thickness, a high permittivitygate dielectric (e.g., Si3N4, HfSixOy, ZrO2) with low

leakage current and at least equivalent capacitance,performance, and reliability will be required. Thephysics of failure and traditional reliability testingtechniques must be reexamined for ultra-thin gateoxides that exhibit excessive tunneling currentsand soft breakdown. Electrical characterization ofMetal Oxide Semiconductor (MOS) capacitors andField Effect Transistors (FETs) has historically beenused to determine device and gate dielectric prop-erties such as insulator thickness, defect densi-ties, mobility, substrate doping, bandgap, and reli-ability. Electrical and reliability characterizationmethodologies need to be developed and en-hanced to address issues associated with bothultra-thin SiO2 and alternate dielectrics includinglarge leakage currents, quantum effects, and thick-ness dependent properties. As compared to SiO2,very little is known about the physical or electricalproperties of high dielectric constant gate dielec-trics in MOS devices. The use of these films inCMOS technology requires a fundamental under-standing of the relationship between the gate di-electric material/interface and device electrical andreliability measurements.

TECHNICAL STRATEGY

The strategy of this effort is to develop robustelectrical characterization techniques and method-ologies to characterize charge trapping kinetics, Vtinstability, defect generation rates, and time-de-pendent dielectric breakdown (TDDB) for bothpatterned device samples and blanket films ob-tained from our collaborators. Many issues suchas tunnel/leakage current and spatially dependentproperties associated with metal oxide and silicatedielectrics are also present in ultra-thin oxide andoxide-nitride stacked dielectrics. Therefore, manyof the characterization schemes will first be devel-oped on the simpler ultra-thin oxide and oxide-ni-tride dielectrics and then be applied to the metaloxide and silicate dielectrics for a variety of high-κsamples subject to different deposition and gateelectrode processes. Studies will be conducted todetermine the effect of multiple interfaces onstress-induced defect generation and wear-out. Itwill be determined what technique or combinationof techniques provides the most consistent resultsfor all films. The electrical results will be used tovalidate simulation models and compared to stud-ies from various analytical materials characteriza-tion.

Technical Contact:John S. Suehle

Staff-Years (FY 2004):2 professionals1 technician3 guest researchers


The understanding generated in this research willbe used to continue generating standard measure-ments through a NIST-coordinated collaborationbetween EIA-JEDEC (Electronic Industries Asso-ciation-Joint Electron Device Engineering Coun-cil) and the ASTM (American Society for Testingand Materials). Studies on the reliability of highdielectric constant dielectrics also will be per-formed.

Energy distribution of interface traps as determined byrise and fall time dependence of charge-pumpingcurrents for HfO2-gated MOSFETs. (a) n-MOSFET.(b) p-MOSFET.

“The success of this

project’s methodologies

and its ability to provide

standards for the entire

U.S. industry is attested

to by the fact that the

same standards are now

being adopted interna-

tionally and are being

used in the qualification

of offshore foundries.”


DELIVERABLE: Deliver experimental results of chargestability and trapping in HfO2 films including defectgeneration rates due to constant voltage stress.

DELIVERABLE: Conduct gate polarity dependentstudies of the long-term wear-out and breakdown ofadvanced high-κ dielectrics.

DELIVERABLE: Complete comparison study of variouselectrical techniques to determine interface trapspectra for a variety of control samples.

DELIVERABLE: Provide test technique(s) and analysisto quantify electrical trap densities at multiple interfacestacks.

DELIVERABLE: Provide correlation study of electricalparameters to results from materials analysis on aselect number of samples fabricated with differentmetal gate processing.

ACCOMPLISHMENTS

# Energy dependence of interface traps in HfO2was characterized. A series of experiments wasconducted to characterize the energy dependenceof interface trap density in n and p-channel HfO2FETs supplied by IBM. The study demonstratedthat the mobility reduction observed in n-channeldevices is due to positions of interface traps in theupper half of the Si energy band.

# New JEDEC standard, JESD-92, is pub-lished. The standard describes several techniquesthat can be used to detect soft breakdown in ultra-thin gate oxides, where detection can be difficult.

The standard also includes guidelines for design-ing test structures and data analysis procedures.

# Mechanistic study of progressive breakdownin small area ultra-thin gate oxides wascompleted. A study was completed to investigatetwo gate oxides. One breakdown mode features aconducting filament that is stable until hardbreakdown occurs, and a second mode features afilament that continually degrades with time. Theacceleration factors are different for each mode,indicating different physical mechanisms areinvolved in the evolution and formation of the finalhard breakdown event. Unstable filaments thatresult from the first soft breakdown progressivelydegrade and change physical structure until theirleakage current becomes unacceptably large. A setof voltage and temperature acceleration parametersdifferent from oxide wear-out is necessary toproject the leakage current with time.

# Study of anomalous threshold voltage roll-up behavior observed in HfO2 MOSFETs. Reverseshort channel effect (RSCE) was observed ofhigh-κ (HfO2 on SiON buffer, Al2O3 on SiON buff-er) gated submicron n-MOSFETs. SiO2 or SiONcontrol samples show normal short channel effect(SCE) behavior. The possible causes such as in-homogeneous channel doping profile and gateoxide thickness variation near S/D ends have beenruled out. The results indicate that the channellength dependent interface trap density is the maincause of the RSCE, while oxide charge also plays arole.

FY OUTPUTS

COLLABORATIONS

Agere Technologies, Ultra-thin gate oxide reliability

General Electric, Gate dielectric integrity of SiC electronics

Jet Propulsion Laboratory, Ionizing radiation effects inhigh-κ gate dielectric materials

N.C. State University (oxynitrides, nitrides, ultra-thinSiO2), Alternative gate dielectrics

National Semiconductor, Ultra-thin gate oxide reliability

NIST Divisions 836, 837, 838, Roger van Zee et al.,Molecular Electronics Competence Project

NIST Divisions 836, 837, 838, Roger Van Zee et al.,Spectroscopic ellipsometry of molecular electronics

Penn State University, Ultra-thin gate oxide reliability

Sharp Microelectronics, Characterization of Hafnium-oxide dielectric films

International SEMATECH, Electrical and ReliabilityCharacterization of HfO2 based gate dielectrics


Texas Instruments, Ultra-thin gate oxide reliability

The Pennsylvania State University, Molecular electronics

University of Maryland, College Park, Ultra-thin gateoxide reliability

University of Maryland, Gate dielectric reliability

University of Minnesota, Alternate Gate Dielectrics


JEDEC JC14.2 Committee on Wafer-Level Reliability,Dielectric Working Group, Chairman (John S. Suehle)

INVITED PRESENTATIONS

J. S. Suehle, “Reliability Implications of Scaling GateOxides in Deep Submicron CMOS Technologies,” 2004GOMACTech, Monterey, CA, March 2004.

J. S. Suehle, “Reliability Metrology for the SemiconductorIndustry at NIST,” 2004 GOMACTech, Monterey, CA,March 2004.

J. S. Suehle, “Reliability Year In Review: Gate Dielectrics,”2004 IRPS.

J. S. Suehle, “Long-Term Reliability Projection Issues forUltra-Thin Gate Dielectrics,” Workshop on Aging andLong Term.

E. M. Vogel, “Characterization Needs for EmergingResearch Materials and Devices,” ITRS Emerging ResearchMaterials Workshop, San Francisco, CA, July 11, 2004.

E. M. Vogel, “Challenges of Electrical Measurements ofAdvanced Gate Dielectrics in MOS Devices,” AppliedMaterials, February 9, 2004.

J. S. Suehle, “Reliability Characterization and ProjectionIssues of Advanced Gate Dielectrics,” University ofMaryland, Dept. of Reliability Engineering, March 3,2003.

J. S. Suehle, “Potential Reliability Issues for MolecularElectronics,” The Aerospace Corporation, Los Angeles,CA, December 5, 2002.

E. M. Vogel, “Issues with Electrical and ReliabilityCharacterization of Advanced Gate Dielectrics,” 12th

Workshop on Dielectrics in Microelectronics, Grenoble,France, November 20, 2002.

J. S. Suehle, “Molecular Electronics: What Will Be theReliability Issues?” 2002 Integrated Reliability Workshop,Lake Tahoe, CA, October 22, 2002.

RECENT PUBLICATIONS

J. Han, S. Koo, C. A. Richter, E. M. Vogel, “Influence ofBuffer Layer Thickness on Memory Effects of SrBi2Ta2O9/SiN/Si Structures,” Appl. Phys. Lett., Vol. 85, No. 8, pp.1439-1441 (23-AUG.-2004)

J. S. Suehle, B. Zhu, Y. Chen, J. B. Berstein, “AccelerationFactors and Mechanistic Study of Progressive Breakdownin Small Area Ultra-thin Gate Oxides,” 2004 IEEEInternational Reliability Physics Symposium Proceedings,International Reliability Physics Symposium, Apr 25-29, 2004, Phoenix, Arizona, pp. 95-101 (29-APRIL-2004)

J. S. Suehle, “Reliability Implications of Scaling GateOxides in Deep Submicron CMOS Technologies,” GOMACDigest of Technical Papers, GOMACTech, Mar 15-18,2004, Monterey, California, pp. 213-216 (18-MARCH-2004)

J. Han, E. M. Vogel, E. P. Gusev, C. D’Emic, C. A. Richter,D. Heh, J. S. Suehle, “Asymmetric Energy Distribution ofInterface Traps in n- & p- MOSFETs with HfO2 GateDielectric on Ultra-thin SiON Buffer Layer,” ElectronDevice Letters, Vol. 25, No. 3, pp. 126-128 (01-MARCH-2004)

J. S. Suehle, “Ultra-Thin Gate Oxide Breakdown: A FailureThat We Can Live With?” Electronic Device FailureAnalysis, Vol. 6, No. 1, pp. 6-11 (01-FEB.-2004)

E. M. Vogel, G. A. Brown, “Challenges of ElectricalMeasurements of Advanced Gate Dielectrics in Metal-Oxide-Semiconductor Devices,” Characterization andMetrology for ULSI Technology: 2003, 2003International Conference on Characterization andMetrology for ULSI Technology, Mar 24-28, 2003,Austin, Texas, pp. 771-781 (30-SEPT.-2003)

J. Han, E. M. Vogel, E. P. Gusev, C. D’Emic, C. A. Richter,D. Heh, J. S. Suehle, “Energy Distribution of InterfaceTraps in High-κ Gated MOSFETs,” Tech. Dig., VLSITechnology, 2003 Symposia on VLSI Technology andCircuits, June 10-14, 2003, Kyoto, Japan, pp. 161-162(01-JUNE-2003)

D. Heh, E. M. Vogel, J. B. Bernstein, “Impact of SubstrateHot Hole Injection on Ultra-thin Silicon DioxideBreakdown,” Appl. Phys. Lett., Vol. 82, No. 19, pp. 3242-3244 (12-MAY-2003)

E. M. Vogel, C. A. Richter, B. G. Rennex, “A Capacitance-Voltage Model for Polysilicon-Gated MOS DevicesIncluding Substrate Quantization Effects Based onModification of the Total Semiconductor Charge,” Solid-State Electronics, Vol. 47, pp. 1589-1596 (10-MARCH-2003)

E. M. Vogel, D. Heh, J. B. Bernstein, “Impact of theTrapping of Anode Hot Holes on Silicon DioxideBreakdown,” IEEE Electron Device Letters, Vol. 23, No.11, pp. 667-669 (01-NOV.-2002)


INFRASTRUCTURE FOR INTEGRATED ELECTRONICSDESIGN & MANUFACTURING

Technical Contact:John Messina

Staff-Years (FY 2004):6.0 professionals1.0 guest researcher

GOALS

The primary goal of the Infrastructure forIntegrated Electronics Design & Manufacturing(IIEDM) Project is to contribute actively to thetechnical development of neutral product data ande-manufacturing exchange specifications andadvanced interoperable e-business infrastructurecomponents. In pursuit of its primary goal, theIIEDM Project aids the growth of the electronicsand semiconductor industries by providing twovaluable services: technical expertise in an impartialforum in the development of standards andassistance in resolving interoperability issuesbetween similar, and often conflicting,standardization efforts. The neutral nature of NISTallows industry consortia, academic bodies, andstandards organizations to accept free technicaladvice on how to improve their data exchangestandards from the IIEDM staff without concernsof favoritism or bias. This impartiality enables theIIEDM Project to work with groups of industrymembers to solve data exchange problems that arefacing the industry as a whole. The second servicethat the IIEDM project provides focuses on helpingthe industry deal with multiple conflicting andoverlapping standards. Due to the nature of theindustry, with no single organization dictatingstandard development, companies are often facedwith no clear optimal choice when it comes to dataexchange standards. The IIEDM staff focus oncreating environments in which companies canevaluate newly emerging standards and howdiffering standards can interoperate with eachother successfully.

CUSTOMER NEEDS

To maintain a globally competitive posture, semi-conductor and electronics manufacturers arequickening their pace of production and innova-tion. Electronic products are transitioned rapidlyto a commodity status, production sites are con-structed and decommissioned in shorter time-frames, and manufacturers are globally outsourc-ing an expanding scope of production process —and in some cases, the entire design and produc-tion process. To achieve the flexibility and quickturn-around they require, manufacturers rely on adistributed supply network and the ability to “mixand match” hardware and software within theirown enterprise. This rapid reconfigurability need-

ed by industry depends upon a robust IT infra-structure, consisting of standards for collabora-tion, business process integration, and the ex-change of technical data. Industry also needsneutral test beds in which to evaluate new stan-dards and the risks associated with technologyadoption.

Ya-Shian Li holds a printed circuit board. The projectbrings printed circuit board standards developmenttechniques and technologies to the semiconductorindustry.

TECHNICAL STRATEGY

This project is working with industry to enable theinfrastructure needed to support electronic com-merce for both electronic components and manu-facturing. The technical areas being addressed bythis project are: the fundamental terminology usedto describe components, the organization of thecomponent data and metadata, and the ability toaccess this data and incorporate it into a product’slifecycle from design all the way through manufac-turing. Development of standards within this do-


“The valuable conversion

of the formats to XML

Schema was not a

simple one. NIST

personnel spent signifi-

cant and painstaking

efforts to ensure that the

finished format is the

best it can be.”

IPC Award Speech at IPCPrinted Circuits Expo (APEX),February 2004 on thedevelopment of the IPC 2581standard board format

main is crucial in order for U.S. electronics andsemiconductor manufacturers to take advantageof the global marketplace. This project assists in-dustry in the development of standards that arecritical to the infrastructure, but that no singlecompany will pursue because of the broad-basedbenefit. Industry and standards groups in Japanand Europe are actively working on electronic com-merce and manufacturing related projects. In work-ing with these groups, NIST will try to minimizethe overlapping standards development and en-sure interoperability between U.S. and interna-tional standards.

DELIVERABLE: Organize an international effort tosupport the inclusion of material componentinformation into existing electronic dictionariesformats.

One key aspect of this work, as identified by in-dustry, is the need for on-line traceable dictionar-ies in order to distribute electronic component dataeffectively via the Internet. On-line dictionariesenable the industry to evaluate electronic compo-nent information properly. In support of on-linedictionaries, NIST has been working with largeindustry consortiums and standards groups, suchas RosettaNet and the IEC, providing technicalexpertise in the design of both the electronic dic-tionary formats and the software tools necessaryto access and use those newly created dictionar-ies.

While the project’s original work focused on cre-ating a common electronic dictionary format us-able by everyone. It soon became evident that theelectronics industry would always create new dic-tionaries that were focused on very specific do-mains, and these separate dictionaries would bein different formats. At that point, the projectswitched from creating a generic dictionary for-mat to organizing an international effort to ensurethat all the different dictionary formats would beinteroperable with each other. Under the umbrellaof the IEC Technical Committee 93 Working Group6, the IIEDM staff have been working to createinternational dictionary mapping experiments thatstudy the overall interoperability problems and tryto determine the steps that can be taken by cur-rent and future dictionary formats to ensure in-teroperability between all the electronic dictionaryformats.

DELIVERABLE: Develop a package of software toolsdesigned to support the electronics industry migrationfrom the Gerber file format to the new IPC 2581standard.

“NIST provides unique

capabilities that have

greatly improved the

definition of industry

standards that are

required for useful

implementation of data

collection software

capabilities for e-

Manufacturing”

International SEMATECHletter to NIST, July 8, 2004

In conjunction with the dictionary work, the IIEDMProject continues to work with the electronicsmanufacturing industry, identifying andaddressing new electronic data exchange needs.One aspect of the project’s continuing work withthe electronic industry is working with the NationalElectronics Manufacturing Initiative (NEMI) ontheir bi-annual roadmapping activity. NEMI’sroadmap seeks to survey the electronics industryand identify the major development trends for theindustry for the next two years. By working withNEMI on the roadmapping activity, the IIEDMProject has the ability to work with industry toidentify future needs and start developingsolutions to those needs early enough to be inplace by the time they are needed.

In addition to its activities within the electronicsmanufacturing industry, the IIEDM Project is tak-ing its technical expertise in designing electronicdata exchange specifications and applying it tothe semiconductor industry. In the Printed CircuitBoard (PCB) industry, the move toward outsourc-ing over the last several years has pushed the de-velopment of data standards that can accuratelyexchange product information between any twopartners in a manufacturing design chain. Thisexchange of information can occur anywhere inthe process from trading purchase order informa-tion between trading partners to exchanging de-sign information between factory floor equipment.The semiconductor industry is now facing thesame need to outsource various manufacturing anddesign activities that the PCB industry faced sev-eral years ago. While the actual standards needsare different for the semiconductor industry dueto the differing manufacturing process and theproducts being developed, the design process formaking the needed standards is still the same. To-ward that end, the IIEDM Project is teaming upwith leading industry consortiums and companiesin the semiconductor industry in order to addresstheir data exchange needs. The project’s activi-ties include becoming involved in standards de-velopment activities, developing prototype soft-ware systems to test new standards, and leadingroadmapping activities to help identify future in-dustry problems.

DELIVERABLE: Develop an augmented domainmodeling environment for standards development thatimproves the quality of the standards through the useof software visualization tools.

ACCOMPLISHMENTS

# NIST chaired the IEC Technical Committee 93Working Group 6 that authored the IEC report 61908


“The Technology Roadmap for Industry Data Dic-tionary Structure, Utilization and Implementation.”The report studied interoperability for electronicdictionary formats on an international level andhas been accepted by the IEC as a Final Draft In-ternational Standard (FDIS).

# Developed a new software tool (“Hydra 3D”)which is a unique three-dimensional viewer andeditor for XML files. The software is currently avail-able on CD ROM and on the Internet (http://hydra3d.sourceforge.net).

# Established a new work agreement with Inter-national SEMATCH (ISMT) in order to bring theproject’s standards development skills from theprinted circuit board industry to the semiconduc-tor industry. The collaboration between NIST andISMT has had considerable success within its firstyear with the various tasks leading to four sub-missions being accepted to ISMT’s AdvancedEquipment Control/Advanced Process Control(AEC/APC) Symposium XVI.

# Helped the Institute for the Packaging ofElectronic Circuits (IPC) complete a new boardlayout standard IPC 2581 “Offspring” designed tobe the next generation replacement for the Gerberboard layout currently being used by industry.

# Developed several software tools designedto assist with industry’s adoption of the IPC 2571standard including an IPC 2571 board viewer tooland a Gerber to IPC 2571 software translator.

# Chaired the NEMI 2004 Roadmapping activitydesigned to identify future industry issues onproduct lifecycle management.

FY OUTPUTS

COLLABORATIONS

We are currently working with ISMT, a leadingsemiconductor industry consortium, by providing technicalexpertise in the development of data exchangespecifications and reference software implementations.

We are working with the IPC on the development ofsoftware tools to assist the industry in the migration fromGerber board layouts into the new IPC 2571 standardboard layouts.

We are currently working with a group of organizations(RosettaNet, Electronic Commerce Code ManagementAssociation [ECCMA], and the IEC) on electronic formatsfor dictionary and parts catalogues.


The “3D Hydra” software tool and an accompanyingpaper were accepted at the Extreme Markup Conference2004 in Montreal, Canada, and at the 31st International

Conference on Computer Graphics and InteractiveTechniques (SIGGRAPH 2004).

The IIEDM Project Leader, John Messina, was invited togive a talk on electronic dictionaries and parts cataloguesat the ECCMA 4th Annual Conference.

The IPC gave NIST an award for its significant andpainstaking efforts in the development of the IPC 2571standard.

ISMT sent NIST a letter thanking the IIEDM Project forits efforts in the development of data exchangespecifications and software tools for the semiconductorindustry.

The collaboration between NIST and ISMT led to fourpapers on XML standard work being accepted at ISMT’sAdvanced Equipment Control/Advanced Process Control(AEC/APC) Symposium XVI.

RECENT PUBLICATIONS

Y. Li, B. Van Eck, E. Simmon, “Running Out of Time:Improvements Required in Current Semiconductor Factoryand Equipment Clock Synchronization for SupportingFuture Real-Time Data Collection,” AEC/APC SymposiumXVI Proceedings/(CD format), AEC/APC SymposiumXVI, September 18-23, 2004, Westminster, CO, USA.(23-SEPT.-2004)

E. Simmon, G. Crispieri, “Measuring the Performance ofXML-Based Data Standards,” AEC/APC Symposium XVIProceedings, AEC/APC Symposium XVI, September18-23, 2004, Westminster, CO, USA (23-SEPT.-2004)

A. Griesser, “Ensuring High Quality Data TransferStandards,” AEC/APC Symposium XVI Proceedings (CDformat), AEC/APC Symposium XVI, September 18-23,2004, Westminster, CO, USA (23-SEPT.-2004)

M. L. Aronoff, J. V. Messina, K. G. Brady, “Seeing inThree Dimensions: an Alternative Technique for ViewingLarge Information Spaces,” NISTIR 7093 (30-AUG.-2004)

M. L. Aronoff, “Hydra Users’ Guide,” NISTIR 7087 (30-AUG.-2004)

J. D. Gale, Y. Li, “Time Synchronization for ElectronicDistributed Systems,” NIST Interagency/Internal Report(NISTIR) 7116 (28-MAY-2004)

D. Zwemer, M. Bajaj, R. Peak, T. Thurman, K. G. Brady,S. McCarron, A. Spradling, M. Dickerson, L. Klein, G.Liutkus, J. V. Messina, “PWB Warpage Analysis andVerification Using an AP210 Standards-based EngineeringFramework and Shadow Moiré,” 5th InternationalConference on Thermal, Mechanical and Thermo-mechanical Simulation and Experiments in Micro-electronics and Micro-systems, EuroSimE 2004, May11-13, 2004, Brussells, Belgium, pp. 121-132 (10-MARCH-2004)

Y. Li, B. Van Eck, “Semiconductor Factory and EquipmentTime Synchronization,” NIST Interagency/InternalReport (NISTIR) 7088 (25-FEB.-2004)

Y. Li, B. L. Goldstein, “Semiconductor Industry IT Needs:Lessons Learned from Across the Engineering Chain,” 12p. (01-JUNE-2003)


KNOWLEDGE FACILITATION

GOALS

# To eliminate paper-intensive and manual op-erations by automating tasks, decreasing the ad-ministrative requirements of the technical and sup-port staff, increasing responsiveness to custom-ers, and implementing a secure eNIST paperlessenvironment.

# To provide Information Technology securitypolicies, procedures, guidelines, and baselines andensure compliance with Federal Information Secu-rity Management Act (FISMA) requirements.

# Develop an XML schema based security modelfor information sharing for the Department of Jus-tice.

Jennifer Kostick configures a machine to use theLandesk centralized support software in order toincrease security and centralize PC support.

Technical Contact:Jennifer A. Kostick

Staff-Years (FY 2004):1.0 professional0.5 guest researcher1.0 student

CUSTOMER NEEDS

Scientists need time to work on their research, test-ing, calibrations, etc. However, managers needproject plans, status, and similar information, andcustomers should have access to information in atimely manner. To best enable all of these func-tions, we have developed several web-based ap-plications to minimize the time and efforts of tech-nical staff and project leaders, while providing cus-tomers with up-to-date information.

As more and more of our data is stored electroni-cally, it is natural to progress toward sharing theinformation, maximizing the benefits while minimiz-ing the number of times it has to be entered.

As we grow to rely on the data in our computers,and that data is shared more frequently, the need

for security of that data also grows. Our custom-ers depend upon the confidentiality, integrity, andavailability of the information. Confidentiality re-fers to allowing access to our data only to thepeople who should have it. Integrity refers to en-suring the data is what it should be and no onehas tampered with it. And, availability refers tomaking sure the data is there when it is needed.

The Federal Government has established FISMAGuidelines that allow agencies to provide moresecure information systems within the FederalGovernment including the critical infrastructure ofthe United States. These guidelines provide aframework for us to develop and implement poli-cies and procedures, implement training and aware-ness programs, and secure our assets.

Through our experience and knowledge gainedfrom internal efforts of securing our electronictransfer of data, we have been given theopportunity to assist the justice community in theirefforts. We are assisting a global group of justiceorganizations made from local, state, tribal, federal,and international justice entities to develop anXML schema based security model allowing thejustice and safety community to share informationsecurely. The sharing of information is critical toprovide timely defense to ensure safety. Protectingthe confidentiality, integrity, and availability of thatinformation is paramount.

TECHNICAL STRATEGY

A web-based application has been created to storeand track all of the Electronics and Electrical Engi-neering Laboratory’s publications and reports pro-vided to management. Management is able toobtain access to the information they need easily,and the administrative burden on the technicalstaff has been alleviated. Generation of requiredpaperwork has been automated, removing that re-sponsibility from the support staff. The applica-tions also serve as a warehouse for all publica-tions and reports.

We developed the Information System to SupportCalibrations (ISSC), which is a structured-querylanguage database-driven application. The ISSCstores all of the administrative, technical, and fi-nancial data involved with items calibrated at NIST.The system has over 250 NIST users and providesstatus information to over 1400 calibration cus-tomers. The web-based system allows access froman unlimited number of different machines and


operating systems used by personnel at NIST. TheISSC has reduced the time to complete the requiredpaperwork by automating the entire workflow pro-cess. The ISSC was migrated to Technology Ser-vices for maintenance in 2003. We are collaborat-ing with the National Research Council (NRC) In-stitute for National Measurement Standards(INMS) to assist them in the development of anapplication similar to the ISSC.

A project reporting system, also developed as aweb application, is being created to reduce theduplication of the storage of information whileproviding management with immediate access toproject data without interrupting project staff. Thisapplication contains all project-related informationsuch as funding, milestones, staff, etc. Access tothe application is controlled by a role-based accesscontrol — what you have access to is contingentupon who you are.

A web-based information system is beingdeveloped to support the clean rooms. Scientistswill use the system to reserve equipment in theclean rooms. The system will automatically keeptrack of the time that equipment is used. Accesswill be limited to staff with proper training. This isbeing developed in collaboration with StanfordUniversity.

A web-based information system was created tolog and track all paper documents through theadministrative process. Status of required paper-work can be easily determined.

A web-based information system was developedfor use by NIST’s Conference Facilities personnelto automate all the processes of conferences fromregistration to billing.

To ensure the security of our systems, we havedeveloped and implemented IT Security policiesand procedures and a training and awareness pro-gram. We have met all FISMA requirements, suchas developing detailed security plans, risk assess-ments, self assessments, security tests and evalu-ations, rules of behavior, business impact analy-sis, contingency plans, plans of actions and mile-stones, asset inventories, and architecture andnetwork diagrams for all of the systems withinE E E L .

To augment the efforts of the Security WorkingGroup of the Global initiative to create a securitymodel for information sharing in the justice com-munities, we created a Unified Modeling Language(UML) model from the document developed bythe group, Applying Security Practices to Justice

Information Sharing. The UML diagrams were cre-ated from each category of the Justice Intercon-nection Services (JISN) Model section. At thisstage of the project, the information used to createthe UML diagrams is a literal translation from thetext. In the next stage, efforts will be taken to weedout the redundant information and shape the dia-grams based on input from both the text and thedesigners of the diagrams. This will help to createa more natural means to express the JISN text intoUML.

ACCOMPLISHMENTS

# Implemented Information System to SupportCalibrations (ISSC) NIST-wide.

# Transitioned ISSC to Technology Services.

# Met annual FISMA requirements.

# Developed Bibliography Information System.

# Developed NIST Conference RegistrationSystem.

# Created Electronic Logbook.

# Created Document Information System.

# Developed UML model for informationsharing in the justice community.

FY OUTPUTS

COLLABORATIONS

Kevin Brady is collaborating with Stanford University inthe creation of the Clean Room Information System.

Jennifer Kostick is collaborating with the NationalResearch Council (NRC) Institute for NationalMeasurement Standards (INMS) to assist them in thedevelopment of an application similar to the ISSC.


Kevin Brady, Jennifer Kostick, and John Messina receivedthe Department of Commerce Bronze Medal Award fortheir work with the ISSC.

RECENT PUBLICATIONS

J. Lindeman, “Information System to Support Calibrations(ISSC) Data Entry User’s Tutorial” (27-MARCH-2003)


MAJOR FACILITIES / LABORATORIES

MICROFABRICATION PROCESS FACILITY

See next page for facility description

Contacts: Russell Hajdaj, 301-975-2699Richard Roppolo, 301-975-2096

MATERIALS CHARACTERIZATION LABS

High-Resolution Optical:

Spectroscopic Ellipsometry, High-Resolution Fourier Transform InfraredSpectroscopy, Photoluminescence, Raman Scattering, Photoreflectance, and otherModulation Spectroscopies

Electrical:

Resistivity, Spreading Resistance, Lifetime, Hall Effect, Deep-Level TransientSpectroscopy, Deep-Level Optical Spectroscopy, Charge-Pumping Measurements,Capacitance-Voltage (high frequency & quasi-static), Surface Photovoltage, ACImpedance Analysis, Scanning Capacitance/Atomic Force Microscopy

X-Ray:

Double-Crystal Rocking Curve, Laue Orientation Facility

DEVICE AND TEST STRUCTURE CHARACTERIZATION LABS

Electrical and Thermal Package EvaluationPower Device Model Extraction and ValidationPackaging, Assembly, and Bonding EvaluationPackage InterconnectScanning-Electron MicroscopeScanning-Probe MicroscopeAutomatic Wafer-Level MeasurementGate Dielectric IntegrityMEMS Electrical, Mechanical, Optical, and Microwave

COMPUTER-AIDED DESIGN LABS

Test Structure Layout and DesignIntegrated Circuit Layout, Design, and SimulationFinite Element Thermal Analysis Tools and Computational Fluid SimulationsSystem, Device, Process, Interconnect, and Virtual Fabrications Simulations


MICROFABRICATION PROCESS FACILITY

Metallization: sputter and evaporation.

DESCRIPTION

As integrated circuit (IC) sizes increase to morethan 1 cm2 and feature sizes within the circuitsdecrease to less than 1 µm, critical demands areplaced on the measurement capability required tocontrol and monitor IC fabrication successfully.To meet the demand, NIST researchers aredeveloping state-of-the-art measurementprocedures for microelectronics manufacturing.

The Microfabrication Process Facility provides aquality physical environment for a variety of re-search projects in semiconductor microelectron-ics as well as in other areas of physics, chemistry,and materials research. The laboratory facilities areused for projects addressing many areas of semi-conductor materials and processes, including pro-cess control and metrology, materials character-ization, and the use of IC materials and processesfor novel applications.

The laboratory complex, approximately half ofwhich is composed of Class 1000 cleanroom space,occupies about 2900 square meters. Within thecleanroom, work areas are maintained at Class 100or better. The facility is designed so the work areascan be modified easily to accommodate thefrequent equipment and other changes requiredby research.

OBJECTIVE

Current objectives are to develop and fabricatestructures and devices to fulfill the needs ofmetrology projects within SED and NIST. Thesestructures include MEMS-based devices, micro-electronic devices, and other specialized devices.

CAPABILITIES

The facility has a complete capability for ICfabrication. A list of principal processing andanalytical equipment follows.

DIFFUSION, OXIDATION, AND ANNEALING

Six furnace tubes for up to 75 mm diameter wafersand five tubes for up to 100 mm diameter wafers.

MASK ALIGNMENT

The Karl Suss Mask Aligner model MA/BA6 iscapable of sub-micron resolution (< 0.75 µm) andalso has the ability to expose the backside of asubstrate, which can be aligned to the front sidefeatures. The tool also is designed to be upgradedto a wafer-to-wafer bond aligner.

PLASMA ETCHING AND DEPOSITION

The Unaxis 790, a plasma etching and depositionsystem, is capable of etching Si, SiO2, SiliconNitride, and polyamides. Low temperature(< 300 °C) film depositions of SiO2 and silicon nitridecan also be accomplished using Plasma EnhancedChemical Vapor Deposition.

Unaxis 790 plasma etching and deposition system.[Property of Unaxis Wafer Processing, reprinted withpermission]

PHOTOLITHOGRAPHY

Research mask aligner (proximity and contact) forwafers up to 100 mm in diameter and irregularlyshaped samples and 10 × direct-step-on wafer sys-tem for 75 mm diameter wafers. Photoresist spincoating and developing and related chemical pro-cessing, including oxygen plasma stripping.E-beam writing and scanning electron microscopeexamination for nano-features on 75 mm diameterwafers.


Film deposition and diffusion furnaces.

Wet chemical processing.

FILM DEPOSITION

Low-pressure chemical vapor deposition systemsfor depositing silicon nitride, polysilicon, and low-temperature silicon dioxide. Radio frequency anddc vacuum sputtering of metals and dielectrics.

ETCHING

Wet and dry etching processes. Plasma barreletching of nitride films and wet chemical etchingof silicon for micromachining. Xenon Difluoridesilicon etch process.

ANALYTICAL MEASUREMENTS

Thin-film reflectometry and other thicknessmeasurements, optical microscopy, and groovingand staining. Detak 6M Profilometer providingstep height measurements and thin film stressanalysis software.

POST PROCESSING EQUIPMENT

DISCO HI-Tech America Inc. 8" wafer dicing sawand SEM cross section sample prep equipment.

APPLICATIONS

Small quantities of specialized semiconductor testspecimens, experimental samples, prototype de-vices, MEMS, and BioMEMS structures can beproduced. The processes and processing equip-ment can be monitored during operation to studythe process chemistry and physics. The effects ofvariations in operating conditions and processgases and chemical purities can be investigated.Research is performed under well-controlled con-ditions.

A research-oriented facility, the laboratory is notdesigned to produce large-scale ICs or similar com-plex structures. Rather, the laboratory emphasizesbreadth and flexibility to support a wide variety ofprojects.

Automatic 8" wafer dicing saw.

Currently, research projects address many aspectsof microelectronic processing steps and materialsas well as silicon micro-machining. Examples in-clude: metal-oxide-semiconductor measurements;metal-semiconductor-specific contact resistivity;uniformity of resistivity, ion-implanted dopant den-sity, surface potential, and interface state density;characterization of deposited insulating films onsilicon carbide; ionization and activation of ion-implanted species in semiconductors as a func-tion of annealing temperature; electrical techniquesfor dopant profiling and leakage current measure-ments; and processing effects on silicon-on-insulator materials. A simple Complementary


Metal-Oxide Semiconductor (CMOS) process hasbeen established. Recent work has also begun inthe field of molecular electronics.

AVAILABILITY

Facility staff welcome collaborative researchprojects consistent with the research goals of theNIST semiconductor program. Work is performedin cooperation with the technical staff of thelaboratory.

The most productive arrangements begin with thedevelopment of a research plan with specific goals.The commitment of knowledgeable researchers towork closely with NIST staff and the provision ofequipment and other needed resources arerequired. Because hazardous materials are present,laboratory staff must supervise all researchactivities.

TASKS

# Fabrication of test structures on silicon andgallium nitride (MIS) for AFM

# Fabrication of a refrigerant expansion valveusing sub resist (1200 nm)

# Investigation of neuron growth in microfluidicdevices

# Development of nano-metrology standardsbased on surface atomic spacing

# Fabrication of a magnetic spin inject device


NIST ADVANCED MEASUREMENT LABORATORYNANOFABRICATION FACILITY

Technical Contacts:Eric M. VogelRussell Hajdaj

GOALS

The NIST Advanced Measurement Laboratory(AML) Nanofabrication Facility (NF) will: enablefabrication of prototypical nanoscale teststructures, measurement instruments, standardreference materials, electronic devices, MEMS, andbio-devices critical to NIST’s Strategic FocusAreas (Nanotechnology, Homeland Security,Biosystems and Health) and the Nation’sNanotechnology Needs; provide access toexpensive nanofabrication tools, technologies,and expertise in a shared-access, shared-costenvironment to NIST and its partners; fosterinternal collaboration in nanotechnology acrossNIST’s Laboratories; and foster externalcollaboration in nanotechnology with NIST’spartners.

CUSTOMER NEEDS

To continue to respond to U.S. science and indus-try’s needs for more sophisticated measurementsand standards in the face of heightened globalcompetition, NIST is constructing one of the mosttechnologically advanced facilities in the world -the Advanced Measurement Laboratory, or AML.The NIST Nanofabrication Facility (NF) is one offive buildings in the AML at the Gaithersburg, MD,campus. The AML Nanofabrication Facility willprovide researchers at NIST working on a varietyof semiconductor and other nanotechnology re-search the ability to fabricate prototypical nanos-cale test structures, measurement instruments,standard reference materials, and electronic de-vices.

TECHNICAL STRATEGY

The AML contains 2 above ground instrumentbuildings, 2 completely below ground metrologybuildings, and 1 class 100 clean room buildingwhich will house the NIST AML NanofabricationFacility. The AML will provide NIST with superi-or vibration, temperature and humidity control, andair cleanliness. The NIST AML NF has approxi-mately 1672 m2 of Class 100, raised floor, bay andchase, clean room space. NIST has invested in acomplete suite of new equipment (capable of pro-cessing 150 mm wafers) that will be installed overthe upcoming year. This includes furnaces (2banks of 4 tubes each), LPCVD (poly, nitride, LTO),rapid thermal annealer, 3 reactive ion etchers (SF6/

O2, Metal, Deep), 3 metal deposition tools (ther-mal, e-beam, sputterer), contact lithography (front-and back-side alignment), e-beam lithography, fo-cused ion beam, and numerous monitoring tools(FESEM, spectroscopic ellipsometer, contact pro-filometer, 4-point probe, microscope with imagecapture, etc.).

“The planned AML, with

clean-room capability

that is to be shared by all

NIST laboratories, is

believed to be essential

to support the exacting

future metrology needs

that have been identified

by the semiconductor

and other

nanotechnology indus-

tries.”


The NIST Advanced Measurement Laboratory.

The NF will be operated as a shared-access userfacility. This means that the staff of NIST and itspartners, subject to provisions, training, and userfees, will be permitted to operate the equipmentindependently. The tools will be operated in amanner such that a wide variety of materials canbe processed. The facility will be directed byNIST’s Semiconductor Electronics Division. Un-like other NFs, the AML NF is unique in that, be-ing located at NIST, it is next to the most advancedmetrology tools in the world, and its focus will beon fabricating nanoscale structures necessary formetrology and standards in support of the semi-conductor industry, nanotechnology, biotechnol-ogy, and homeland security.

It is anticipated that the fit up of the facility andequipment will be completed by the first quarter of2005, with the facility becoming fully operationalby the fourth quarter (also 2005).


NATIONAL RESEARCH COUNCIL (NRC)POST-DOCTORAL OPPORTUNITIES

The Semiconductor Electronics Division at the National Institute of Standards and Technology (NIST),in cooperation with the National Research Center (NRC), offers awards for post-doctoral research forAmerican citizens in the fields described below. The Division conducts research in semiconductormaterials, processing, devices, and integrated circuits to provide, through both experimental andtheoretical work, the necessary basis for understanding measurement-related requirements insemiconductor technology.

NIST affords great freedom and an opportunity for both interdisciplinary research and research in well-defined disciplines. These technical activities of NIST are conducted in its laboratories, which are basedin Gaithersburg, a large complex in a Maryland suburb of metropolitan Washington, DC. Applicationsfor NIST Research Associateships are evaluated by the panels only during February. To be eligible forreview in February, completed application materials must be postmarked no later than February 1, 2005.This time will also be approximately the same in 2006.

MOLECULAR ELECTRONICS:ELECTRICAL METROLOGY

In Molecular Electronics — a field that is predict-ed to have important technological impacts on thecomputational and communication systems of thefuture — molecules perform the functions of elec-tronic components. We are developing methodsto reliably and reproducibly measure the electricalproperties of small ensembles of molecules in or-der to investigate molecular conduction mecha-nisms. Specifically, we are developing test-struc-tures based on nanofabrication and MicroElectro-Mechanical Systems processing techniques for as-sessing the electrical properties and reliability ofmoletronic molecules. In addition to the complexi-ty of the nanofabrication of test structures, thechallenges associated with measuring the electri-cal properties (such as current-voltage and capac-itance-voltage as functions of temperature andapplied fields) of these small molecular ensemblesare daunting. The measured electrical propertieswill be correlated with systematic characterizationstudies by a variety of probes and the results usedin the validation of predictive models. This task ispart of a cross-disciplinary, inter-laboratory effortat NIST, whose overall role is to develop the mea-surement science that will enable molecular elec-tronics to blossom into a viable industry.

Contact: Curt A. Richter, 301-975-2082, or John S.Suehle, 301-975-2247

SCANNING PROBE METROLOGY

We are developing scanning probe microscopesto characterize and manipulate the physical andelectrical properties of electronic devices, semi-conductors, and related materials at the nanom-

eter resolution scale. Projects are aimed at impact-ing silicon technology 5 to 10 years in the future orat characterization problems unique to compoundsemiconductors, molecular electronic devices, orquantum devices. We recently developed scan-ning capacitance microscopy as a tool for measur-ing the two-dimensional dopant profile across asilicon p-n junction. We are particularly interestedin projects to develop techniques to measure ma-terial properties in three dimensions and that havespatial resolution below 1 nm. Our interests extendto other scanning probe techniques, includingvariable temperature scanning tunneling micros-copy in UHV, surface photovoltage microscopy,and other optically pumped probes.

Contact: Joseph J. Kopanski, 301-975-2089, orDavid G. Seiler, 301-975-2054

ELECTRICAL OVERLAY- AND CD-METROLOGY DEVELOPMENT FORCHARACTERIZATION OF ADVANCEDLITHOGRAPHY INSTRUMENTS

Projected CD and overlay control-tolerances fornew generations of ICs are reducing metrologyuncertainty down to the several-nanometer region.However, the development of CD and overlay me-trology is not keeping pace with lithographic reso-lution capabilities of advanced imaging systems.In addition, preferred processing options such aschemical/mechanical polishing tend to render ex-isting overlay-metrology less effective for key pro-cess steps. The Enabling Devices and ICs Groupseeks individuals interested in conducting furtherresearch in: (1) novel electrical overlay-sensinginstruments and techniques; (2) the design andoptimization of reference materials for scatterome-


try metrology; (3) noncontact electrical CD-mea-surement and extraction methodologies; and (4)design, fabrication, and certification of CD stan-dards in the range 0.05 µm to 0.10 µm. We alsoencourage applicants with research experience innoncontact/nonintrusive electrical CD extractionand multimode overlay-sensor development, in-cluding MEMS-based overlay and CD reference-material implementations.

Contact: Michael W. Cresswell, 301-975-2072

NOVEL TEST STRUCTURES FORCHARACTERIZING THE PERFORMANCEOF ADVANCED MULTILEVELINTERCONNECTION SYSTEMS

As the complexity of advanced integrated circuitscontinues to increase, new materials (copper, low-κ dielectrics) need to be characterized in order toperform parameter extraction for modeling on-chipinterconnect systems. Extensions of traditionalwiring technologies are no longer practical. TheEnabling Devices and ICs Group seeks individualsinterested in developing electrical test structures,measurement methods, and analysis modelsneeded to evaluate copper based, multilevelinterconnection systems. Of particular importanceare methods to measure interconnect and barrierfilm thickness, dimensional control, by filling,interfacial contact resistance, planarity, defectdensity/yield, dishing, stress effects, median-time-to-failure, and high-frequency performance.Emphasis is placed on developing test structuresfor use with high-measurement speed, low-frequency electrical test techniques.

Contact: Michael W. Cresswell, 301-975-2072

ELECTRICAL AND OPTICALCHARACTERIZATION OFSEMICONDUCTORS AND DEVICES

Research focuses on understanding the electron-ic, optical, and magneto-optical behavior of semi-conductor materials and devices. Areas of inter-est include the role of impurities and native de-fects in bulk crystals, and novel and useful prop-erties induced by quantum confinement in reduceddimensional structures (heterostructures, quantumwells, superlattices, and quantum wires and dots).A broad range of optical techniques is availablefor reflection, transmission and absorption, andmodulation spectroscopy; photoluminescence andphotoluminescence excitation; Raman and reso-nant-Raman scattering; spectroscopic ellipsome-try; and surface photovoltage. A wide variety of

electrical and magnetotransport techniques is alsoutilized to characterize the electronic properties.Emphasis is placed on understanding fundamen-tals and technologically relevant properties as wellas developing accurate measurement techniques.

Contact: David G. Seiler, 301-975-2054

PHYSICS OF SEMICONDUCTORDEVICES AND C AND BN NANOTUBES

Theoretical solid-state physics research for elec-tronic applications is in progress in order to un-derstand the operation of advanced electronicdevices and to provide more physically correctand numerically robust carrier transport models.Such transport models are used to interpret mea-surements and to enable predictive computer sim-ulations of electronic devices. For example, topicsinclude densities of states, band structures, high-concentration effects, carrier lifetimes, and carriermobilities. The approach involves careful exami-nation, extension, and experimental verification ofthe theoretical basis used in device models for el-emental and compound semiconductors and formetallic, semiconducting, and insulating nano-tubes. We are interested in extending such researchto include magnetic semiconductors and nano-tubes (spintronics), such as manganese-dopedGaAs.

Contact: Herbert S. Bennett, 301-975-2079

MICROELECTRONIC PACKAGECHARACTERIZATION

Research focuses on the thermal properties of mi-croelectronic packages and interconnects. Ourobjectives are to improve methods for characteriz-ing these properties for advanced packages andmodules; improve measurement methods and tech-niques; and verify “compact” electrical and ther-mal models for packages and modules, and param-eter extraction techniques for the models. We havefully equipped thermal characterization laborato-ries including an infrared thermal imager with µstemporal and 20 µm spatial resolution, and severalcomputer workstations with a compliment of ther-mal and electrical modeling and analysis software.

Contact: David L. Blackburn, 301-975-2068

QUANTUM DEVICES FOR ULSICIRCUITS

The complementary-metal-oxide-semiconductor(CMOS) field-effect-transistor is showing funda-mental limits associated with the laws of quantum


mechanics and the limitations of fabrication tech-niques. This is driving research on innovative so-lutions to augment or replace CMOS technologies.Quantum devices such as quantum dots, resonanttunneling devices, and single-electron transistors,deliberately exploit quantum and size effects. Weare interested in fundamental research in all as-pects of quantum devices, particularly those thatare compatible with Si technologies. Our interestsinclude, but are not limited to, fabrication, simula-tion, and characterization of device structures andconstituent materials/processes. Our primary ex-pectation is to be able to identify and address crit-ical metrology issues for this emerging technolo-gy of silicon-based quantum devices. In supportof this research, we have a clean room with a vari-ety of fabrication equipment including furnaces,evaporators, and optical and electron-beam lithog-raphy. We have numerous device, electrical, andphysical simulation software available includingthe NanoElectronic Modeling program, NEMO,and the molecular simulation program, CeriusII/CASTEP. We have a wide range of electrical char-acterization equipment that allows device charac-terization at temperatures ranging from approxi-mately 1 K to 700 K. This includes ultra-low noiseprobe stations, cryostats, semiconductor parame-ter analyzers for current-voltage measurements, accapacitance-conductance-inductance measure-ments, specialized setups for Hall and magne-totransport measurements, and a variety of addi-tional electronics. We also have numerous sup-porting analytical measurement techniques avail-able including spectroscopic ellipsometry, atomicforce microscopy, and scanning capacitance mi-croscopy.

Contact: Eric M. Vogel, 301-975-4723, or Curt A.Richter, 301-975-2082

MODELING ADVANCEDSEMICONDUCTOR DEVICES FORCIRCUIT SIMULATION

Accurate circuit simulator models for advancedsemiconductor devices are required for effectivecomputer-aided design of electronic circuits andsystems. However, the semiconductor device mod-els provided in most commercial circuit simulators(e.g., simulation program with integrated circuitemphasis) are based on microelectronic devices,and they do not adequately describe the dynamicbehavior of advanced semiconductor devices.Therefore, research focuses on the following: (1)physics-based models for advanced semiconduc-tor devices such as power and compound semi-

conductor devices (these models are implementedinto available circuit and system simulation pro-grams; (2) parameter extraction algorithms for ob-taining model parameters from terminal electricalmeasurements; and (3) characterization proceduresfor verifying the models’ ability to simulate the be-havior of the devices within application circuits.NIST also works closely with commercial softwarevendors, to make the new models available to cir-cuit design engineers, and has established theNIST/IEEE Working Group on Model Validation todevelop comprehensive procedures for evaluatingthe performance of circuit simulator models. (Formore information, see ray.eeel.nist.gov/modval.html.)

Contact: Allen R. Hefner, Jr., 301-975-2071


The MicroElectroMechanical Systems (MEMS)project focuses on the development of new MEMS-based sensors and actuators for measurement ap-plications. It functions in a multidisciplinary envi-ronment with collaborations in the NIST laborato-ries in Chemistry, Materials Science, Physics, Bio-technology, and Building and Fire Research. Cur-rent activities in the project include thermal-basedelements, mechanically resonant structures, micro-wave elements, and microfluidic systems. Theproject is also developing MEMS test structures,test methods, and standards to characterize de-vice properties for device performance and reli-ability testing. These MEMS-based test structuresare being utilized to characterize thin-film proper-ties in mainline semiconductor fabrication pro-cesses. We are interested in postdoctoral applica-tions not only from individuals who have special-ized in MEMS research but also from individualsof other science disciplines who wish to learnmicrofabrication methods and apply their exper-tise for new measurement applications.

Contact: Michael Gaitan, 301-975-2070

NANOBIOTECHNOLOGY FOR SINGLECELL AND SINGLE MOLECULEMANIPULATION AND MEASUREMENTS

Our work focuses on developing microfluidic sys-tems and nanofluidic restrictions for cell andbiomolecule transport and detection. We are inter-ested in methods to pattern cells on surfaces, celladhesion, sorting, and electronic and electrochemi-cal monitoring of cell activity. We are also inter-ested in nanofluidic systems for DNA, RNA, andprotein transport and detection to determine the


structure and function. This project is part of amultidisciplinary program with collaborations inthe NIST laboratories in Chemistry, Materials Sci-ence, Physics, and Biotechnology. Research willfocus on the development of new fabrication meth-odologies, design and fabrication of new and novelnanofluidic systems, and measurement methods.

Contact: Michael Gaitan, 301-975-2070

RELIABILITY OF INTEGRATED CIRCUITDIELECTRIC FILMS

Aggressive scaling of gate oxide thickness usedin silicon integrated circuits necessitates theunderstanding of physical mechanismsresponsible for dielectric degradation andbreakdown. We are particularly concerned withthe reliability of ultrathin gate oxides that are inthe direct tunneling regime during circuit operation.Research focuses on (1) identifying parameters todetermine the physics of time-dependent dielectricbreakdown of ultrathin dielectric films in thetunneling regime, (2) determining the effectivenessof highly accelerated stress tests to predict long-term reliability of thin dielectric films, (3) relatinganalytical characterization of oxide bulk andinterfaces to electrical behavior, (4) identifying andcontrolling fabrication process parameters thataffect intrinsic and extrinsic failure modes, and (5)characterizing and evaluating alternate dielectricsfor use as substitutes for silicon oxide in advancedcircuit technologies.

Contact: John S. Suehle, 301-975-2247

PHYSICAL AND ELECTRICALPROPERTIES OF ADVANCED GATEDIELECTRIC FILMS

It is increasingly difficult to characterize ultrathingate dielectric films (typically 0.1 nm to 3.0 nm)used in MOS devices as technology drives themever thinner. We are developing electrical testmethods (using conventional techniques such asI-V and C-V, as well as low-temperature magne-totransport techniques) to measure the physicalproperties (e.g., film thickness and permittivity) ofalternate gate dielectric materials such ashigh-κ metal oxides as well as ultrathin SiO2. Elec-trical results are compared with those of opticaland other measurement methods, and fundamen-tal physical models are developed to be effectivefor more than one measurement technique. Be-cause the interface between the dielectric film andthe silicon substrate is critical to understandingthese measurements, we are developing techniques

to characterize buried interfaces (i.e., interfaceroughness) and are determining how the inter-face and physical properties affect device perfor-mance and reliability.

Contact: Eric M. Vogel, 301-975-4723, or Curt A.Richter, 301-975-2082

OPTICAL AND PHYSICALCHARACTERIZATION OF THIN FILMSUSED IN INTEGRATED-CIRCUITDEVICES

The continued scaling of integrated-circuit (IC)technology requires more stringent precision andaccuracy for the optical and physical measure-ments of thin films. Our research involves the de-velopment of optical measurement techniques,specifically spectroscopic ellipsometry and theenhancement of data analyses and modeling. In-put from various physical, optical, and electricaltechniques is needed to improve our knowledgeof the structure and composition of these thinfilms. With a broad collaboration from various thin-film measurement groups within NIST, our re-search will focus on relating the analyses of HR-TEM, scanning probe methods, X-ray reflectance,Fourier-transform infrared, photo reflectance, Ra-man scattering, and various electrical techniquesto improve our understanding of these films andalso validate some of the optical models used inthe analysis of the ellipsometric data. Simple ac-tual IC devices can be fabricated in-house for elec-trical test structures.

Contact: Curt A. Richter, 301-975-2082, NhanV. Nguyen, 301-975-2044, or Eric M. Vogel,301-975-4723


DIVISION HIGHLIGHTS

UNCERTAINTIES OF CD REFERENCE FEATURESSIGNIFICANTLY REDUCED

Researchers in the Electrical Test Structure Me-trology Project, in collaboration with NIST’s MELand ITL along with International SEMATECH(ISMT) and VLSI Standards, have significantlyreduced the uncertainty in critical dimension ref-erence features that were delivered to 10 member-companies of ISMT in September 2004. The im-provement in uncertainty results from the imple-mentation of a new type of HRTEM-target teststructure, the extensive use of SEM (Scanning Elec-tron Microscope) inspection to identify targetswith superior critical dimension (CD) uniformity,and the use of advanced Atomic Force Microsco-py (AFM) implemented at ISMT by NIST’s Manu-facturing Engineering Laboratory personnel onspecial assignment to serve as the transfer metrol-ogy. Researchers anticipate that features on otheravailable chips will eventually be distributed asNIST-traceable artifacts to other end users in thesemiconductor industry for metrology-tool devel-opment by VLSI Standards Corporation.

Example of AFM transfer-calibration from a singleHRTEM target.

SEM image of the new test structure. (The lengths ofthe lines shown are approximately 10 µm.)

The calibration function relating the HRTEM andAFM CDs is derived from measurements of thenew HRTEM-target test structures, each of whichcontains six features with a distribution of drawnlinewidths, on three chips. HRTEM provides theessential absolute primary measurement of CD,since it is traceable to the known spacing of thelattice planes of mono-crystalline silicon. AFMprovides a transfer calibration since HRTEMimaging destroys the chips.

A key attribute of each distributed CD referencefeature is its uncertainty, which is derived statisti-cally from the calibration function which enablestracing the AFM measurements to HRTEM metrol-ogy. The previous generation of reference materi-als, which was delivered in 2001 and used electri-cal CD as the transfer calibration, had uncertain-ties of approximately 14 nm. The second genera-tion units, which are being distributed to ISMT atthis time, have CDs as low as 45 nm. The calculat-ed standard uncertainty ranges upwards from 1.5nm. At this time, the chips are being distributedwith a stated standard uncertainty of no less than4 nm, pending additional analysis by NIST’s Sta-tistical Engineering Division.

SED RESEARCHER DEVELOPS NOVEL 3D XMLBROWSER/EDITORMatthew Aronoff, of the IIEDM Project, hasdeveloped what some have called a “novel” 3DXML Browser/Editor: Hydra3D. The work wasinitiated by a request from RosettaNet which isdeveloping a wide range of XML based informationexchange standards for the printed circuit boardindustry. RosettaNet and many others in theelectronics industry are developing XML-basedstandards and have an appreciation of the benefitsof XML; however, they are not XML experts. Theyinquired as to whether NIST might be able toprovide a tool that could help them manage thecomplexity of the XML based standards they aredeveloping. Aronoff ’s 3D Browser/Editoraccomplishes this by providing a hierarchical 3Dview of any XML document. The tool providesthe user with the ability to view the entiredocument, or only those portions of interest. Thetool allows the user to manipulate the document;e.g., zoom in and out, rotate, search, and filter outportions of the document and save different viewsof the document.

Although the tool is still under furtherdevelopment, several groups both internal andexternal to NIST have requested copies of thesoftware for their own use. BFRL has requestedthe software for use on XML standards they aredeveloping with their construction industrycustomers. MEL researchers have also expressedinterest in the tool. Researchers from Georgia Techhave requested copies of the software.International SEMATECH and SEMI researchershave requested a variation of the software forsupport of XML based standards that they aredeveloping for the semiconductor industry. Thesoftware is currently available on CD ROM andon the Internet (http://hydra3d.sourceforge.net).The software runs on Linux and Windows. A Macversion has also been completed and will beavailable pending optimizations.

A user’s guide for the tool was published as aNIST internal report, and a paper on the tool waspresented at the Extreme Mark-Up Conference inAugust 2004. It is hoped that commercial XMLtool providers who heard about the tool at theconference will consider adopting Aronoff’s ideasinto some of their products.

Screenshot of the Hydra3D XML Browser/Editor.


SED WRITES FIRST MEMS STANDARDS

The first MicroElectroMechanical Systems(MEMS) standards in the world were published inthe Annual Book of ASTM Standards in thesummer of 2003. The three standard test methodsare for measuring in-plane lengths, residual strain,and strain gradient.

Written by MEMS Project staff member JanetMarshall (who, for her efforts, received an awardof appreciation from the Committee on Fatigue andFracture), these test methods are based on theresearch and analyses detailed in NIST InteragencyReport 6779. The residual strain and strain gradientstandard calculations can be performed on theNIST Semiconductor Electronics Division Web site(www.eeel.nist.gov/812/test-structures/) tofacilitate quick and easy calculations.

The round robin test chip.

MEMS is a rapidly growing component of the semi-conductor industry. Applications for MEMS de-mand high performance and reliability. The stan-dard test methods are crucial for tightening thevariations in the parametric measurements betweenlaboratories. These international standards areexpected to facilitate international commerce inMEMS technologies and improve manufacturingyields.

All three test methods apply to thin films such asfound in MEMS materials, which can be imagedusing a non-contact optical interferometer. Thefirst test method shows how to measure an in-plane length (or deflection) measurement, giventhat each end is defined by a distinctive out-of-

plane vertical displacement. The second testmethod shows how to calculate the residual strainfrom two cosine functions that are used to modelthe out-of-plane shape of fixed-fixed beams. Thethird test method shows how to measure the straingradient from a circular function that is used tomodel the out-of-plane shape of cantilevers.

A MEMS Length and Strain Round Robin Experi-ment is underway to compare results from thesetest methods. The goal is to demonstrate the re-producibility of measurements performed using thesame test methods at independent laboratories aswell as the repeatability of measurements whenperformed using the same test method, in the samelaboratory, by the same operator with the sameequipment, in the shortest practicable period oftime.

For the round robin, a test chip (the design of whichis shown in the figure) was passed from laboratoryto laboratory, and measurements were taken onrandom test units using the procedures given inthe ASTM standard test methods. Data (i.e., x or yand/or z values) from these measurements are fedinto a NIST web-based program for analysis. Theanalysis also provides a means for verifying thedata before submitting the results to NIST forcollection. Currently, eight laboratories (NIST,Kavlico, Motorola, Lucent Technologies, VeecoMetrology, Zygo, FLX Micro, and Delphi) areparticipants in this round robin. The final resultswill be recorded in the three related ASTM standardtest methods for re-balloting.

These test methods are under the jurisdiction ofASTM Committee E08 on Fatigue and Fracture andare the direct responsibility of SubcommitteeE08.05 on Cyclic Deformation and Fatigue CrackFormation.


NEW MICROFLUIDIC DNA ANALYSIS SYSTEM FORFORENSICS APPLICATIONS DEMONSTRATED

Modern forensic DNA analysis systems are cur-rently based on the separation of DNA fragmentsby capillary electrophoresis, a process which typi-cally takes 30 m. Recognizing an urgent need toimprove the efficiency, speed, and accuracy of theDNA testing to alleviate a growing backlog of fo-rensic DNA testing for criminal cases, The Depart-ment of Justice has requested NIST’s guidance onthe development of new measurement technologyfor DNA separation. Using a newly developedmicrofluidic device, NIST researchers in EEEL andCSTL have demonstrated a separation of a DNAladder with fragments ranging from 50 to 550 basepairs in 4 m.

The three phases of DNA testing. NIST efforts arefocused on the “Laboratory Analysis” phase.

This effort to develop a rapid DNA Analysis Sys-tem for Forensics using microfluidic systems isbeing sponsored by the Department of Justice(National Institute of Justice, Office of Science andTechnology, Investigative and Forensic SciencesDivision’s Program on DNA Research and Devel-opment). The research team will draw on its exten-sive expertise in microfluidics, microfabrication,DNA separations, as well as state-of-the-art op-tics and detection to build a prototype system thatcan be used as a model to demonstrate the advan-tages of applying these latest technologies forforensic identification. There are two overall re-quirements that must be satisfied to meet the needsof the Department of Justice: (1) development of areliable, easy-to-use, high-throughput, microflu-idics-based system that is smaller and faster (by afactor of 10) than capillary-based techniques; and(2) validation of the system that would supportthe adoption of this technology by the judicialsystem.

A final goal of this effort is to develop a devicethat will integrate sample preparation functionalitywith the current DNA separation process. It isanticipated that this integration will furtherdecrease the laboratory analysis time. Theprototype of such a device is pictured below.

Prototype 16 channel device for DNA finger-printing.

Microfluidic technology is a promising alternativeto capillary-based techniques due to its great po-tential to miniaturize, simplify, integrate, automate,and multiplex the analysis with higher throughputand speed. Although DNA analysis systems basedon microfluidics technology have been recentlycommercialized for DNA sequencing applications,these systems do not meet the specific needs ofthe forensic community due to poor separationresolution of the relatively long fragments (order100 bps to 400 bps) as well as incompatibility withstandard test procedures.

The team involved in this effort includes theSemiconductor Electronics Division (EEEL), theAnalytical Chemistry Division (CSTL), the NIH,Northwestern University, and Cambridge Researchand Instrumentation of Woburn, Massachusetts.


PATTERNING PDMS SURFACES WITH MICROFLUIDICNETWORKS PROVIDES FOUNDATION FORBIOELECTRONICS

The EEEL NIST Director has recently awarded a 3-year collaborative effort to the MEMS Project(Semiconductor Electronics Division) and the Elec-tromagnetic Properties of Materials Project (Elec-tromagnetics Division) entitled Bioelectronics.The overall goal of this effort is to develop meth-ods in EEEL to interface microelectronic and mi-crowave circuits to single cells or small cell clus-ters. As such, Bioelectronics is an interdiscipli-nary field that integrates elements of chemistry,biology, physics, electronics, nano- and biotech-nology, and materials science.

One of the first outcomes of bioelectronics is anew method to pattern neural (retinal) cells onbiocompatible non-biological cell adhesivematerials; an important first-step towards our goalto interface them to microelectrodes, micro-electrochemical cells, and microwave circuits. Thiswork has been recently reported in the journalLangmuir by Darwin R. Reyes, Elizabeth M.Perruccio, S. Patricia Becerra, Laurie E. Locascio,and Michael Gaitan entitled “MicropatterningNeuronal Cells on Polyelectrolyte Multilayers”(Langmuir 2004, 20, 8805-8811).

Fluorescent images of the cytoskeleton and nuclei ofR28 cells on polystyrene.

This method employs a nanofabrication process,which consists of a sequential deposition of poly-electrolyte layers (PEMs) on polydimethylsiloxane(PDMS), a soft biocompatible polymer material thatis resistant to cell adhesion. The patterned PEMsfilm creates a cell “adhesive” where the cells willpreferentially plate while leaving the bare PDMSsurface free of cells. Our method to pattern thePEMs film on the PDMS is based on using a mi-

crochannel network, placed on PDMS, to flow thepolyelectrolyte over the desired pattern on thePDMS surface. Consecutive steps of rinsing andflowing oppositely charged polyelectrolytes ren-dered the desired patterned multilayer films. Afterthe films were formed and dried, the microchannelnetwork was removed, exposing the PDMS sur-face with a patterned PEMs film on it.

To assess the behavior of cells on the patternedsurfaces, two basic tests were carried out: a viabil-ity test, which reveals if the cells are alive or dead,and a morphological analysis, which determines ifthe shape of the cells changes with the surfaceand chemical composition of the material. The cellswere first seeded on the PEMs/PDMS surface andthen preferentially positioned on the PEM regions.A viability test carried out 24 h after seeding thecells showed normal activity within the cell, dem-onstrating that cells were alive while on the pat-terned biocompatible material. The cell cultureswere allowed to grow for up to 14 d. The morphol-ogy of cells on the PEMs was also observed. Spe-cifically, the major structural proteins that providethe cellular architecture were observed and com-pared in tissue culture material and on the PEMpatterns. The cells looked similar in both materials— when there was enough available space inwhich to grow. In more constrained areas theytended to elongate in order to accommodate ahigher number of cells within the PEM areas. Butin general, they seemed to preserve the same mor-phological appearance.

There is a plethora of information that can begathered from cells almost instantaneously whenthey are interfaced with microelectronic devices.We envision the development of tools to studythe progression of diseases, such as thoseassociated with neuron degeneration, by creatingarray of cells that could be interrogated in parallel.Also, we foresee the development of pioneerelectronic methods to probe cellular activity andto improve cell handling and culturing.

This work was done in a collaboration involvingDarwin R. Reyes and Michael Gaitan fromSemiconductor Electronics Division, LaurieLocascio from Chemical Science TechnologyLaboratory, and Patricia Becerra from the NationalEye Institute of the NIH.


SED LEADERSHIP PRODUCES UNIQUE STANDARD ONTIME-DEPENDENT BREAKDOWN OF ULTRA-THINGATE DIELECTRICS

Dr. John Suehle, leader of the Advanced MOSDevice Reliability and Characterization Project,chaired the committee that developed the newJEDC (Joint Electron Device Engineering Council)standard: JESD92, “Procedure for CharacterizingTime-Dependent Dielectric Breakdown of Ultra-Thin Gate Dielectrics.” Dr. Suehle is the Chairmanof the JEDEC JC14.2 Working Group on DielectricReliability. This new standard was published inAugust 2003.

This standard is the first of its kind to define aconstant voltage stress test procedure for charac-terizing time-dependent dielectric breakdown or“wear-out” of the newer ultra-thin (2 nm or below)gate dielectrics. The standard uses special tech-niques to detect breakdown in ultra-thin oxidefilms that exhibit large tunneling currents and softor noisy breakdown characteristics. Representa-tives from a majority of the U.S. semiconductorindustry provided input in the development of thestandard. It will be used in the qualification of gatedielectric processes in domestic and overseassemiconductor manufacturing facilities. The stan-dard is available to view on-line free-of-charge atwww.jedec.org/-download/search/JESD92.pdf.

As the semiconductor industry continues toincrease integrated circuit performance bydecreasing the lateral dimensions of metal-oxide-semiconductor (MOS) devices, the thickness ofthe gate dielectric, which is projected to continueto be in use over the next five years, must also bescaled downward. The thickness of the gatedielectric in state-of-the-art microprocessors is2.0 nm or below and will continue to decrease overthe next several years, leading to serious concernsabout the reliability of the gate dielectric.

Stress gate current vs. time and gate current noise vs.time for a 2.0 nm thick SiO2 film with an area of4 x 10-6 cm2. The onset of breakdown is detected by a>500X increase in the current noise.


CONGRESSMAN WOLF VISITS MEMS LABORATORY

House Appropriations Subcommittee on Com-merce, Justice, State, the Judiciary, and RelatedAgencies Chairman Frank Wolf (R-VA) visited theNIST Gaithersburg, Maryland, campus on April20, 2004. Under Secretary of Commerce for Tech-nology Phillip Bond; Arden Bement, NIST Direc-tor/Acting National Science Foundation Director;Hratch Semerjian, NIST Deputy Director/ActingDirector; Dave Karmol, American National Stan-dards Institute Vice President of Public Policy andGovernment Affairs; and Verna Hines, NIST Di-rector of the Office of Congressional and Legisla-tive Affairs, accompanied Wolf.

Chairman Wolf visited the MEMS Laboratory,where he heard about DNA forensics anddiagnostics testing research.

Chairman Wolf stated that he was impressed withNIST staff and programs. He added that NIST’sactivities should be more visible, and that NIST

Hratch Semerjian, Arden Bement, Frank Wolf, PhillipBond, and Dave Karmol.

Phillip Bond, Michael Gaitan, Frank Wolf, Laurie Locasio, and Jayna Shah.

should devote greater effort to getting the wordout to the highest levels of industry, and specifi-cally to Congress.


SED LEADS MAJOR SEMICONDUCTOR METROLOGYCONFERENCE SERIES

Dr. David Seiler, Chief of the Semiconductor Elec-tronics Division, provided critical leadership andco-chaired the 2005 International Conference onCharacterization and Metrology for ULSI Tech-nology, which was held in March 2005 at the Uni-versity of Texas at Dallas. This was the fifth meet-ing in the only conference series devoted exclu-sively to characterization and metrology for theULSI silicon industry. The conference assembledhundreds of attendees from industry, government,and universities from around the world. The con-ference proceedings, to be published by theAmerican Institute of Physics in a hard-boundvolume with CD-ROM, will be published in fall2005.

Cover of the proceedings for the 2003 InternationalConference on Characterization and Metrology forULSI Technology, which was published in September2003.

“SED’s role in the

organization of the

ongoing International

Conference on Charac-

terization and Metrology

for ULSI [ultralarge-scale

integration] Technology

is seen as a particularly

valuable leadership

activity.”


Led and co-sponsored by NIST, the conferenceseries provides a forum to present and discusscritical issues, future directions, and key measure-ment capabilities and limitations related to themanufacture and diagnostics of silicon devices.The conferences consist of invited presentationsessions and poster sessions for contributed pa-pers, which cover new developments in charac-terization/metrology technology.

Among the many distinguished members of thesemiconductor industry scheduled to speak at theconference were Bob Helms (UT Dallas), MichaelPolcari (International SEMATECH), Hans Stork(Texas Instruments), Dan Hutcheson (VLSIResearch, Inc.), and Alain Diebold (InternationalSEMATECH).

Keynotes speakers from past conferences in thisseries include Craig Barrett (President, Intel), MarkMelliar-Smith (President and CEO of SEMATECH),Dennis Buss (Vice-President of Mixed-SignalTechnology, Texas Instruments), and Kenneth L.Schroeder (President and CEO of KLA-Tencor).1

Other sponsors for the 2005 conference includedInternational SEMATECH, Semiconductor Inter-national, the American Physical Society, the Na-tional Science Foundation, Semiconductor Equip-ment and Materials International, SemiconductorResearch Corporation, and the University of Tex-as at Dallas.

For additional information on the conferenceseries, or to view slides from many of the invitedpresentations, visit the conference website atwww.eeel.nist.gov/812/conference/.

1 Titles and affiliations were those held at the timeof presentation.


NIST’S GAITHERSBURG, MARYLAND, CAMPUS ANDSURROUNDING AREA

NIST MISSION –

To develop and promote

measurement, stan-

dards, and technology to

enhance productivity,

facilitate trade, and

improve the quality of

life.

NIST VISION –

To be the global leader in

measurement and

enabling technology,

delivering outstanding

value to the nation.

ABOUT NISTThe National Institute of Standards and Technol-ogy (NIST) is an agency of the U.S. Department ofCommerce’s Technology Administration. NIST wasestablished in 1901 by Congress “to assist indus-try in the development of technology ... needed toimprove product quality, to modernize manufac-turing processes, to ensure product reliability ...and to facilitate rapid commercialization ... of prod-ucts based on new scientific discoveries.”

LOCATION

Located approximately 40 km northwest ofWashington, D.C., on a 234 hectare campus, NISTGaithersburg offers the advantages of being inclose proximity to government offices, whilemaintaining the seclusion of a rural setting. Thesite is beautifully landscaped and features maturetrees and ponds, as well as a herd of white-taileddeer and gaggles of Canada geese. Walking pathsand picnic areas provide easy and pleasant accessfor outdoor repasts, biking, walking, and jogging.The campus also is easily accessible, with a shuttleservice to a nearby metro (subway) station and isin close proximity to near three major airports.

NIST’s 11-story Administration Building.

STAFF

NIST’s staff is composed of about 3,300 scientists,engineers, technicians, business specialists, andadministrative personnel. About 1,500 visitingresearchers complement the staff. In addition, NISTpartners with 2,000 manufacturing specialists andstaff at affiliated centers around the country.

SOME NEARBY ATTRACTIONS

LandmarksBureau of Engraving and PrintingCapitol BuildingFord’s TheaterFranklin Delano Roosevelt MemorialI.R.S. BuildingJ. Edgar Hoover F.B.I. BuildingJefferson MemorialLibrary of CongressLincoln MemorialNational ArchivesSupreme CourtUnion StationVietnam Veterans MemorialWashington MonumentWhite House

The NIST Gaithersburg, Maryland campus is home tomany different types of wildlife.

“Washington is located

in a region that is rich in

historic lore and natural

beauty. From the

bustling sounds of a

Chesapeake Bay harbor

to the utter stillness of a

Blue Ridge mountaintop,

from the small, old

tobacco farms of

southern Maryland to the

grand estates of

Virginia’s hunt country,

you will find a richness of

scenery and history.”

“Welcome to Washington”brochure, National ParkService, U.S. Department ofthe Interior

Museums and Other AttractionsCapital Children’s MuseumCorcoran GalleryKennedy CenterMCI CenterNational Geographic SocietyNational Sports GalleryNational TheaterSmithsonian InstituteUnited States Holocaust Memorial Museum

Outdoor AttractionsAntietam National Battlefield SiteC&O Canal National Historical ParkClara Barton National Historic SiteEisenhower National Historic SiteFort McHenryFort WashingtonGettysburg National Military ParkGlen Echo ParkGreat Falls ParkGreenbelt ParkMount VernonOxon Hill FarmPrince William Forest ParkRock Creek ParkShenandoah National ParkWolf Trap Farm Park for the Performing Arts


Division/Office Publication Editor: Erik M. Secula

Publication Coordinator: Erik M. Secula

Printing Coordinators: Deirdre McMahonIlse Putman

Document Production: Technology & Management Services, Inc.Gaithersburg, Maryland

January 2005

For additional information contact:Telephone: (301) 975-2054Facsimile: (301) 975-6021On the Web: http://www.eeel.nist.gov/812/

Electronics and Electrical Engineering Laboratory ... · Some of these projects are supported by...

Documents

Transcript of Electronics and Electrical Engineering Laboratory ... · Some of these projects are supported by...