EN2022: Laboratory Practice Electronic Laboratory Experiment: 01

Logic FamiliesPost-Laboratory Exercise

S.S.JayawardenaS.W.H.M.S.P.Herath S.S.Ruwan PathiranaGroup No: T5Name: S.W.H.M.S.P.HerathGroup Members:Admission No: 090181JDate of Experiment: 30/09/2010Date of Submission: 14/10/2010

1. Diode Logic1.1. By looking at the observations in table01 what can you say about the two diodes used forthis part of the experiment? A(input1)B(input2)Z(Output)

0v0v1.0v

0v5v1,0v

5v0v1.0v

Table 15v5v3.6v

We cant get exactly 0V for logic 0 and 5V for logic 1 because two diodes perform deviation from their ideal characteristics. We can solve this specifying threshold voltage values for logic 0 and 1 1.2. By looking at the observations in table 02 how many different logic low voltages thatyou can observe? (you can consider the threshold value as 2.5V) Hence predict effecton output voltage when the cascade level increases.Diodes we used are not ideal. And three different low voltages are observed they are 1.0V, 1.5V and 1.6V. So there were slight variations of all the low voltages, when the output voltage is in high, the output voltage will rise to 3.5V. It maybe goes into the forbidden zone, which is unspecified voltage zone. When we increase cascade manner that will be limited for few number of circuits.

1.3. Comment on the limitations/drawbacks of the diode logic family in terms of fan-out. The fan-out of the diode logic family is lower compared to the other families. The output of the gate tends to reach the undefined voltage range when we adding a new diode. So the maximum number of gates that can be connected together is lower. Therefore it may have a small fan-out value. Also it may have low noise margin.2. Resistor Transistor Logic2.1 Calculate the power dissipation of the RTL NAND gate shown in Fig.03 in the lab sheet.You may separately calculate the power dissipation for the two scenarios that were testedunder 2.1 and 2.2 in the lab sheet.

Case 01: Current drawn from the supply = 0.1/120 ~ 0 mA

Hence: - Power dissipation of the RTL NAND gate = 0 W

Case 02: Current drawn from the supply = 4.0/120 = 33.333 mA

Hence: - Power dissipation of the RTL NAND gate = (33.33310-3)2120 = 0.133 WCase 03: Current drawn from the supply = 0.075/470 ~ 0 mA

Hence:- Power dissipation of the RTL NAND gate = 0 W

Case 04: Current drawn from the supply = 4.0/470 = 8.511 mA

Hence:- Power dissipation of the RTL NAND gate = (8.51110-3)2470 = 0.034 W 2.2 Comment on the effect of resistor values on the gate power dissipation. According to our observations, when the resistor values increase, the power dissipation will decrease.

2.3 Comment on the effect of resistor values on the gate propagation delay. When we increase the resistor values propagation delay is increased. 3. Diode Transistor Logic3.1 Briefly explain what is meant by noise margin with respect to logic families.

Logic 1 Vih(Min)Logic 2 VIl(Max)Logic 1 VoH(min)Vol(max)Logic 2 NMLow level = VIL(max) Vol(max) NMHigh level =VoH(min) V IH(min)

Noise Margin = Minimum (NM(High), NM(Low))

Noise margins were differing from the different logic families.

3.2 By using the observations in table 03 in your lab sheet calculate the power dissipation ofthe RTL gate you constructed.

Output voltage = 4.3VCurrent drawn = 0.002 A

Power dissipation of the RTL gate = 4.30.002 = 8.6 mW

4. TTL Logic family4.1 Justify the observation you obtained in section 4.2 in the lab sheet. (Briefly explain whythe output looks like what you have observed)

Because of the propagation delay of the ICs output signal behave like a analog signal. But it should be a 1010101.

4.2 Using the observations in the section 4.3 in the lab sheet calculate the per gatepropagation delay of the TTL logic IC you used. Compare this value with the valuementioned in the datasheet of the IC Time of the wave form = 10-6/21.5=46.5 nsPropagation delay per gate = 9.3 ns References[1] Electronic Devices & Circuits (Applied Electronic Vol I) by G.M. Mithal.[2] Digital Electronics (3rd Edition) by Morris Mano