Electronic Chips

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© 2000 Fairchild Semiconductor Corporation DS006439 www.fairchildsemi.com

August 1986

Revised March 2000

D M7 4 L S

0 0 Q u a d 2 - I n p u t N A N D

G a t e

DM74LS00

Quad 2-Input NAND Gate

General DescriptionThis device contains four independent gates each of which

performs the logic NAND function.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function Table

Y = AB

H = HIGH Logic Level

L = LOW Logic Level

Order Number Package Number Package Description

DM74LS00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74LS00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Output

A B Y

L L H

L H H

H L H

H H L



www.fairchildsemi.com 2

D M 7 4 L S 0 0

Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute Maximum Ratings” are those values beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “Recommended Operating Conditions” table will define the conditions

for actual device operation.

Recommended Operating Conditions

Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)

Note 2: All typicals are at VCC = 5V, TA = 25°C.

Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristicsat VCC = 5V and TA = 25°C

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

TA Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions MinTyp

Max Units(Note 2)

VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max,2.7 3.4 V

Output Voltage VIL = Max

VOL LOW Level VCC = Min, IOL = Max,0.35 0.5

Output Voltage VIH = Min V

IOL = 4 mA, VCC = Min 0.25 0.4

II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.36 mA

IOS Short Circuit Output Current VCC = Max (Note 3) −20 −100 mA

ICCH Supply Current with Outputs HIGH VCC = Max 0.8 1.6 mA

ICCL Supply Current wi th Outputs LOW VCC = Max 2.4 4.4 mA

RL = 2 kΩ

Symbol Parameter CL = 15 pF CL = 50 pF Units

Min Max Min Max

tPLH Propagation Delay Time3 10 4 15 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time3 10 4 15 ns

HIGH-to-LOW Level Output



3 www.fairchildsemi.com

D M7 4 L S

0 0

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

Package Number M14A




D M 7 4 L S 0 0

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M14D




D M7 4 L S

0 0 Q u a d 2 - I n p u t N A N D

G a t e


14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to theuser.

2. A critical component in any component of a life supportdevice or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com




May 1986

Revised March 2000

D M7 4 L S

0 2 Q u a d 2 - I n p u t N OR

G a t e

DM74LS02

Quad 2-Input NOR Gate


performs the logic NOR function.

Ordering Code:




L = LOW Logic Level





Y = A + B

Inputs Output

A B Y

L L H

L H L

H L L

H H L




D M 7 4 L S 0 2













Supply Voltage 7V

Input Voltage 7V

Operating Free AirTemperatureRange 0°C to +70°C










Max Units(Note 2)






IOL = 4 mA, VCC = Min 0.25 0.4







RL = 2 kΩ


Min Max Min Max

tPLH Propagation Delay Time13 18 ns


tPHL Propagation Delay Time10 15 ns





D M7 4 L S

0 2



Package Number M14A




D M 7 4 L S 0 2






D M7 4 L S

0 2 Q u a d 2 - I n p u t N OR

G a t e




LIFE SUPPORT POLICY















August 1986

Revised March 2000

D M7 4 L S

0 8 Q u a d 2 - I n p u t A N D

G a t e s

DM74LS08

Quad 2-Input AND Gates


performs the logic AND function.

Ordering Code:



Y = AB


L = LOW Logic Level





Inputs Output

A B Y

L L L

L H L

H L L

H H H




D M 7 4 L S 0 8













Supply Voltage 7V

Input Voltage 7V











Max Units(Note 2)



Output Voltage VIH = Min


Output Voltage VIL = Max V

IOL = 4 mA, VCC = Min 0.25 0.4







RL = 2 kΩ


Min Max Min Max








D M7 4 L S

0 8



Package Number M14A




D M 7 4 L S 0 8






D M7 4 L S

0 8 Q u a d 2 - I n p u t A N D

G a t e s


14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A


LIFE SUPPORT POLICY















August 1986

Revised March 2000

D M7 4 L S

1 0 T r i pl e 3 - I n p u t N A N D

G a t e

DM74LS10

Triple 3-Input NAND Gate

General DescriptionThis device contains three independent gates each of

which performs the logic NAND function.

Ordering Code:



Y = ABC


L = LOW Logic Level

X = Either LOW or HIGH Logic Level




Inputs Output

A B C Y

X X L H

X L X H

L X X H

H H H L




D M 7 4 L S 1 0













Supply Voltage 7V

Input Voltage 7V











Max Units(Note 2)






IOL = 4 mA, VCC = Min 0.25 0.4





ICCH Supply Current with Outputs High VCC = Max 0.6 1.2 mA

ICCL Supply Current with Outputs Low VCC = Max 1.8 3.3 mA

RL = 2 kΩ


Min Max Min Max








D M7 4 L S

1 0



Package Number M14A




D M 7 4 L S 1 0 T r i p l e 3 - I n p u t N A

N D

G a t e




LIFE SUPPORT POLICY















August 1986

Revised March 2000

D M7 4 L S

1 1 T r i pl e 3 - I n p u t A N D

G a t e

DM74LS11

Triple 3-Input AND Gate

General DescriptionThis device contains three independent gates each of

which performs the logic AND function.

Ordering Code:



Y = ABC


L = LOW Logic Level





Inputs Output

A B C Y

X X L L

X L X L

L X X L

H H H H




D M 7 4 L S 1 1













Supply Voltage 7V

Input Voltage 7V











Max Units(Note 2)


VOH HIGH Level VCC = Min, IOH = Max2.7 3.4 V


VOL LOW Level VCC = Min, IOL = Max0.35 0.5


IOL = 4 mA, VCC = Min 0.25 0.4







RL = 2 kΩ


Min Max Min Max








D M7 4 L S

1 1



Package Number M14A




D M 7 4 L S 1 1 T r i p l e 3 - I n p u t A

N D

G a t e




LIFE SUPPORT POLICY















June 1986

Revised March 2000

D M7 4 L S

2 0 D u al 4 - I n p u t N A N D

G a t e

DM74LS20

Dual 4-Input NAND Gate

General DescriptionThis device contains two independent gates each of which

performs the logic NAND function.

Ordering Code:



Y = ABCD


L = LOW Logic Level





Inputs Output

A B C D Y

X X X L H

X X L X H

X L X X H

L X X X H

H H H H L




D M 7 4 L S 2 0













Supply Voltage 7V

Input Voltage 7V











Max Units(Note 2)






IOL = 4 mA, VCC = Min 0.25 0.4







RL = 2 kΩ


Min Max Min Max








D M7 4 L S

2 0



Package Number M14A




D M 7 4 L S 2 0 D u a l 4 - I n p u t N A

N D

G a t e




LIFE SUPPORT POLICY















June 1986

Revised March 2000

D M7 4 L S

3 2 Q u a d 2 - I n p u t OR

G a t e

DM74LS32

Quad 2-Input OR Gate


performs the logic OR function.

Ordering Code:



Y = A + B


L = LOW Logic Level





Inputs Output

A B Y

L L L

L H H

H L H

H H H




D M 7 4 L S 3 2













Supply Voltage 7V

Input Voltage 7V











Max Units(Note 2)






IOL = 4 mA, VCC = Min 0.25 0.4







RL = 2 kΩ


Min Max Min Max








D M7 4 L S

3 2



Package Number M14A




D M 7 4 L S 3 2






D M7 4 L S

3 2 Q u a d 2 - I n p u t OR

G a t e




LIFE SUPPORT POLICY















October 1988

Revised March 2000

D M7 4 L S

4 7 B C D t o7 - S e gm en t D e c o d er / D r i v er wi t h O p en- C ol l e c t or

O u t p u t s

DM74LS47

BCD to 7-Segment Decoder/Driver withOpen-Collector Outputs

General DescriptionThe DM74LS47 accepts four lines of BCD (8421) input

data, generates their complements internally and decodesthe data with seven AND/OR gates having open-collector

outputs to drive indicator segments directly. Each segment

output is guaranteed to sink 24 mA in the ON (LOW) state

and withstand 15V in the OFF (HIGH) state with a maxi-

mum leakage current of 250 µA. Auxiliary inputs providedblanking, lamp test and cascadable zero-suppression func-tions.

Featuress Open-collector outputs

s Drive indicator segments directly

s Cascadable zero-suppression capability

s Lamp test input

Ordering Code:


Logic Symbol

VCC = Pin 16

GND = Pin 8

Connection Diagram

Pin Descriptions

Note 1: OC—Open Collector



DM74LS47N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

A0–A3 BCD Inputs

RBI Ripple Blanking Input (Active LOW)

LT Lamp Test Input (Active LOW)

BI/RBO Blanking Input (Active LOW) or

Ripple Blanking Output (Active LOW)

a –g Segment Outputs (Active LOW) (Note 1)




D M 7 4 L S 4 7

Truth Table

Note 2: BI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held at a HIGH

level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blanking or a decimal 0 is not

desired. X = input may be HIGH or LOW.

Note 3: When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a HIGH level regardless of the state of any other input

condition.

Note 4: When ripple-blanking input (RBI) and inputs A0, A1, A2 and A3 are LOW level, with the lamp test input at HIGH level, all segment outputs go to a

HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition).Note 5: When the blanking input/ripple-blanking output (BI/RBO) is OPEN or held at a HIGH level, and a LOW level is applied to lamp test input, all segment

outputs go to a LOW level.

Functional DescriptionThe DM74LS47 decodes the input data in the pattern indi-

cated in the Truth Table and the segment identification

illustration. If the input data is decimal zero, a LOW signalapplied to the RBI blanks the display and causes a multi-

digit display. For example, by grounding the RBI of the

highest order decoder and connecting its BI/RBO to RBI of

the next lowest order decoder, etc., leading zeros will be

suppressed. Similarly, by grounding RBI of the lowest orderdecoder and connecting its BI/RBO to RBI of the next high-est order decoder, etc., trailing zeros will be suppressed.

Leading and trailing zeros can be suppressed simulta-

neously by using external gates, i.e.: by driving RBI of a

intermediate decoder from an OR gate whose inputs are

BI/RBO of the next highest and lowest order decoders. BI/

RBO also serves as an unconditional blanking input. Theinternal NAND gate that generates the RBO signal has a

resistive pull-up, as opposed to a totem pole, and thus BI/

RBO can be forced LOW by external means, using wired-

collector logic. A LOW signal thus applied to BI/RBO turns

off all segment outputs. This blanking feature can be usedto control display intensity by varying the duty cycle of theblanking signal. A LOW signal applied to LT turns on all

segment outputs, provided that BI/RBO is not forced LOW.

DecimalInputs Outputs

or Note

Function LT RBI A3 A2 A1 A0 BI/RBO a b c d e f g

0 H H L L L L H L L L L L L H (Note 2)

1 H X L L L H H H L L H H H H (Note 2)

2 H X L L H L H L L H L L H L

3 H X L L H H H L L L L H H L

4 H X L H L L H H L L H H L L

5 H X L H L H H L H L L H L L

6 H X L H H L H H H L L L L L

7 H X L H H H H L L L H H H H

8 H X H L L L H L L L L L L L

9 H X H L L H H L L L H H L L

10 H X H L H L H H H H L L H L

11 H X H L H H H H H L L H H L

12 H X H H L L H H L H H H L L

13 H X H H L H H L H H L H L L

14 H X H H H L H H H H L L L L

15 H X H H H H H H H H H H H H

BI X X X X X X L H H H H H H H (Note 3)

RBI H L L L L L L H H H H H H H (Note 4)

LT L X X X X X H L L L L L L L (Note 5)




D M7 4 L S

4 7

Logic Diagram

Numerical Designations—Resultant Displays




D M 7 4 L S 4 7









Note 7: OFF-State at a–g.

Electrical CharacteristicsOver recommended operating free air temperature range (unless otherwise noted)



Switching Characteristicsat VCC = +5.0V, TA = +25°C

Note 10: LT = HIGH, A0–A3 = LOW

Supply Voltage 7V

Input Voltage 7V







IOH HIGH Level Output Current−250 µA

a − g @ 15V = VOH (Note 7)

IOH HIGH Level Output Current BI /RBO −50 µA




Max Units(Note 8)



Output Voltage VIL = Max, BI /RBO

IOFF Output HIGH Current Segment Outputs VCC = 5.5V, VO = 15V a − g 250 µA


Output Voltage VIH = Min, a − g

IOL = 3.2 mA, BI /RBO 0.5 V

IOL = 12 mA, a –g 0.25 0.4

IOL = 1.6 mA, BI /RBO 0.4II Input Current @ Max VCC = Max, VI = 7V

100 µAInput Voltage VCC = Max, VI = 10V



IOS Short Circuit VCC = Max (Note 9),mA

Output Current IOS at BI/RBO −0.3 −2.0

ICC Supply Current VCC = Max 13 mA

RL = 665Ω

Symbol Parameter Conditions CL = 15 pF Units

Min MaxtPLH Propagation Delay 100

nstPHL An to a –g 100

tPLH Propagation Delay 100ns

tPHL RBI to a –g (Note 10) 100




D M7 4 L S

4 7



Package Number M16A




D M 7 4 L S 4 7 B C D t o 7 - S e g m e n t D e c o d

e r / D r i v e r w i t h O p e n - C o l l e c t o r

O u t p u t s


16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N16E


LIFE SUPPORT POLICY














TLF10172

D M 7 4 L S 4 8 B

C D t o 7 - S e g m e n t D e c o d

e r

January 1992

DM74LS48

BCD to 7-Segment DecoderGeneral DescriptionThe ’LS48 translates four lines of BCD (8421) input datainto the 7-segment numeral code and provides seven corre-sponding outputs having pull-up resistors as opposed to

totem pole pull-ups These outputs can serve as logic sig-nals with a HIGH output corresponding to a lighted lamp

segment or can provide a 13 mA base current to npn lamp

driver transistors Auxiliary inputs provide lamp test blank-ing and cascadable zero-suppression functions

The ’LS48 decodes the input data in the pattern indicated in

the Truth Table and the segment identification illustration

Connection Diagram

Dual-In-Line Package

TLF10172–1

Order Number DM74LS48M or DM74LS48N

See NS Package Number M16A or N16E

C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A



Absolute Maximum Ratings (Note)

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature RangeDM74LS 0C to a70C

Storage Temperature Range b65C to a150C

Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The

parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings

The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation


Symbol ParameterDM74LS48

UnitsMin Nom Max

VCC Supply Voltage 475 5 525 V

VIH High Level Input Voltage 2 V

VIL Low Level Input Voltage 08 V

IOH High Level Output Current b50 mA

IOL Low Level Output Current 60 mA

TA Free Air Operating Temperature 0 70 C

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units(Note 1)

VI Input Clamp Voltage VCC e Min II e b18 mA b15 V

VOH High Level Output VCC Min IOH e Max24 V

Voltage VIL e Max

IOFF Output High Current VCC e Min VO e 085Vb13 mA

Segment Outputs

VOL Low Level Output VCC e Min IOLe Max05

Voltage VIH e Min V

IOLe 20 mA VCCe Min 04

II Input Current Max VCC e Max VI e 7V01 mA

Input Voltage

IIH High Level Input Current VCC e Max VI e 27V 20 mA

IIL Low Level Input Current VCCe

Max VIe

04Vb

04 mAIOS Short Circuit VCC e Max VO e 0V

b03 b2 mAOutput Current at BIRBO (Note 2)

ICCH Supply Current VCC e Max VIN e 45V 38 mA

Note 1 All typicals are at VCC e 5V TA e 25C

Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second

Switching Characteristics at VCC e 5V and TA e 25C

Symbol ParameterCL e 15 pF

UnitsMin Max

tPLH Propagation Delay Time 100ns

tPHL An to a–g 100

tPLH Propagation Delay Time 100ns

tPHL RBI to a–f 100

Note LT e HIGH A0–A 3 e HIGH

2



Numerical DesignationsResultant Displays

TLF10172–4

Truth TableDecimal Inputs Outputs

Or

FunctionLT RBI A3 A2 A1 A0 BIRBO a b c d e f g

0 (Note 1) H H L L L L H H H H H H H L

1 (Note 1) H X L L L H H L H H L L L L

2 H X L L H L H H H L H H L H

3 H X L L H H H H H H H L L H

4 H X L H L L H L H H L L H H

5 H X L H L H H H L H H L H H

6 H X L H H L H L L H H H H H

7 H X L H H H H H H H L L L L

8 H X H L L L H H H H H H H H

9 H X H L L H H H H H L L H H10 H X H L H L H L L L H H L H

11 H X H L H H H L L H H L L H

12 H X H H L L H L H L L L H H

13 H X H H L H H H L L H L H H

14 H X H H H L H L L L H H H H

15 H X H H H H H L L L L L L L

BI (Note 2) X X X X X X L L L L L L L L

RBI (Note 3) H L L L L L L L L L L L L L

LT (Note 4) L X X X X X H H H H H H H H

Note 1 BIRBO is wired-AND logic serving as blanking input (BI) andor ripple-blanking output (RBO) The blanking out (BI) must be open or held at a HIGH level

when output functions 0 through 15 are desired and ripple-blanking input (RBI) must be open or at a HIGH level if blanking of a decimal 0 is not desired X e input

may be HIGH or LOW

Note 2 When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level regardless of the state of any other input

condition

Note 3 When ripple-blanking input (RBI) and inputs A 0 A1 A2 and A3 are at LOW level with the lamp test input at HIGH level all segment outputs go to a LOW

level and the ripple-blanking output (RBO) goes to a LOW level (response condition)Note 4 When the blanking inputripple-blanking output (BIRBO) is open or held at a HIGH level and a LOW level is applied to lamp test input all segment outputs

go to a HIGH level

Logic Symbol

TLF10172–2

VCC e Pin 16

GNDe Pin 8

3



Logic Diagram

TLF10172–3

4



Physical Dimensions inches (millimeters)

16-Lead Small Outline Molded Package (M)

Order Number DM74LS48MNS Package Number M16A

5



D

M 7 4 L S 4 8 B C D t o 7 - S e g m

e n t D e c o d e r

Physical Dimensions inches (millimeters) (Continued)

16-Lead Molded Dual-In-Line Package (N)

Order Number DM74LS48N

NS Package Number N16E

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION As used herein

1 Life support devices or systems are devices or 2 A critical component is any component of a life

systems which (a) are intended for surgical implant support device or system whose failure to perform caninto the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the lifefailure to perform when properly used in accordance support device or system or to affect its safety or

with instructions for use provided in the labeling can effectivenessbe reasonably expected to result in a significant injury

to the user

National Semiconducto r National Semiconduct or Natio nal Semiconducto r National Semiconduct or

Corporation Europe Hong Kong Ltd Japan Ltd1111 West Bardin Road Fax (a4 9) 0 -1 80 -5 30 8 5 8 6 1 3t h F lo or S tr ai gh t B lo ck T el 8 1- 04 3- 29 9- 23 09Arlington TX 76017 Email cnjwget ev m2 n sc c om O ce an C en tr e 5 C an to n R d F ax 8 1- 04 3- 29 9- 24 08Tel 1(800) 272-9959 Deutsch Tel (a49) 0-180-530 85 85 Tsimshatsui KowloonFax 1(800) 737-7018 Eng lish Tel (a49 ) 0- 180 -53 2 7 8 32 Ho ng K ong

Franais Tel (a4 9) 0 -1 80 -5 32 9 3 5 8 T el ( 85 2) 2 73 7- 16 00Italiano Tel (a4 9) 0 -1 80 -5 34 1 6 8 0 F ax ( 85 2) 2 73 6- 99 60

National doesnot assumeany responsibilityfor useof anycircuitry described nocircuit patent licenses areimplied and National reserves the right at anytime without noticeto changesaid circuitryand specifications




August 1986

Revised March 2000

D M7 4 L S

7 3 A D u al N e g a t i v e- E d g e- T r i g

g er e d M a s t er - S l av e J - K F l i p- F

l o p swi t h C l e ar an d C om pl em

en t ar y O u t p u t s

DM74LS73A

Dual Negative-Edge-Triggered Master-SlaveJ-K Flip-Flops with Clear and Complementary Outputs

General DescriptionThis device contains two independent negative-edge-trig-

gered J-K flip-flops with complementary outputs. The J andK data is processed by the flip-flops on the falling edge of

the clock pulse. The clock triggering occurs at a voltage

level and is not directly related to the transition time of the

negative going edge of the clock pulse. The data on the J

and K inputs is allowed to change while the clock is HIGHor LOW without affecting the outputs as long as setup andhold times are not violated. A low logic level on the clear

input will reset the outputs regardless of the levels of the

other inputs.

Ordering Code:




L = LOW Logic Level


↓ = Negative going edge of pulse.

Q0 = The output logic level before the indicated input conditions were

established.

Toggle = Each output changes to the complement of its previous level on

each falling edge of the clock pulse.


DM74LS73AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS73AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

CLR CLK J K Q Q

L X X X L H

H ↓ L L Q0 Q0

H ↓ H L H L

H ↓ L H L H

H ↓ H H Toggle

H H X X Q0 Q0




D M

7 4 L S 7 3 A









Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.


Note 4: The symbol (↓) indicates the falling edge of the clock pulse i s used for reference.

Supply Voltage 7V

Input Voltage 7V









fCLK Clock Frequency (Note 2) 0 30 MHz


tW Pulse Width Clock HIGH 20(Note 2) Preset LOW 25 ns

Clear LOW 25

tW Pulse Width Clock HIGH 25

(Note 3) Preset LOW 30 ns

Clear LOW 30

tSU Setup Time (Note 2)(Note 4) 20↓ ns

tSU Setup Time (Note 3)(Note 4) 25↓ ns

tH Hold Time (Note 2)(Note 4) 0↓ ns

tH Hold Time (Note 3)(Note 4) 5↓ ns





D M7 4 L S

7 3 A



Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, wit h feedback from the outputs,

where shorting the outputs to ground may cause the outputs to change logic state, an equivalent test may be performed where V O = 2.125V with the mini-

mum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.

Note 7: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded.



Max Units(Note 5)



Output Voltage VIL = Max, VIH = Min


Output Voltage VIL = Max, VIH = Min V

IOL = 4 mA, VCC = Min 0.25 0.4

II Input Current @ Max VCC = Max J, K 0.1

Input Voltage VI = 7V Clear 0.3 mA

Clock 0.4

IIH HIGH Level VCC = Max J, K 20

Input Current VI = 2.7V Clear 60 µA

Clock 80

IIL LOW Level VCC = Max J, K −0.4

Input Current VI = 0.4V Clear −0.8 mA

Clock −0.8


ICC Supply Current VCC = Max (Note 7) 4 6 mA

From (Input) RL = 2 kΩ

Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units

Min Max Min Max

fMAX Maximum Clock Frequency 30 25 MHz

tPHL Propagation Delay Time Clear20 28 ns

HIGH-to-LOW Level Output to Q

tPLH Propagation Delay Time Clear20 24 ns

LOW-to-HIGH Level Output to Q

tPLH Propagation Delay Time Clock to20 24 ns

LOW-to-HIGH Level Output Q or Q

tPHL Propagation Delay Time Clock to20 28 ns

HIGH-to-LOW Level Output Q or Q




D M

7 4 L S 7 3 A



Package Number M14A




D M7 4 L S

7 3 A D u al N e g a t i v e- E d g e- T r i g

g er e d M a s t er - S l av e J - K F l i p- F

l o p swi t h C l e ar an d C om pl em

en t ar y O u t p u t s




LIFE SUPPORT POLICY















August 1986

Revised March 2000

D M7 4 L S

7 4 A D u al P o si t i v e- E d g e- T r i g g

er e d D F l i p- F l o p swi t h P r e s e t , C l e ar an d C om pl em en t ar y O

u t p u t s

DM74LS74A

Dual Positive-Edge-Triggered D Flip-Flops withPreset, Clear and Complementary Outputs

General DescriptionThis device contains two independent positive-edge-trig-

gered D flip-flops with complementary outputs. The infor-mation on the D input is accepted by the flip-flops on the

positive going edge of the clock pulse. The triggering

occurs at a voltage level and is not directly related to the

transition time of the rising edge of the clock. The data on

the D input may be changed while the clock is LOW orHIGH without affecting the outputs as long as the datasetup and hold times are not violated. A low logic level on

the preset or clear inputs will set or reset the outputs

regardless of the logic levels of the other inputs.

Ordering Code:





L = LOW Logic Level

↑ = Positive-going Transition

Q0 = The output logic level of Q before the indicated input conditions were

established.

Note 1: This configuration is nonstable; that is, it will not persist when either

the preset and/or clear inputs return to t heir inactive (HIGH) level.


DM74LS74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS85ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE I I, 5.3mm Wide

DM74LS74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

PR CLR CLK D Q QL H X X H L

H L X X L H

L L X X H (Note 1) H (Note 1)

H H ↑ H H L

H H ↑ L L H

H H L X Q0 Q0




D M

7 4 L S 7 4 A









Note 3: CL = 15 pF, RL = 2 kΩ, TA = 25°C, and VCC = 5V.

Note 4: CL = 50 pF, RL = 2 kΩ, TA = 25°C, and VCC = 5V.

Note 5: The symbol (↑) indicates the rising edge of the clock pulse is used for reference.

Note 6: TA = 25°C and VCC = 5V.

Supply Voltage 7V

Input Voltage 7V











tW Pulse Width Clock HIGH 18(Note 3) Preset LOW 15 ns

Clear LOW 15

tW Pulse Width Clock HIGH 25

(Note 4) Preset LOW 20 ns

Clear LOW 20

tSU Setup Time (Note 3)(Note 5) 20↑ ns

tSU Setup Time (Note 4)(Note 5) 25↑ ns

tH Hold Time (Note 5)(Note 6) 0↑ ns





D M7 4 L S

7 4 A



Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, wit h feedback from the outputs,

where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.125V with the minimum

and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.

Note 9: With all outputs OPEN, ICC is measured with CLOCK grounded after setting the Q and Q outputs HIGH i n turn.



Max Units(Note 7)






IOL = 4 mA, VCC = Min 0.25 0.4

II Input Current @ Max VCC = Max Data 0.1

Input Voltage VI = 7V Clock 0.1mA

Preset 0.2

Clear 0.2

IIH HIGH Level VCC = Max Data 20

Input Current VI = 2.7V Clock 20µA

Clear 40

Preset 40

IIL LOW Level VCC = Max Data −0.4

Input Current VI = 0.4V Clock −0.4mA

Preset −0.8

Clear −0.8





Min Max Min Max


tPLH Propagation Delay TimeClock to Q or Q 25 35 ns


tPHL Propagation Delay TimeClock to Q or Q 30 35 ns


tPLH Propagation Delay TimePreset to Q 25 35 ns


tPHL Propagation Delay TimePreset to Q 30 35 ns


tPLH Propagation Delay TimeClear to Q 25 35 ns


tPHL Propagation Delay TimeClear to Q 30 35 ns





D M

7 4 L S 7 4 A



Package Number M14A




D M7 4 L S

7 4 A






D M 7 4 L S 7 4 A D u a l P o s i t i v e - E d g e - T r i g g e r e d D F l i p - F l o p s w i t h P r e s

e t , C l e a r a n d C o m p l e m e n t a r y

O u t p u t s




LIFE SUPPORT POLICY














© Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 6

1 Publication Order Number:

SN74LS76A/D

S N 7 4 L S 7 6 A

D u a l J K F l i p - F l o p

w i t h S e t a n d C l e a r

The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and

Direct Clear inputs. These dual flip-flops are designed so that whenthe clock goes HIGH, the inputs are enabled and data will be accepted.

The Logic Level of the J and K inputs will perform according to the

Truth Table as long as minimum set-up times are observed. Input data

is transferred to the outputs on the HIGH-to-LOW clock transitions.

MODE SELECT – TRUTH TABLE

OPERATING INPUTS OUTPUTS

MODE SD CD J K Q Q

Set

Reset (Clear)*Undetermined

Toggle

Load “0” (Reset)

Load “1” (Set)

Hold

L

HL

H

H

H

H

H

LL

H

H

H

H

X

XX

h

l

h

l

X

XX

h

h

l

l

H

LH

q

L

H

q

L

HH

q

H

L

q

* Both outputs will be HIGH while both SD and CD are LOW, but the output

states are unpredictable if SD and CD go HIGH simultaneously.

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Immaterial

l, h (q) = Lower case letters indicate the state of the referenced input

i, h (q) = (or output) one setup time prior to the HIGH–to–LOW clock transition

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 4.75 5.0 5.25 V

TA Operating Ambient

Temperature Range

0 25 70 °C

IOH Output Current – High –0.4 mA

IOL Output Current – Low 8.0 mA

LOW

POWER

SCHOTTKY

Device Package Shipping

ORDERING INFORMATION

SN74LS76AN 16 Pin DIP 2000 Units/Box

SN74LS76AD 16 Pin

http://onsemi.com

2500/Tape & Reel

SOIC

D SUFFIX

CASE 751B

PLASTIC

N SUFFIX

CASE 648

16

1

16

1



SN74LS76A

http://onsemi.com

2

LOGIC DIAGRAM

Q

CLEAR (CD)

J

CLOCK (CP)

K

SET (SD)

Q

LOGIC SYMBOL

16

1

4

15

14

K Q

CP

J Q

SD

VCC = PIN 5

GND = PIN 13

12

6

9

11

10

K Q

CP

J QCD

72

3 8

CD

SD

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter Min Typ Max Unit Test Conditions

VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage for

All Inputs

VIL Input LOW Voltage0.8

VGuaranteed Input LOW Voltage for

All Inputs

VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

VOH Output HIGH Voltage2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth Table

p0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

OL u u0.35 0.5 V IOL = 8.0 mA

IN = IL IH

per Truth Table

p

J, K

Clear

Clock

20

60

80µA VCC = MAX, VIN = 2.7 V

IH u uJ, K

Clear

Clock

0.1

0.3

0.4

mA VCC = MAX, VIN = 7.0 V

IIL Input LOW CurrentJ, K

Clear, Clock

–0.4

–0.8mA VCC = MAX, VIN = 0.4 V

IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

ICC Power Supply Current 6.0 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

Limits



tPLHp

15 20 nsVCC = 5.0 V

C = 15 pFtPHL

oc , ear, e o u pu

15 20 ns

AC SETUP REQUIREMENTS (TA = 25°C)

Limits


tW Clock Pulse Width High 20 ns

tW Clear Set Pulse Width 25 ns

ts Setup Time 20 nsCC = .

th Hold Time 0 ns



SN74LS76A

http://onsemi.com

3

PACKAGE DIMENSIONS

N SUFFIXPLASTIC PACKAGE

CASE 648–08ISSUE R

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

–A–

B

F C

S

HG

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE –T–

MAM0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55B 0.250 0.270 6.35 6.85C 0.145 0.175 3.69 4.44D 0.015 0.021 0.39 0.53F 0.040 0.70 1.02 1.77

G 0.100 BSC 2.54 BSC

H 0.050 BSC 1.27 BSC

J 0.008 0.015 0.21 0.38K 0.110 0.130 2.80 3.30L 0.295 0.305 7.50 7.74M 0 10 0 10S 0.020 0.040 0.51 1.01

_ _ _ _

D SUFFIXPLASTIC SOIC PACKAGE

CASE 751B–05ISSUE J

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATINGPLANE

F

JM

R X 45_

G

8 PLP –B–

–A–

M0.25 (0.010) B S

–T–

D

K

C

16 PL

SBM0.25 (0.010) A ST

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393

B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7P 5.80 6.20 0.229 0.244R 0.25 0.50 0.010 0.019

_ _ _ _



SN74LS76A

http://onsemi.com

4

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

ASIA/PACIFIC: LDC for ON Semiconductor – Asia SupportPhone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

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Fax Response Line: 303–675–2167800–344–3810 Toll Free USA/Canada

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For additional information, please contact your localSales Representative.

SN74LS76A/D

North America Literature Fulfillment:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303–675–2175 or 800–344–3860 Toll Free USA/CanadaFax: 303–675–2176 or 800–344–3867 Toll Free USA/CanadaEmail: [email protected]

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Email: ONlit–[email protected] Phone: (+1) 303–308–7141 (M–F 2:30pm to 5:00pm Toulouse Time)

Email: ONlit–[email protected] Phone: (+1) 303–308–7142 (M–F 1:30pm to 5:00pm UK Time)

Email: [email protected]




August 1986

Revised March 2000

D M7 4 L S

8 3 A

4 - B i t B i n ar yA d d er wi t h F a s t C ar r y

DM74LS83A

4-Bit Binary Adder with Fast Carry

General DescriptionThese full adders perform the addition of two 4-bit binary

numbers. The sum (∑) outputs are provided for each bit

and the resultant carry (C4) is obtained from the fourth bit.

These adders feature full internal look ahead across all fourbits. This provides the system designer with partial look-

ahead performance at the economy and reduced packagecount of a ripple-carry implementation.

The adder logic, including the carry, is implemented in its

true form meaning that the end-around carry can be

accomplished without the need for logic or level inversion.

Featuress Full-carry look-ahead across the four bits

s Systems achieve partial look-ahead performance with

the economy of ripple carry

s Typical add times

Two 8-bit words 25 ns

Two 16-bit words 45 ns

s Typical power dissipation per 4-bit adder 95 mW

Ordering Code:

Connection Diagram


DM74LS83AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide




D M

7 4 L S 8 3 A

Truth Table

H = HIGH Level, L = LOW Level

Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs ∑1 and ∑2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and

B4 are then used to determine outputs ∑3, ∑4, and C4.

Logic Diagram




D M7 4 L S

8 3 A












Note 4: ICC1 is measured with all outputs open, all B inputs LOW and all other inputs at 4.5V, or all inputs at 4.5V.

Note 5: ICC2 is measured with all outputs OPEN and all inputs grounded.

Supply Voltage 7V

Input Voltage 7V











Max Units(Note 2)






IOL = 4 mA, VCC = Min 0.25 0.4

II Input Current @ Max VCC = Max A or B 0.2mA

Input Voltage VI = 7V C0 0.1

IIH HIGH Level VCC = Max A or B 40µA

Input Current VI = 2.7V C0 20

IIL LOW Level VCC = Max A or B −0.8mA

Input Current VI = 0.4V C0 −0.4


ICC1 Supply Current VCC = Max (Note 4) 19 34 mA

ICC2 Supply Current VCC = Max (Note 5) 22 39 mA




D M

7 4 L S 8 3 A



Symbol ParameterTo (Output)

CL = 15 pF C

L = 50 pF Units

Min Max Min Max

tPLH Propagation Delay TimeC0 to ∑1 or ∑2 24 28 ns


tPHL Propagation Delay TimeC0 to ∑1 or ∑2 24 30 ns


tPLH Propagation Delay TimeC0 to ∑3 24 28 ns


tPHL Propagation Delay TimeC0 to ∑3 24 30 ns


tPLH Propagation Delay TimeC0 to ∑4 24 28 ns


tPHL Propagation Delay TimeC0 to ∑4 24 30 ns


tPLH Propagation Delay TimeAi, Bi to ∑i 24 28 ns


tPHL Propagation Delay TimeAi, Bi to ∑i 24 30 ns


tPLH Propagation Delay TimeC0 to C4 17 24 ns


tPHL Propagation Delay TimeC0 to C4 17 25 ns


tPLH Propagation Delay TimeAi, Bi to C4 17 24 ns


tPHL Propagation Delay TimeAi, Bi to C4 17 26 ns





D M7 4 L S

8 3 A

4 - B i t B i n ar yA d d er wi t h F a s t C ar r y




LIFE SUPPORT POLICY












August 1986

Revised March 2000

D M7 4 L S

8 5 4 - B i t M a gni t u d e C om p ar a t or

DM74LS85

4-Bit Magnitude Comparator

General DescriptionThese 4-bit magnitude comparators perform comparison of

straight binary or BCD codes. Three fully-decoded deci-

sions about two, 4-bit words (A, B) are made and are exter-

nally available at three outputs. These devices are fullyexpandable to any number of bits without external gates.

Words of greater length may be compared by connectingcomparators in cascade. The A > B, A < B, and A = B out-

puts of a stage handling less-significant bits are connected

to the corresponding inputs of the next stage handlingmore-significant bits. The stage handling the least-

significant bits must have a high-level voltage applied tothe A = B input. The cascading path is implemented withonly a two-gate-level delay to reduce overall comparison

times for long words.

Featuress Typical power dissipation 52 mW

s Typical delay (4-bit words) 24 ns

Ordering Code:


Connection Diagram

D M 7 4 L S 8 5

Function Table

H = HIGH Level, L = LOW Level, X = Don’t Care

Logic Diagram

Comparing Cascading Outputs

Inputs Inputs

A3, B3 A2, B2 A1, B1 A0, B0 A > B A B A B3 X X X X X X H L L

A3 < B3 X X X X X X L H L

A3 = B3 A2 > B2 X X X X X H L L

A3 = B3 A2 < B2 X X X X X L H L

A3 = B3 A2 = B2 A1 > B1 X X X X H L L

A3 = B3 A2 = B2 A1 < B1 X X X X L H L

A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X H L L

A3 = B3 A2 = B2 A1 = B1 A0 < B0 X X X L H L

A3 = B3 A2 = B2 A1 = B1 A0 = B0 H L L H L L

A3 = B3 A2 = B2 A1 = B1 A0 = B0 L H L L H L

A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L H L L H

A3 = B3 A2 = B2 A1 = B1 A0 = B0 X X H L L H

A3 = B3 A2 = B2 A1 = B1 A0 = B0 H H L L L L

A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L L H H L

D M7 4 L S

8 5












Note 4: ICC is measured with all outputs OPEN, A = B grounded and all other inputs at 4.5V.

Supply Voltage 7V

Input Voltage 7V











Max Units(Note 2)






IOL = 4 mA, VCC = Min 0.25 0.4

II Input Current @ Max VCC = Max A B 0.1 mA

Others 0.3

IIH HIGH Level VCC = Max A B 20 µA

Others 60

IIL LOW Level VCC = Max A B −0.4 mA

Others −1.2

D M 7 4 L S 8 5


From To Number of RL = 2 kΩ

Symbol Parameter Input Output Gate Levels CL = 15 pF C

L = 50 pF Units

Min Max Min Max

tPLH Propagation Delay Time Any A or B A < B,3 36 42

LOW-to-HIGH Level Output Data Input A > B ns

A = B 4 40 40

tPHL Propagation Delay Time Any A or B A < B,3 30 40

HIGH-to-LOW Level Output Data Input A > B ns

A = B 4 30 40

tPLH Propagation Delay TimeA B 1 22 26 ns


tPHL Propagation Delay TimeA B 1 17 26 ns


tPLH Propagation Delay TimeA = B A = B 2 20 25 ns


tPHL Propagation Delay TimeA = B A = B 2 17 26 ns


tPLH Propagation Delay TimeA > B or A = B A B or A = B A < B 1 17 26 ns




D M7 4 L S

8 5



Package Number M16A




D

M 7 4 L S 8 5 4 - B i t M a g n i t u d e C o m p a r a t o r




LIFE SUPPORT POLICY















August 1986

Revised March 2000

D M7 4 L S

8 6 Q u a d 2 - I n p u t E x cl u si v e- OR

G a t e

DM74LS86

Quad 2-Input Exclusive-OR Gate


performs the logic exclusive-OR function.

Ordering Code:



Y = A ⊕ B = A B + AB


L = LOW Logic Level





Inputs Output

A B Y

L L L

L H H

H L H

H H L




D M 7 4 L S 8 6












Note 4: ICCH is measured with all outputs OPEN, one input at each gate at 4.5V, and the other inputs grounded.

Note 5: ICCL is measured with all outputs OPEN and all inputs grounded.


Supply Voltage 7V

Input Voltage 7V











Max Units(Note 2)






IOL = 4 mA, VCC = Min 0.25 0.4





ICCH Supply Current with Outputs HIGH VCC = Max (Note 4) 6.1 10 mA

ICCL Supply Current wi th Outputs LOW VCC = Max (Note 5) 9 15 mA

RL = 2 kΩ

Symbol Parameter Conditions CL = 15 pF CL = 50 pF Units

Min Max Min Max

tPLH Propagation Delay Time Other18 23 ns

LOW-to-HIGH Level Output Input

tPHL Propagation Delay Time Low17 21 ns


tPLH Propagation Delay Time Other

10 15 nsLOW-to-HIGH Level Output Input

tPHL Propagation Delay Time High12 15 ns





D M7 4 L S

8 6



Package Number M14A




D M 7 4 L S 8 6






D M7 4 L S

8 6 Q u a d 2 - I n p u t E x cl u si v e- OR

G a t e




LIFE SUPPORT POLICY















August 1986

Revised March 2000

D M7 4 L S

9 0 D e c a d e an d B i n ar y C o un t er s

DM74LS90

Decade and Binary Counters

General DescriptionEach of these monolithic counters contains four master-

slave flip-flops and additional gating to provide a divide-by-

two counter and a three-stage binary counter for which the

count cycle length is divide-by-five for the DM74LS90.

All of these counters have a gated zero reset and theDM74LS90 also has gated set-to-nine inputs for use in

BCD nine’s complement applications.

To use their maximum count length (decade or four bitbinary), the B input is connected to the QA output. The

input count pulses are applied to input A and the outputs

are as described in the appropriate truth table. A symmetri-cal divide-by-ten count can be obtained from theDM74LS90 counters by connecting the QD output to the A

input and applying the input count to the B input which

gives a divide-by-ten square wave at output QA.

Featuress Typical power dissipation 45 mW

s Count frequency 42 MHz

Ordering Code:


Connection Diagram Reset/Count Truth Table




Reset Inputs OutputR0(1) R0(2) R9(1) R9(2) QD QC QB QA

H H L X L L L L

H H X L L L L L

X X H H H L L H

X L X L COUNT

L X L X COUNT

L X X L COUNT

X L L X COUNT




D M 7 4 L S 9 0

Function Tables

BCD Count Sequence (Note 1)

Bi-Quinary (5-2) (Note 2)

H = HIGH Level

L = LOW Level

X = Don’t Care

Note 1: Output QA is connected to input B for BCD count.

Note 2: Output QD is connected to input A for bi-quinary count.

Note 3: Output QA is connected to input B.

Logic Diagram

The J and K inputs shown without connection are for reference only and

are functionally at a high level.

Count OutputQD QC QB QA

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

Count Output

QA QD QC QB

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 H L L L

6 H L L H

7 H L H L

8 H L H H

9 H H L L




D M7 4 L S

9 0




operated at these limits. The parametric values defined in the “ElectricalCharacteristics” table are not guaranteed at the absolute maximum ratings.








Supply Voltage 7V

Input Voltage (Reset) 7V

Input Voltage (A or B) 5.5V









fCLK Clock Frequency (Note 5) A to QA 0 32 MHz

B to QB 0 16fCLK Clock Frequency (Note 6) A to QA 0 20 MHz

B to QB 0 10

tW Pulse Width (Note 5) A 15

B 30 ns

Reset 15

tW Pulse Width (Note 6) A 25

B 50 ns

Reset 25

tREL Reset Release Time (Note 5) 25 ns

tREL Reset Release Time (Note 6) 35 ns



Max Units(Note 7)




VOL LOW Level VCC = Min, IOL = Max(Note 8)

VOutput Voltage VIL = Max, VIH = Min 0.35 0.5

IOL = 4 mA, VCC = Min 0.25 0.4

II Input Current @ Max VCC = Max, VI = 7V Reset 0.1

mAInput Voltage VCC = Max A 0.2

VI = 5.5V B 0.4

IIH HIGH Level VCC = Max, VI = 2.7V Reset 20

µAInput Current A 40

B 80

IIL LOW Level VCC = Max, VI = 0.4V Reset −0.4

mAInput Current A −2.4

B −3.2

IOS Short Ci rcuit Output Current VCC = Max (Note 9) −20 −100 mA





D M 7 4 L S 9 0

Electrical Characteristics (Continued)Note 8: QA outputs are tested at IOL = Max plus the limit value of I IL for the B input. This permits driving the B input while maintaining full fan-out capability.


Note 10: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.

Switching Characteristics at VCC = 5V and TA = 25°C



Min Max Min Max

fMAX Maximum Clock A to QA 32 20MHz

Frequency B to QB 16 10

tPLH Propagation Delay TimeA to QA 16 20 ns


tPHL Propagation Delay TimeA to QA 18 24 ns


tPLH Propagation Delay TimeA to QD 48 52 ns


tPHL Propagation Delay TimeA to Q

D50 60 ns


tPLH Propagation Delay TimeB to QB 16 23 ns


tPHL Propagation Delay TimeB to QB 21 30 ns


tPLH Propagation Delay TimeB to QC 32 37 ns


tPHL Propagation Delay TimeB to QC 35 44 ns


tPLH Propagation Delay TimeB to QD 32 36 ns


tPHL Propagation Delay TimeB to QD 35 44 ns


tPLH Propagation Delay TimeSET-9 to QA, QD 30 35 ns


tPHL Propagation Delay Time SET-9 to QB, QC 40 48 nsHIGH-to-LOW Level Output

tPHL Propagation Delay TimeSET-0 to Any Q 40 52 ns





D M7 4 L S

9 0



Package Number M14A




D M 7 4 L S 9 0 D e c a d e a n d B i n a r y C o u n t e r s




LIFE SUPPORT POLICY













http://slidepdf.com/reader/full/electronic-chips 82/1515-90

FAST AND LS TTL DATA

DECADE COUNTER;DIVIDE-BY-TWELVE COUNTER;4-BIT BINARY COUNTER

The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed

4-bit ripple type counters partitioned into two sections. Each counter has a di-

vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or

divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-

tion on the clock inputs. Each section can be used separately or tied together

(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of

the counters have a 2-input gated Master Reset (Clear), and the LS90 also

has a 2-input gated Master Set (Preset 9).

• Low Power Consumption . . . Typically 45 mW

• High Count Rates . . . Typically 42 MHz

• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,

Binary

• Input Clamp Diodes Limit High Speed Termination Effects

PIN NAMES LOADING (Note a)

HIGH LOW

CP0 Clock (Active LOW going edge) Input to

÷2 Section

0.5 U.L. 1.5 U.L.


÷5 Section (LS90), ÷6 Section (LS92)

0.5 U.L. 2.0 U.L.


÷8 Section (LS93)

0.5 U.L. 1.0 U.L.

MR1, MR2 Master Reset (Clear) Inputs 0.5 U.L. 0.25 U.L.

MS1, MS2 Master Set (Preset-9, LS90) Inputs 0.5 U.L. 0.25 U.L.

Q0 Output from ÷2 Section (Notes b & c) 10 U.L. 5 (2.5) U.L.

Q1, Q2, Q3 Outputs from ÷5 (LS90), ÷6 (LS92),÷8 (LS93) Sections (Note b)

10 U.L. 5 (2.5) U.L.

NOTES:

a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.

b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)

b. Temperature Ranges.

c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.

d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.

SN54/74LS90SN54/74LS92SN54/74LS93

DECADE COUNTER;DIVIDE-BY-TWELVE COUNTER;

4-BIT BINARY COUNTER

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 632-08

N SUFFIX

PLASTIC

CASE 646-06

14

1

14

1


SN54LSXXJ Ceramic

SN74LSXXN Plastic

SN74LSXXD SOIC

14

1

D SUFFIX

SOIC

CASE 751A-02

LOGIC SYMBOL

1 22

VCC = PIN 5

GND = PIN 10

NC = PINS 4, 13

VCC = PIN 5

GND = PIN 10

NC = PINS 2, 3, 4, 13

VCC = PIN 5

GND = PIN 10

NC = PIN 4, 6, 7, 13

LS90 LS92 LS93

6 7

1 2

14

1

1 2

2 3

MSCP0

CP1MR Q0 Q1 Q2 Q3

12 9 8 11 6 7

14

1

1

CP0

CP1MR Q0 Q1 Q2 Q3

12 9 811

14

1

2 3

CP0

CP1MR Q0 Q1 Q2 Q3

12 9 8 11




SN54/74LS90 •SN54/74LS92 •SN54/74LS93

LOGIC DIAGRAM

MS1MS2

MR1MR2

CP0

CP1

Q0 Q1 Q2 Q3

MR1

CP0

CP1

Q0 Q1 Q2 Q3MR2

LS90

MR1

CP0

CP1

Q0 Q1 Q2 Q3MR2

SDJ

CP

K

Q

QCD

SDR

CP

S

Q

QCD

SDJ

CP

K

Q

QCD

SDJ

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

14

1112

1

2

6

7

9

3

8

14

13

12

11

10

9

1

2

3

4

5

6

87

CP0

NC

Q0

Q3

GND

Q1

Q2

CP1

MR1

MR2

NC

VCC

MS1

MS2

CONNECTION DIAGRAM

DIP (TOP VIEW)

NC = NO INTERNAL CONNECTION

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual In-Line Package.

14

1

6

7

12 11 9 8

LOGIC DIAGRAM

LS92

14

13

12

11

10

9

1

2

3

4

5

6

87

CP0

NC

Q0

Q1

GND

Q2

Q3

CP1

NC

NC

NC

VCC

MR1

MR2

CONNECTION DIAGRAMDIP (TOP VIEW)


NOTE:




LOGIC DIAGRAM

LS93

VCC = PIN 5

GND = PIN 10

= PIN NUMBERS

VCC = PIN 5

GND = PIN 10

= PIN NUMBERS

VCC = PIN 5

GND = PIN 10

= PIN NUMBERS

14

1

2

3

12 9 8 11

14

13

12

11

10

9

1

2

3

4

5

6

87

CP0

NC

Q0

Q3

GND

Q1

Q2

CP1

MR1

MR2

NC

VCC

NC

NC

CONNECTION DIAGRAM

DIP (TOP VIEW)


NOTE:







SN54/74LS90 •SN54/74LS92 •SN54/74LS93

FUNCTIONAL DESCRIPTION

The LS90, LS92, and LS93 are 4-bit ripple type Decade,

Divide-By-Twelve, and Binary Counters respectively. Each

device consists of four master/slave flip-flops which are

internally connected to provide a divide-by-two section and a

divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight

(LS93) section. Each section has a separate clock input whichinitiates state changes of the counter on the HIGH-to-LOW

clock transition. State changes of the Q outputs do not occur

simultaneously because of internal ripple delays. Therefore,

decoded output signals are subject to decoding spikes and

should not be used for clocks or strobes. The Q0 output of

each device is designed and specified to drive the rated

fan-out plus the CP1 input of the device.

A gated AND asynchronous Master Reset (MR1 • MR2) is

provided on all counters which overrides and clocks and

resets (clears) all the flip-flops. A gated AND asynchronous

Master Set (MS1 • MS2) is provided on the LS90 which

overrides the clocks and the MR inputs and sets the outputs to

nine (HLLH).

Since the output from the divide-by-two section is notinternally connected to the succeeding stages, the devices

may be operated in various counting modes.

LS90

A. BCD Decade (8421) Counter — The CP1 input must be ex-

ternally connected to the Q0output. The CP0 input receives

the incoming count and a BCD count sequence is pro-

duced.

B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3output must be externally connected to the CP0 input. The

input count is then applied to the CP1 input and a divide-by-

ten square wave is obtained at output Q0.

C. Divide-By-Two and Divide-By-Five Counter — No external

interconnections are required. The first flip-flop is used as a

binary element for the divide-by-two function (CP0 as the

input and Q0 as the output). The CP1 input is used to obtain

binary divide-by-five operation at the Q3 output.

LS92

A. Modulo 12, Divide-By-Twelve Counter — The CP1 input

must be externally connected to the Q0 output. The CP0 in-

put receives the incoming count and Q3 produces a sym-

metrical divide-by-twelve square wave output.

B. Divide-By-Two and Divide-By-Six Counter —No external

interconnections are required. The first flip-flop is used as a

binary element for the divide-by-two function. The CP1 in-

put is used to obtain divide-by-three operation at the Q1and Q2 outputs and divide-by-six operation at the Q3 out-

put.

LS93

A. 4-Bit Ripple Counter — The output Q0 must be externally

connected to input CP1. The input count pulses are applied

to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are

performed at the Q0, Q1, Q2, and Q3 outputs as shown in

the truth table.

B. 3-Bit Ripple Counter— The input count pulses are applied

to input CP1. Simultaneous frequency divisions of 2, 4, and

8 are available at the Q1, Q2, and Q3 outputs. Independent

use of the first flip-flop is available if the reset function coin-

cides with reset of the 3-bit ripple-through counter.




SN54/74LS90 •SN54/74LS92 •SN54/74LS93

LS90

MODE SELECTION

RESET /SET INPUTS OUTPUTS

MR1 MR2 MS1 MS2 Q0 Q1 Q2 Q3

H

HX

L

X

L

X

H

HX

X

L

X

L

L

XH

L

X

X

L

L

LH

L

LL

L

LL

L

LH

Count

Count

Count

Count

X

LH

X

L

L

X

H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

LS92 AND LS93

MODE SELECTION

RESETINPUTS

OUTPUTS

MR1 MR2 Q0 Q1 Q2 Q3

HL

H

L

HH

L

L

L L L LCount

Count

Count



X = Don’t Care

LS90

BCD COUNT SEQUENCE

COUNTOUTPUT

Q0 Q1 Q2 Q3

0

1

2

3

4

5

6

7

8

9

L

H

L

H

L

H

L

H

L

H

L

L

H

H

L

L

H

H

L

L

L

L

L

L

H

H

H

H

L

L

L

L

L

L

L

L

L

L

H

H

NOTE: Output Q0 is connected to Input

CP1 for BCD count.

LS92

TRUTH TABLE

COUNTOUTPUT

Q0 Q1 Q2 Q3

0

1

2

3

4

5

6

7

8

9

10

11

L

H

L

H

L

H

L

H

L

H

L

H

L

L

H

H

L

L

L

L

H

H

L

L

L

L

L

L

H

H

L

L

L

L

H

H

L

L

L

L

L

L

H

H

H

H

H

H

NOTE: Output Q0 is connected to InputCP1.

LS93

TRUTH TABLE

COUNTOUTPUT

Q0 Q1 Q2 Q3

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

L

H

H

L

L

H

H

L

L

H

H

L

L

H

H

L

L

L

L

H

H

H

H

L

L

L

L

H

H

H

H

L

L

L

L

L

L

L

L

H

H

H

H

H

H

H

H

NOTE: Output Q0 is connected to Input

CP1.




SN54/74LS90 •SN54/74LS92 •SN54/74LS93



VCC Supply Voltage 54

74

4.5

4.75

5.0

5.0

5.5

5.25

V

TA Operating Ambient Temperature Range 54

74

–55

0

25

25

125

70

°C

IOH Output Current — High 54, 74 –0.4 mA

IOL Output Current — Low 54

74

4.0

8.0

mA


Limits



All Inputs

54 0.7 Guaranteed Input LOW Voltage for

IL

74 0.8

All Inputs


54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH

OH 74 2.7 3.5 V


54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

OL 74 0.35 0.5 V IOL = 8.0 mA

=

per Truth Table

20 µA VCC = MAX, VIN = 2.7 V

IH 0.1 mA VCC = MAX, VIN = 7.0 V

IIL

Input LOW Current

MS, MR

CP0CP1 (LS90, LS92)CP1 (LS93)

–0.4

–2.4

–3.2 –1.6



ICC Power Supply Current 15 mA VCC = MAX





SN54/74LS90 •SN54/74LS92 •SN54/74LS93

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF)

Limits

LS90 LS92 LS93

Symbol Parameter Min Typ Max Min Typ Max Min Typ Max Unit

fMAX CP0 Input Clock Frequency 32 32 32 MHz

fMAX CP1 Input Clock Frequency 16 16 16 MHz

tPLHtPHL

Propagation Delay,

CP0 Input to Q0 Output

10

12

16

18

10

12

16

18

10

12

16

18ns

tPLHtPHL

CP0 Input to Q3 Output32

34

48

50

32

34

48

50

46

46

70

70ns

tPLHtPHL


14

16

21

10

14

16

21

10

14

16

21ns

tPLHtPHL


23

32

35

10

14

16

21

21

23

32

35ns

tPLHtPHL


23

32

35

21

23

32

35

34

34

51

51ns

tPLH MS Input to Q0 and Q3 Outputs 20 30 ns

tPHL MS Input to Q1 and Q2 Outputs 26 40 ns

tPHL MR Input to Any Output 26 40 26 40 26 40 ns

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)

Limits

LS90 LS92 LS93

Symbol Parameter Min Max Min Max Min Max Unit

tW CP0 Pulse Width 15 15 15 ns

tW CP1 Pulse Width 30 30 30 ns

tW MS Pulse Width 15 ns

tW MR Pulse Width 15 15 15 ns

trec Recovery Time MR to CP 25 25 25 ns

RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize

and transfer HIGH data to the Q outputs

AC WAVEFORMS

Figure 1

Figure 2 Figure 3

*CP

Q

1.3 V

tPHLtW

1.3 V

1.3 V 1.3 V

1.3 V

tPLH

*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.

MR & MS

CP

Q

MS

Q0 • Q3(LS90)

1.3 V 1.3 V

1.3 V

1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

tPHL

tW

tPLH

trec tW

CP

trec




4-BIT SHIFT REGISTER

The SN54/74LS95B is a 4-Bit Shift Register with serial and parallel

synchronous operating modes. The serial shift right and parallel load are acti-vated by separate clock inputs which are selected by a mode control input.

The data is transferred from the serial or parallel D inputs to the Q outputs

synchronous with the HIGH to LOW transition of the appropriate clock input.

The LS95B is fabricated with the Schottky barrier diode process for high

speed and is completely compatible with all Motorola TTL families.

• Synchronous, Expandable Shift Right

• Synchronous Shift Left Capability

• Synchronous Parallel Load

• Separate Shift and Load Clock Inputs

• Input Clamp Diodes Limit High Speed Termination Effects

NOTE:

The Flatpak version has the

same pinouts (Connection

Diagram) as the Dual In-Line

Package.

CONNECTION DIAGRAM DIP (TOP VIEW)

V

C C

= P I N 1 4

G N D = P I N 7

1 4 1 3 1 2 1 1 1 0 9

1 2 3 4 5 6

8

7

V

C C

Q

0

Q

1

Q

2

Q

3

C P

1

C P

2

D

S

P

0

P

1

P

2

P

3

S G N D

PIN NAMES LOADING (Note a)

HIGH LOW

S Mode Control Input 0.5 U.L. 0.25 U.L.

DS Serial Data Input 0.5 U.L. 0.25 U.L.

P0 –P3 Parallel Data Inputs 0.5 U.L. 0.25 U.L.

CP1 Serial Clock (Act ive LOW Going Edge) Input 0.5 U.L. 0.25 U.L.

CP2 Parallel Clock (Active LOW Going Edge) Input 0.5 U.L. 0.25 U.L.

Q0 –Q3 Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L.

NOTES:

a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.

b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

Temperature Ranges.




74

4.5

4.75

5.0

5.0

5.5

5.25

V


74

–55

0

25

25

125

70

°C



74

4.0

8.0

mA

SN54/74LS95B

4-BIT SHIFT REGISTER

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 632-08

N SUFFIX

PLASTIC

CASE 646-06

14

1

14

1


SN54LSXXJ Ceramic

SN74LSXXN Plastic

SN74LSXXD SOIC

14

1

D SUFFIX

SOIC

CASE 751A-02




SN54/74LS95B

LOGIC DIAGRAM

Q

0

Q

1

Q

2

Q

3

S

D

S

C P

1

C P

2

P

0

P

2

P

3

R

S Q

P

1

R

S Q

R

S Q

R

S Q

V

C C

= P I N 1 4

G N D = P I N 7

= P I N N U M B E R S

6

1

2 3

8

4 5

9

1 1 1 2 1 0 1 3

FUNCTIONAL DESCRIPTION

The LS95B is a 4-Bit Shift Register with serial and parallel

synchronous operating modes. It has a Serial (DS) and four

Parallel (P0 –P3) Data inputs and four Parallel Data outputs

(Q0 –Q3). The serial or parallel mode of operation is controlled

by a Mode Control input (S) and two Clock Inputs (CP1) and

(CP2). The serial (right-shift) or parallel data transfers occur

synchronous with the HIGH to LOW transition of the selected

clock input.

When the Mode Control input (S) is HIGH, CP2 is enabled. A

HIGH to LOW transition on enabled CP2 transfers parallel

data from the P0 –P

3inputs to the Q

0 –Q

3outputs.

When the Mode Control input (S) is LOW, CP1 is enabled. A

HIGH to LOW transition on enabled CP1 transfers the data

from Serial input (DS) to Q0 and shifts the data in Q0 to Q1, Q1to Q2, and Q2 to Q3 respectively (right-shift). A left-shift is ac-

complished by externally connecting Q3 to P2, Q2 to P1, and

Q1 to P0, and operating the LS95B in the parallel mode (S =

HIGH).

For normal operation, S should only change states when

both Clock inputs are LOW. However, changing S from LOW

to HIGH while CP2 is HIGH, or changing S from HIGH to LOW

while CP1 is HIGH and CP2 is LOW will not cause any changes

on the register outputs.

MODE SELECT — TRUTH TABLE

INPUTS OUTPUTS

S CP1 CP2 DS Pn Q0 Q1 Q2 Q3

L X I X L q0 q1 q2L X h X H q0 q1 q2

Parallel Load H X X Pn P0 P1 P2 P3

L L X X No Change

L L X X No Change

H L X X No ChangeMode Change H L X X Undetermined

L H X X Undetermined

L H X X No Change

H H X X Undetermined

H H X X No Change



X = Don’t Care

I = LOW Voltage Level one set-up time prior to the HIGH to LOW clock transition.

h = HIGH Voltage Level one set-up time prior to the HIGH to LOW clock transition.

Pn = Lower case letters indicate the state of the referenced input (or output) one set-up t ime prior to the Pn

= HIGH to LOW clock transition.




SN54/74LS95B


Limits



All Inputs


IL 74 0.8

All Inputs



OH 74 2.7 3.5 V



OL 74 0.35 0.5 V IOL = 8.0 mA

=

per Truth Table

20 µA VCC = MAX, VIN = 2.7 V

IH 0.1 mA VCC = MAX, VIN = 7.0 V

IIL

Input HIGH Current –0.4 mA VCC

= MAX, VIN

= 0.4 V


ICC Power Supply Current 21 mA VCC = MAX


AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

Limits



tPLH

18 27 nsVCC = 5.0 V

CtPHL

21 32 ns

=

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)

Limits


tW CP Pulse Width 20 ns

ts Data Setup Time 20 ns

th Data Hold Time 20 ns VCC = 5.0 V

ts Mode Control Setup Time 20 ns

th Mode Control Hold Time 20 ns




SN54/74LS95B

DESCRIPTION OF TERMS

SETUP TIME(ts) —is defined as the minimum time required

for the correct logic level to be present at the logic input prior to

the clock transition from HIGH to LOW in order to be recog-

nized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time following

the clock transition from HIGH to LOW that the logic level must

be maintained at the input in order to ensure continued recog-

nition. A negative HOLD TIME indicates that the correct logic

level may be released prior to the clock transition from HIGH to

LOW and still be recognized.

AC WAVEFORMS

Figure 1

Figure 2

The shaded areas indicate when the input is permitted to change for predictable output performance.

1 . 3 V 1 . 3 V 1 . 3 V 1 . 3 V

1 . 3 V

t

h ( H )

t

s ( H )

t

s ( L )

t

h ( L )

t

W

l / f

m a x

t

P H L

t

P L H

*The Data Input is(DS for CP1) or (Pn for CP2).

D

C P

1

o r C P

2

Q

1 . 3 V 1 . 3 V

1 . 3 V

1 . 3 V 1 . 3 V

1 . 3 V

1 . 3 V 1 . 3 V

1 . 3 V 1 . 3 V

t

s ( L )

t

s ( H )

t

h ( L )

t

s ( L )

t

s ( H )

t

s ( L )

t

s ( H )

t

h ( H )

t

W

t

h ( L Ă O R Ă H )

S T A B L E

( H L O N L Y )

S

C P

1

C P

2

t

W

1 . 3 V 1 . 3 V

1 . 3 V

1 . 3 V

( L H O N L Y ) ( L H O N L Y )




M I N M I N M A X M A X

M I L L I M E T E R S I N C H E S

D I M

A

B

C

D

F

G

J

K

M

P

R

8 . 5 5

3 . 8 0

1 . 3 5

0 . 3 5

0 . 4 0

0 . 1 9

0 . 1 0

0 °

5 . 8 0

0 . 2 5

8 . 7 5

4 . 0 0

1 . 7 5

0 . 4 9

1 . 2 5

0 . 2 5

0 . 2 5

7 °

6 . 2 0

0 . 5 0

0 . 3 3 7

0 . 1 5 0

0 . 0 5 4

0 . 0 1 4

0 . 0 1 6

0 . 0 0 8

0 . 0 0 4

0 °

0 . 2 2 9

0 . 0 1 0

0 . 3 4 4

0 . 1 5 7

0 . 0 6 8

0 . 0 1 9

0 . 0 4 9

0 . 0 0 9

0 . 0 0 9

7 °

0 . 2 4 4

0 . 0 1 9

1 . 2 7 B S C 0 . 0 5 0 B S C

N O T E S :

1 . D I M E N S I O N S A " A N D B " A R E D A T U M S A N D

T " I S A D A T U M S U R F A C E .

2 . D I M E N S I O N I N G A N D T O L E R A N C I N G P E R A N S I

Y 1 4 . 5 M , 1 9 8 2 .

3 . C O N T R O L L I N G D I M E N S I O N : M I L L I M E T E R .

4 . D I M E N S I O N A A N D B D O N O T I N C L U D E M O L D

P R O T R U S I O N .

5 . M A X I M U M M O L D P R O T R U S I O N 0 . 1 5 ( 0 . 0 0 6 )

P E R S I D E .

6 . 7 5 1 A Ć 0 1 I S O B S O L E T E , N E W S T A N D A R D

7 5 1 A Ć 0 2 .

-A-

-B- P

G C

K

S E A T I N G

P L A N E

1 4 P L D M F J

7 P L

R X 45°

17

814

Case 751A-02 D Suffix

14-Pin Plastic

SO-14

B 0 . 2 5 ( 0 . 0 1 0 )

M M

T 0 . 2 5 ( 0 . 0 1 0 ) B A

M S S

Case 632-08 J Suffix

14-Pin Ceramic Dual In-Line



D I M

A

B

C

D

F

G

J

K

L

M

N

1 9 . 0 5

6 . 2 3

3 . 9 4

0 . 3 9

1 . 4 0

0 . 2 1

3 . 1 8

0 °

0 . 5 1

1 9 . 9 4

7 . 1 1

5 . 0 8

0 . 5 0

1 . 6 5

0 . 3 8

4 . 3 1

1 5 °

1 . 0 1

0 . 7 5 0

0 . 2 4 5

0 . 1 5 5

0 . 0 1 5

0 . 0 5 5

0 . 0 0 8

0 . 1 2 5

0 °

0 . 0 2 0

0 . 7 8 5

0 . 2 8 0

0 . 2 0 0

0 . 0 2 0

0 . 0 6 5

0 . 0 1 5

0 . 1 7 0

1 5 °

0 . 0 4 0

2 . 5 4 B S C

7 . 6 2 B S C

0 . 1 0 0 B S C

0 . 3 0 0 B S C

N O T E S :


Y 1 4 . 5 M , 1 9 8 2 .

2 . C O N T R O L L I N G D I M E N S I O N : I N C H .

3 . D I M E N S I O N L T O C E N T E R O F L E A D W H E N

F O R M E D P A R A L L E L .

4 . D I M F M A Y N A R R O W T O 0 . 7 6 ( 0 . 0 3 0 ) W H E R E

T H E L E A D E N T E R S T H E C E R A M I C B O D Y .

5 . 6 3 2 Ć 0 1 T H R U Ć 0 7 O B S O L E T E , N E W S T A N D A R D

6 3 2 Ć 0 8 .

14 8

1 7

-A-

-B-

-T-S E A T I N G

P L A N E

F G

D 1 4 P L

N

K

C L

J 1 4 P L

M

0 . 2 5 ( 0 . 0 1 0 ) T A

M

S

0 . 2 5 ( 0 . 0 1 0 ) T B

M

S

Case 646-06 N Suffix

14-Pin Plastic



D I M

1 8 . 1 6

6 . 1 0

3 . 6 9

0 . 3 8

1 . 0 2

1 . 3 2

0 . 2 0

2 . 9 2

1 9 . 5 6

6 . 6 0

4 . 6 9

0 . 5 3

1 . 7 8

2 . 4 1

0 . 3 8

3 . 4 3

0 °

0 . 3 9

0 . 7 1 5

0 . 2 4 0

0 . 1 4 5

0 . 0 1 5

0 . 0 4 0

0 . 0 5 2

0 . 0 0 8

0 . 1 1 5

0 . 7 7 0

0 . 2 6 0

0 . 1 8 5

0 . 0 2 1

0 . 0 7 0

0 . 0 9 5

0 . 0 1 5

0 . 1 3 5

1 0 °

1 . 0 1

2 . 5 4 B S C

7 . 6 2 B S C

0 . 1 0 0 B S C

0 . 3 0 0 B S C

0 °

0 . 0 1 5

1 0 °

0 . 0 3 9

A

B

C

D

F

G

H

J

K

L

M

N

N O T E S :

1 . L E A D S W I T H I N 0 . 1 3 m m ( 0 . 0 0 5 ) R A D I U S O F T R U E

P O S I T I O N A T S E A T I N G P L A N E A T M A X I M U M

M A T E R I A L C O N D I T I O N .

2 . D I M E N S I O N L " T O C E N T E R O F L E A D S W H E N


3 . D I M E N S I O N B " D O E S N O T I N C L U D E M O L D

F L A S H .

4 . R O U N D E D C O R N E R S O P T I O N A L .

5 . 6 4 6 Ć 0 5 O B S O L E T E , N E W S T A N D A R D 6 4 6 Ć 0 6 .

1 7

14 8

B

AN O T E 4

F

HG

DS E A T I N G

P L A N E

N

K

C

L

J

M




Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in differentapplications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola doesnot convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of

the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any suchunintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmlessagainst all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers:

USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.

EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.

JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan.

ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

◊




August 1986

Revised March 2000

D M7 4 L S

1 3 8 • D M7 4 L S 1 3 9 D e c o d er / D em ul t i pl ex er

DM74LS138 • DM74LS139

Decoder/Demultiplexer

General DescriptionThese Schottky-clamped circuits are designed to be used

in high-performance memory-decoding or data-routing

applications, requiring very short propagation delay times.

In high-performance memory systems these decoders canbe used to minimize the effects of system decoding. When

used with high-speed memories, the delay times of thesedecoders are usually less than the typical access time of

the memory. This means that the effective system delay

introduced by the decoder is negligible.

The DM74LS138 decodes one-of-eight lines, based upon

the conditions at the three binary select inputs and thethree enable inputs. Two active-low and one active-high

enable inputs reduce the need for external gates or invert-

ers when expanding. A 24-line decoder can be imple-

mented with no external inverters, and a 32-line decoderrequires only one inverter. An enable input can be used asa data input for demultiplexing applications.

The DM74LS139 comprises two separate two-line-to-four-

line decoders in a single package. The active-low enable

input can be used as a data line in demultiplexing applica-tions.

All of these decoders/demultiplexers feature fully buffered

inputs, presenting only one normalized load to its driving

circuit. All inputs are clamped with high-performanceSchottky diodes to suppress line-ringing and simplify sys-

tem design.

Featuress Designed specifically for high speed:

Memory decoders

Data transmission systems

s DM74LS138 3-to-8-line decoders incorporates 3 enable

inputs to simplify cascading and/or data reception

s DM74LS139 contains two fully independent 2-to-4-linedecoders/demultiplexers

s Schottky clamped for high performance

s Typical propagation delay (3 levels of logic)

DM74LS138 21 ns

DM74LS139 21 ns

s Typical power dissipation

DM74LS138 32 mW

DM74LS139 34 mW

Ordering Code:



DM74LS138M M16A 16-Lead Smal l Outline Integrated Circui t (SOIC), JEDEC MS-012, 0.150 Narrow

DM74LS138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE I I, 5.3mm Wide








D M 7 4 L S 1 3 8 • D M

7 4 L S 1 3 9

Connection Diagrams

DM74LS138 DM74LS139

Function Tables

DM74LS138 DM74LS139

H=

HIGH Level

L = LOW Level

X = Don’t Care

Note 1: G2 = G2A + G2B

Logic Diagrams

DM74LS138 DM74LS139

InputsOutputs

Enable Select

G1 G2 (Note 1) C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7

X H X X X H H H H H H H H

L X X X X H H H H H H H H

H L L L L L H H H H H H H

H L L L H H L H H H H H H

H L L H L H H L H H H H H

H L L H H H H H L H H H H

H L H L L H H H H L H H H

H L H L H H H H H H L H HH L H H L H H H H H H L H

H L H H H H H H H H H H L

InputsOutputs

Enable Select

G B A Y0 Y1 Y2 Y3

H X X H H H H

L L L L H H H

L L H H L H H

L H L H H L H

L H H H H H L




D M7 4 L S

1 3 8 • D M7 4 L S 1 3 9








DM74LS138 Recommended Operating Conditions

DM74LS138 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)



Note 5: ICC is measured with all outputs enabled and OPEN.

DM74LS138 Switching Characteristicsat VCC = 5V and TA = 25°C

Supply Voltage 7V

Input Voltage 7V











Max Units(Note 3)


VOH HIGH Level Output Voltage VCC = Min, IOH = Max, VIL = Max, VIH = Min 2.7 3.4 V

VOL LOW Level VCC = Min, IOL = Max, VIL = Max, VIH = Min 0.35 0.5V

Output Voltage IOL = 4 mA, VCC = Min 0.25 0.4





ICC Supply Current VCC = Max (Note 5) 6.3 10 mA

From (Input) Levels RL = 2 kΩ

Symbol Parameter To (Output) of Delay CL = 15 pF CL = 50 pF Units

Min Max Min Max

tPLH Propagation Delay TimeSelect to Output 2 18 27 ns


tPHL Propagation Delay TimeSelect to Output 2 27 40 ns






tPLH Propagation Delay TimeEnable to Output 2 18 27 ns

LOW-to-HIGH Level OutputtPHL Propagation Delay Time

Enable to Output 2 24 40 nsHIGH-to-LOW Level Output



tPHL Propagation Delay TimeEnable to Output 3 28 40 ns





D M 7 4 L S 1 3 8 • D M

7 4 L S 1 3 9















Max Units(Note 6)






IOL = 4 mA, VCC = Min 0.25 0.4








Min Max Min Max

tPLH Propagation Delay TimeSelect to Output 18 27 ns


tPHL Propagation Delay TimeSelect to Output 27 40 ns


tPLH Propagation Delay TimeEnable to Output 18 27 ns


tPHL Propagation Delay TimeEnable to Output 24 40 ns





D M7 4 L S

1 3 8 • D M7 4 L S 1 3 9



Package Number M16A




D M 7 4 L S 1 3 8 • D M

7 4 L S 1 3 9


16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D




D M7 4 L S





LIFE SUPPORT POLICY















August 1986

Revised March 2000

D M7 4 L S


DM74LS138 • DM74LS139

Decoder/Demultiplexer

General DescriptionThese Schottky-clamped circuits are designed to be used

in high-performance memory-decoding or data-routing

applications, requiring very short propagation delay times.

In high-performance memory systems these decoders canbe used to minimize the effects of system decoding. When

used with high-speed memories, the delay times of thesedecoders are usually less than the typical access time of

the memory. This means that the effective system delay

introduced by the decoder is negligible.

The DM74LS138 decodes one-of-eight lines, based upon

the conditions at the three binary select inputs and thethree enable inputs. Two active-low and one active-high

enable inputs reduce the need for external gates or invert-

ers when expanding. A 24-line decoder can be imple-

mented with no external inverters, and a 32-line decoderrequires only one inverter. An enable input can be used asa data input for demultiplexing applications.

The DM74LS139 comprises two separate two-line-to-four-

line decoders in a single package. The active-low enable

input can be used as a data line in demultiplexing applica-tions.

All of these decoders/demultiplexers feature fully buffered

inputs, presenting only one normalized load to its driving

circuit. All inputs are clamped with high-performanceSchottky diodes to suppress line-ringing and simplify sys-

tem design.

Featuress Designed specifically for high speed:

Memory decoders

Data transmission systems

s DM74LS138 3-to-8-line decoders incorporates 3 enable

inputs to simplify cascading and/or data reception

s DM74LS139 contains two fully independent 2-to-4-linedecoders/demultiplexers

s Schottky clamped for high performance

s Typical propagation delay (3 levels of logic)

DM74LS138 21 ns

DM74LS139 21 ns

s Typical power dissipation

DM74LS138 32 mW

DM74LS139 34 mW

Ordering Code:












D M 7 4 L S 1 3 8 • D M

7 4 L S 1 3 9

Connection Diagrams

DM74LS138 DM74LS139

Function Tables

DM74LS138 DM74LS139

H=

HIGH Level

L = LOW Level

X = Don’t Care

Note 1: G2 = G2A + G2B

Logic Diagrams

DM74LS138 DM74LS139

InputsOutputs

Enable Select

G1 G2 (Note 1) C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7

X H X X X H H H H H H H H

L X X X X H H H H H H H H

H L L L L L H H H H H H H

H L L L H H L H H H H H H

H L L H L H H L H H H H H

H L L H H H H H L H H H H

H L H L L H H H H L H H H

H L H L H H H H H H L H HH L H H L H H H H H H L H

H L H H H H H H H H H H L

InputsOutputs

Enable Select

G B A Y0 Y1 Y2 Y3

H X X H H H H

L L L L H H H

L L H H L H H

L H L H H L H

L H H H H H L




D M7 4 L S

1 3 8 • D M7 4 L S 1 3 9














Supply Voltage 7V

Input Voltage 7V











Max Units(Note 3)


VOH HIGH Level Output Voltage VCC = Min, IOH = Max, VIL = Max, VIH = Min 2.7 3.4 V

VOL LOW Level VCC = Min, IOL = Max, VIL = Max, VIH = Min 0.35 0.5V

Output Voltage IOL = 4 mA, VCC = Min 0.25 0.4






From (Input) Levels RL = 2 kΩ

Symbol Parameter To (Output) of Delay CL = 15 pF CL = 50 pF Units

Min Max Min Max










LOW-to-HIGH Level OutputtPHL Propagation Delay Time

Enable to Output 2 24 40 nsHIGH-to-LOW Level Output



tPHL Propagation Delay TimeEnable to Output 3 28 40 ns





D M 7 4 L S 1 3 8 • D M

7 4 L S 1 3 9















Max Units(Note 6)






IOL = 4 mA, VCC = Min 0.25 0.4








Min Max Min Max

tPLH Propagation Delay TimeSelect to Output 18 27 ns


tPHL Propagation Delay TimeSelect to Output 27 40 ns


tPLH Propagation Delay TimeEnable to Output 18 27 ns


tPHL Propagation Delay TimeEnable to Output 24 40 ns





D M7 4 L S

1 3 8 • D M7 4 L S 1 3 9



Package Number M16A




D M 7 4 L S 1 3 8 • D M

7 4 L S 1 3 9



Package Number M16D




D M7 4 L S





LIFE SUPPORT POLICY















10-LINE-TO-4-LINEAND 8-LINE-TO-3-LINEPRIORITY ENCODERS

The SN54/74LS147 and the SN54/74LS148 are Priority Encoders. Theyprovide priority decoding of the inputs to ensure that only the highest order

data line is encoded. Both devices have data inputs and outputs which are

active at the low logic level.

The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied

decimal zero condition does not require an input condition because zero is

encoded when all nine data lines are at a high logic level.

The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By

providing cascading circuitry (Enable Input EI and Enable Output EO) octal

expansion is allowed without needing external circuitry.

The SN54/74LS748 is a proprietary Motorola part incorporating a built-in

deglitcher network which minimizes glitches on the GS output. The glitch

occurs on the negative going transition of the EI input when data inputs 0– 7

are at logical ones.

The only dc parameter differences between the LS148 and the LS748 arethat (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on

the LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have a

fan-in of 3 on the LS748 versus a fan-in of 2 on the LS148.

The only ac difference is that tPHL from EI to EO is changed from 40 to

45 ns.

SN54/74LS147

(TOP VIEW)

SN54/74LS148

SN54/74LS748

(TOP VIEW)

4 5 6 7 8 C B G N D

D 3 2 1 9 A V

C C

N C

1 4 1 3 1 2 1 1 1 0 9

1 2 3 4 5 6

7

1 6 1 5

8

D 3 2 1 9

A 4

5 6 7 8 C B

O U T P U T I N P U T S O U T P U T

I N P U T S O U T P U T S

4 5 6 7 E 1 A 2 A 1 G N D

V

C C

E O G S 3 2 1 0 A 0

1 4 1 3 1 2 1 1 1 0 9

1 2 3 4 5 6 7

1 6 1 5

8

E O G S 3 2 1 0

A 0 4

5 6 7 E I A 2 A 1

O U T P U T S I N P U T S O U T P U T

I N P U T S O U T P U T S

SN54/74LS147SN54/74LS148SN54/74LS748

10-LINE-TO-4-LINEAND 8-LINE-TO-3-LINEPRIORITY ENCODERS

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1


SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

16

1

D SUFFIX

SOIC

CASE 751B-03




SN54/74LS147 •SN54/74LS148 •SN54/74LS748

SN54/74LS147

FUNCTION TABLE

INPUTS OUTPUTS

1 2 3 4 5 6 7 8 9 D C B A

H H H H H H H H H H H H HX X X X X X X X L L H H L

X X X X X X X L H L H H H

X X X X X X L H H H L L L

X X X X X L H H H H L L H

X X X X L H H H H H L H L

X X X L H H H H H H L H H

X X L H H H H H H H H L L

X L H H H H H H H H H L H

L H H H H H H H H H H H L

SN54/74LS148

SN54/74LS748

FUNCTION TABLE

INPUTS OUTPUTS

EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO

H X X X X X X X X H H H H HL H H H H H H H H H H H H L

L X X X X X X X L L L L L H

L X X X X X X L H L L H L H

L X X X X X L H H L H L L H

L X X X X L H H H L H H L H

L X X X L H H H H H L L L H

L X X L H H H H H H L H L H

L X L H H H H H H H H L L H

L L H H H H H H H H H H L H

H = HIGH Logic Level, L = LOW Logic Level, X = Irrelevant

FUNCTIONAL BLOCK DIAGRAMS

SN54/74LS147 SN54/74LS148

1

2

3

4

5

6

7

8

9

( 1 1 )

( 1 2 )

( 1 3 )

( 1 )

( 2 )

( 3 )

( 4 )

( 5 )

( 1 0 )

( 9 )

( 7 )

( 6 )

( 1 4 )

A

B

C

D

0

1

2

3

4

5

6

7

E I

( 1 0 )

( 1 1 )

( 1 2 )

( 1 3 )

( 1 )

( 2 )

( 3 )

( 4 )

( 5 )

( 1 5 )

E O

( 1 4 )

G S

( 8 )

A 0

( 7 )

A 1

( 6 )

A 2




SN54/74LS147 •SN54/74LS148 •SN54/74LS748

FUNCTIONAL BLOCK DIAGRAMS (continued)

SN54/74LS748

G 3 1

G 2

G 3

G 4

G 5

G 6

G 7

G 8

G 1

G 9

G 1 0

G 1 1

G 1 2

G 1 3

0

1

2

3

4

5

6

7

E I

( 1 0 )

( 1 1 )

( 1 2 )

( 1 3 )

( 1 )

( 2 )

( 3 )

( 4 )

( 5 )

( 1 5 )

E O

( 1 4 )

G S

( 9 )

A 0

( 7 )

A 1

( 6 )

A 2

G 2 9

G 1 8

G 2 3

G 2 8




SN54/74LS147 •SN54/74LS148 •SN54/74LS748




74

4.5

4.75

5.0

5.0

5.5

5.25

V


74

–55

0

25

25

125

70

°C



74

4.0

8.0

mA


Limits



All Inputs


IL npu o age74 0.8

All Inputs



OH 74 2.7 3.5 V



OL 74 0.35 0.5 V IOL = 8.0 mA

=

per Truth Table

IIH

Input HIGH Current

All Others

Input 0 (LS748)

Inputs 1–7 (LS148)


20

40

40

60

µA VCC = MAX, VIN = 2.7 V

All Others

Input 0 (LS748)



0.1

0.2

0.2

0.3


IIL

Input LOW Current

All Others

Input 0 (LS748)



–0.4

–0.8

–0.8

–1.2



ICCH Power Supply Current Output HIGH 17 mA VCC = MAX, All Inputs = 4.5 V

ICCL Output LOW 20 mAVCC = MAX, Inputs 7 & E1 = GND

All Other Inputs = 4.5 V





SN54/74LS147 •SN54/74LS148 •SN54/74LS748

AC CHARACTERISTICS (VCC = 5.0 V, TA = 25°C)

SN54/74LS147

From To Limits

Symbol (Input) (Output) Waveform Min Typ Max Unit Test Conditions

tPLH In-phase 12 18

tPHLoutput 12 18 CL = 15 pF,

tPLH Out-of-phase 21 33

RL = 2.0 kΩ

tPHLny ny

output 15 23ns

SN54/74LS148

SN54/74LS748

From To Limits

Symbol (Input) (Output) Waveform Min Typ Max Unit Test Conditions

tPLH

In-phase 14 18

tPHL, ,

output 15 25

tPLH

Out-of-phase 20 36

tPHL, ,

output 16 29

tPLH

Out-of-phase 7.0 18

tPHLru

output 25 40ns

tPLH

In-phase 35 55

CL = 15 pF,

R = 2.0 kΩ

tPHL

output 9.0 21

.

tPLH

In-phase 16 25

tPHL, ,

output 12 25

tPLH In-phase 12 17

tPHLoutput 14 36

tPLH 12 21

tPHL EI EO-

output 28

30

40

45

ns (LS148)

(LS748)






D I M

A

B

C

D

F

G

J

K

M

P

R

9 . 8 0

3 . 8 0

1 . 3 5

0 . 3 5

0 . 4 0

0 . 1 9

0 . 1 0

0 °

5 . 8 0

0 . 2 5

1 0 . 0 0

4 . 0 0

1 . 7 5

0 . 4 9

1 . 2 5

0 . 2 5

0 . 2 5

7 °

6 . 2 0

0 . 5 0

0 . 3 8 6

0 . 1 5 0

0 . 0 5 4

0 . 0 1 4

0 . 0 1 6

0 . 0 0 8

0 . 0 0 4

0 °

0 . 2 2 9

0 . 0 1 0

0 . 3 9 3

0 . 1 5 7

0 . 0 6 8

0 . 0 1 9

0 . 0 4 9

0 . 0 0 9

0 . 0 0 9

7 °

0 . 2 4 4

0 . 0 1 9

1 . 2 7 B S C 0 . 0 5 0 B S C

N O T E S :


Y 1 4 . 5 M , 1 9 8 2 .

2 . C O N T R O L L I N G D I M E N S I O N : M I L L I M E T E R .

3 . D I M E N S I O N A A N D B D O N O T I N C L U D E M O L D

P R O T R U S I O N .

4 . M A X I M U M M O L D P R O T R U S I O N 0 . 1 5 ( 0 . 0 0 6 )

P E R S I D E .

5 . 7 5 1 B Ć 0 1 I S O B S O L E T E , N E W S T A N D A R D

7 5 1 B Ć 0 3 .

18

916

-A-

-B- P

1 6 P L D

-T-

K

CG

M

R X 45°

F J

8 P L

S E A T I N G

P L A N E

Case 751B-03 D Suffix

16-Pin Plastic

SO-16

B 0 . 2 5 ( 0 . 0 1 0 )

M M

T 0 . 2 5 ( 0 . 0 1 0 ) B A

M S S

Case 648-08 N Suffix

16-Pin Plastic



D I M

A

B

C

D

F

G

H

J

K

L

M

S

1 8 . 8 0

6 . 3 5

3 . 6 9

0 . 3 9

1 . 0 2

0 . 2 1

2 . 8 0

7 . 5 0

0 °

0 . 5 1

1 9 . 5 5

6 . 8 5

4 . 4 4

0 . 5 3

1 . 7 7

0 . 3 8

3 . 3 0

7 . 7 4

1 0 °

1 . 0 1

0 . 7 4 0

0 . 2 5 0

0 . 1 4 5

0 . 0 1 5

0 . 0 4 0

0 . 0 0 8

0 . 1 1 0

0 . 2 9 5

0 °

0 . 0 2 0

0 . 7 7 0

0 . 2 7 0

0 . 1 7 5

0 . 0 2 1

0 . 0 7 0

0 . 0 1 5

0 . 1 3 0

0 . 3 0 5

1 0 °

0 . 0 4 0

N O T E S :


Y 1 4 . 5 M , 1 9 8 2 .


3 . D I M E N S I O N L " T O C E N T E R O F L E A D S W H E N


4 . D I M E N S I O N B " D O E S N O T I N C L U D E M O L D

F L A S H .

5 . R O U N D E D C O R N E R S O P T I O N A L .


6 4 8 Ć 0 8 .

2 . 5 4 B S C

1 . 2 7 B S C

0 . 1 0 0 B S C

0 . 0 5 0 B S C

-A-

B

1 8

916

F

H

GD 1 6 P L

S

C

-T- S E A T I N G

P L A N E

K J M

L

T A 0 . 2 5 ( 0 . 0 1 0 )

M M

Case 620-09 J Suffix

16-Pin Ceramic Dual In-Line



D I M

1 9 . 0 5

6 . 1 0

Ċ

0 . 3 9

1 . 4 0

0 . 2 3

Ċ

0 °

0 . 3 9

1 9 . 5 5

7 . 3 6

4 . 1 9

0 . 5 3

1 . 7 7

0 . 2 7

5 . 0 8

1 5 °

0 . 8 8

0 . 7 5 0

0 . 2 4 0

Ċ

0 . 0 1 5

0 . 0 5 5

0 . 0 0 9

Ċ

0 °

0 . 0 1 5

0 . 7 7 0

0 . 2 9 0

0 . 1 6 5

0 . 0 2 1

0 . 0 7 0

0 . 0 1 1

0 . 2 0 0

1 5 °

0 . 0 3 5

1 . 2 7 B S C

2 . 5 4 B S C

7 . 6 2 B S C

0 . 0 5 0 B S C

0 . 1 0 0 B S C

0 . 3 0 0 B S C

A

B

C

D

E

F

G

J

K

L

M

N

N O T E S :


Y 1 4 . 5 M , 1 9 8 2 .


3 . D I M E N S I O N L T O C E N T E R O F L E A D W H E N


4 . D I M F M A Y N A R R O W T O 0 . 7 6 ( 0 . 0 3 0 ) W H E R E

T H E L E A D E N T E R S T H E C E R A M I C B O D Y .


6 2 0 Ć 0 9 .

-B-

-A-

1 6 P L

-T-

C

D

E

F G J

K

MN

S E A T I N G

P L A N E

1 6 P L

L

16 9

1 8

0 . 2 5 ( 0 . 0 1 0 ) T A

M S

0 . 2 5 ( 0 . 0 1 0 ) T B

M

S




Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in differentapplications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola doesnot convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of

the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any suchunintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmlessagainst all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers:

USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.

EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.

JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan.

ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

◊




August 1986

Revised March 2000

D M7 4 L S

1 5 1 1 - of - 8 L i n eD a t a S el e c t or

/ M ul t i pl ex er

DM74LS151

1-of-8 Line Data Selector/Multiplexer

General DescriptionThis data selector/multiplexer contains full on-chip decod-

ing to select the desired data source. The DM74LS151

selects one-of-eight data sources. The DM74LS151 has a

strobe input which must be at a low logic level to enablethese devices. A high level at the strobe forces the W out-

put HIGH, and the Y output LOW.

The DM74LS151 features complementary W and Y out-

puts.

Featuress Select one-of-eight data lines

s Performs parallel-to-serial conversion

s Permits multiplexing from N lines to one line

s Also for use as Boolean function generator

s Typical average propagation delay time data input to

W output 12.5 ns

s Typical power dissipation 30 mW

Ordering Code:


Connection Diagram Truth Table

H = HIGH Level

L = LOW Level

X = Don't Care

D0, D1...D7 = the level of the respective D input





Inputs Outputs

Select StrobeY W

C B A S

X X X H L H

L L L L D0 D0

L L H L D1 D1L H L L D2 D2

L H H L D3 D3

H L L L D4 D4

H L H L D5 D5

H H L L D6 D6

H H H L D7 D7




D M

7 4 L S 1 5 1

Logic Diagrams

See Address Buffers

Address Buffers




D M7 4 L S

1 5 1












Note 4: ICC is measured with all outputs OPEN, strobe and data select inputs at 4.5V, and all other inputs OPEN.

Supply Voltage 7V

Input Voltage 7V











Max Units(Note 2)






IOL = 4 mA, VCC = Min 0.25 0.4









D M

7 4 L S 1 5 1



Symbol ParameterTo (output)

CL = 15 pF C

L = 50 pF Units

Min Max Min Max

tPLH Propagation Delay Time Select43 46 ns

LOW-to-HIGH Level Output (4 Levels) to Y

tPHL Propagation Delay Time Select30 36 ns

HIGH-to-LOW Level Output (4 Levels) to Y

tPLH Propagation Delay Time Select23 25 ns

LOW-to-HIGH Level Output (3 Levels) to W

tPHL Propagation Delay Time Select32 40 ns

HIGH-to-LOW Level Output (3 Levels) to W

tPLH Propagation Delay Time Strobe42 44 ns

LOW-to-HIGH Level Output to Y

tPHL Propagation Delay Time Strobe32 40 ns

HIGH-to-LOW Level Output to Y

tPLH Propagation Delay Time Strobe24 27 ns

LOW-to-HIGH Level Output to W

tPHL Propagation Delay Time Strobe30 36 ns

HIGH-to-LOW Level Output to W

tPLH Propagation Delay Time D0 thru D732 35 ns

LOW-to-HIGH Level Output to Y

tPHL Propagation Delay Time D0 thru D726 33 ns

HIGH-to-LOW Level Output to Y

tPLH Propagation Delay Time D0 thru D721 25 ns

LOW-to-HIGH Level Output to W

tPHL Propagation Delay Time D0 thru D720 27 ns

HIGH-to-LOW Level Output to W




D M7 4 L S

1 5 1



Package Number M16A




D M

7 4 L S 1 5 1



Package Number M16D




D M7 4 L S

1 5 1 1 - of - 8 L i n eD a t a S el e c t or

/ M ul t i pl ex er




LIFE SUPPORT POLICY















August 1986

Revised March 2000

D M7 4 L S

1 5 3 D u al 1 - of - 4 L i n eD a t a S el

e c t or s / M ul t i pl ex er s

DM74LS153

Dual 1-of-4 Line Data Selectors/Multiplexers

General DescriptionEach of these data selectors/multiplexers contains invert-

ers and drivers to supply fully complementary, on-chip,

binary decoding data selection to the AND-OR-invert

gates. Separate strobe inputs are provided for each of thetwo four-line sections.

Featuress Permits multiplexing from N lines to 1 line

s Performs at parallel-to-serial conversion

s Strobe (enable) line provided for cascading

(N lines to n lines)

s High fan-out, low impedance, totem pole outputs

s Typical average propagation delay times

From data 14 ns

From strobe 19 ns

From select 22 ns


Ordering Code:



Select inputs A and B are common to both sections.

H = HIGH Level

L = LOW Level

X = Don't Care




SelectData Inputs Strobe Output

Inputs

B A C0 C1 C2 C3 G Y

X X X X X X H LL L L X X X L L

L L H X X X L H

L H X L X X L L

L H X H X X L H

H L X X L X L L

H L X X H X L H

H H X X X L L L

H H X X X H L H




D M

7 4 L S 1 5 3

Logic Diagram




D M7 4 L S

1 5 3










Note 2: All typicals are at VCC = 5V, TA = 25° C.


Note 4: ICC is measured with all outputs OPEN and all other inputs GROUNDED.


Supply Voltage 7V

Input Voltage 7V


Storage Temperature Range −65°C to +150° C









Max Units(Note 2)






IOL = 4 mA, VCC = Min 0.25 0.4







Symbol Parameter to (Output) CL = 15 pF CL = 50 pF Units

Min Max Min Max

tPLH Propagation Delay TimeData to Y 15 20 ns


tPHL Propagation Delay TimeData to Y 26 35 ns


tPLH Propagation Delay TimeSelect to Y 29 35 ns


tPHL Propagation Delay Time

Select to Y 38 45 nsHIGH-to-LOW Level Output

tPLH Propagation Delay TimeStrobe to Y 24 30 ns


tPHL Propagation Delay TimeStrobe to Y 32 40 ns





D M

7 4 L S 1 5 3



Package Number M16A




D M7 4 L S

1 5 3 D u al 1 - of - 4 L i n eD a t a S el

e c t or s / M ul t i pl ex er s



Package Number N16E


LIFE SUPPORT POLICY















August 1986

Revised March 2000

D M7 4 L S

1 5 4 4 - L i n e t o1 6 - L i n eD e c o d e

r / D em ul t i pl ex er

DM74LS154

4-Line to 16-Line Decoder/Demultiplexer

General DescriptionEach of these 4-line-to-16-line decoders utilizes TTL cir-

cuitry to decode four binary-coded inputs into one of six-

teen mutually exclusive outputs when both the strobe

inputs, G1 and G2, are LOW. The demultiplexing functionis performed by using the 4 input lines to address the out-

put line, passing data from one of the strobe inputs with theother strobe input LOW. When either strobe input is HIGH,

all outputs are HIGH. These demultiplexers are ideally

suited for implementing high-performance memory decod-ers. All inputs are buffered and input clamping diodes are

provided to minimize transmission-line effects and therebysimplify system design.

Featuress Decodes 4 binary-coded inputs into one of 16 mutually

exclusive outputs

s Performs the demultiplexing function by distributing data

from one input line to any one of 16 outputs

s Input clamping diodes simplify system design

s High fan-out, low-impedance, totem-pole outputs

s Typical propagation delay

3 levels of logic 23 ns

Strobe 19 ns


Ordering Code:


Connection Diagram Logic Diagram


DM74LS154WM M24B 24-Lead Smal l Outline Integrated Circui t (SOIC), JEDEC MS-013, 0.300 Wide





D M

7 4 L S 1 5 4

Function Table

H = HIGH Level

L = Low Level

X = Don’t Care

Inputs Outputs

G1 G2 D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

L L L L L L L H H H H H H H H H H H H H H H

L L L L L H H L H H H H H H H H H H H H H H

L L L L H L H H L H H H H H H H H H H H H H

L L L L H H H H H L H H H H H H H H H H H H

L L L H L L H H H H L H H H H H H H H H H H

L L L H L H H H H H H L H H H H H H H H H H

L L L H H L H H H H H H L H H H H H H H H H

L L L H H H H H H H H H H L H H H H H H H H

L L H L L L H H H H H H H H L H H H H H H H

L L H L L H H H H H H H H H H L H H H H H H

L L H L H L H H H H H H H H H H L H H H H H

L L H L H H H H H H H H H H H H H L H H H H

L L H H L L H H H H H H H H H H H H L H H H

L L H H L H H H H H H H H H H H H H H L H H

L L H H H L H H H H H H H H H H H H H H L H

L L H H H H H H H H H H H H H H H H H H H L

L H X X X X H H H H H H H H H H H H H H H H

H L X X X X H H H H H H H H H H H H H H H H

H H X X X X H H H H H H H H H H H H H H H H




D M7 4 L S

1 5 4












Note 4: ICC is measured with all outputs OPEN and all inputs GROUNDED.


Supply Voltage 7V

Input Voltage 7V











Max Units(Note 2)




VOL LOW Level VCC = Min, IOL = Max 0.25 0.4

Output Voltage VIL = Max, VIH = Min 0.35 0.5 V

IOL = 4 mA, VCC = Min 0.25 0.4








Min Max Min Max

tPLH Propagation Delay TimeData to Output 30 35 ns


tPHL Propagation Delay TimeData to Output 30 35 ns


tPLH Propagation Delay TimeStrobe to Output 20 25 ns


tPHL Propagation Delay Time

Strobe to Output 25 35 nsHIGH-to-LOW Level Output




D M

7 4 L S 1 5 4


24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B




D M7 4 L S

1 5 4 4 - L i n e t o1 6 - L i n eD e c o d e

r / D em ul t i pl ex er



Package Number N24A


LIFE SUPPORT POLICY















March 1989

Revised March 2000

D M7 4 L S

2 6 6 Q u a d 2 - I n p u t E x cl u si v e- N

OR

G a t e

DM74LS266

Quad 2-Input Exclusive-NOR Gate

with Open-Collector Outputs


performs the logic exclusive-NOR function. Outputs areopen collector.

Ordering Code:


Connection Diagram Truth Table






Inputs Outputs

A B Y

L L H

L H L

H L L

H H H




D M

7 4 L S 2 6 6




operated at these limits. The parametric values defined in the “Electrical

Characteristics” table are not guaranteed at the absolute maximum ratings.







Switching CharacteristicsVCC = 5V, TA = 25°C

Supply Voltage 7V

Input Voltage 7V







VOH HIGH Level Output Voltage 5.5 V




Max Units(Note 2)


ICEX HIGH Level VCC = Min, VO = 5.5V,100 µA

Output Current VIL = Max

VOL LOW Level VCC = Min, IOL = Max,0.5


IOL = 4 mA, VCC = Min 0.4





ICC Supply Current VCC = Max 13 mA

RL = 2 kΩ

Symbol Parameter CL = 15 pF Units

Min Max

tPLH Propagation Delay Time23 ns


tPHL Propagation Delay Time23 ns





D M7 4 L S

2 6 6



Package Number M14A




D M 7 4 L S

2 6 6 Q u a d 2 - I n p u t E x c l u s i v e - N

O R

G a t e




LIFE SUPPORT POLICY















April 1986

Revised March 2000

D M7 4 L S

3 7 3 • D M7 4 L S 3 7 4 3 - S T A T E O c t al D - T y p eT r an s p ar en t L a t ch

e s an d E d g e- T r i g g er e d F l i p- F

l o p s

DM74LS373 • DM74LS374

3-STATE Octal D-Type Transparent Latchesand Edge-Triggered Flip-Flops

General DescriptionThese 8-bit registers feature totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-tively low-impedance loads. The high-impedance state and

increased high-logic level drive provide these registers with

the capability of being connected directly to and driving the

bus lines in a bus-organized system without need for inter-

face or pull-up components. They are particularly attractivefor implementing buffer registers, I/O ports, bidirectionalbus drivers, and working registers.

The eight latches of the DM74LS373 are transparent D-

type latches meaning that while the enable (G) is HIGH the

Q outputs will follow the data (D) inputs. When the enableis taken LOW the output will be latched at the level of thedata that was set up.

The eight flip-flops of the DM74LS374 are edge-triggered

D-type flip flops. On the positive transition of the clock, theQ outputs will be set to the logic states that were set up at

the D inputs.

A buffered output control input can be used to place theeight outputs in either a normal logic state (HIGH or LOWlogic levels) or a high-impedance state. In the high-imped-

ance state the outputs neither load nor drive the bus lines

significantly.

The output control does not affect the internal operation ofthe latches or flip-flops. That is, the old data can beretained or new data can be entered even while the outputs

are OFF.

Featuress Choice of 8 latches or 8 D-type flip-flops in a single

package

s 3-STATE bus-driving outputs

s Full parallel-access for loading

s Buffered control inputs

s P-N-P inputs reduce D-C loading on data lines

Ordering Code:








IDM29901NC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide




D M 7 4 L S 3 7 3 • D M

7 4 L S 3 7 4

Connection Diagrams

DM74LS373 DM74LS374

Function Tables

DM74LS373 DM74LS374

H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don’t Care Z = High Impedance State

↑ = Transition from LOW-to-HIGH level Q0 = The level of the output before steady-state input conditions were established.

Logic Diagrams

DM74LS373

Transparent Latches

DM74LS374

Positive-Edge-Triggered Flip-Flops

Output EnableD Output

Control G

L H H HL H L L

L L X Q0

H X X Z

OutputClock D Output

Control

L ↑ H HL ↑ L L

L L X Q0

H X X Z




D M7 4 L S

3 7 3 • D M7 4 L S 3 7 4









Note 2: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.





Supply Voltage 7V

Input Voltage 7V









tW Pulse Width Enable HIGH 15ns

(Note 3) Enable LOW 15

tSU Data Setup Time (Note 2) (Note 3) 5↓ nstH Data Hold Time (Note 2) (Note 3) 20↓ ns



Max Units(Note 4)




VOL LOW Level VCC = Min, IOL = Max






IOZH Off -State Output Current with VCC = Max, VO = 2.7V20 µA

HIGH Level Output Voltage Applied VIH = Min, VIL = Max

IOZL Off -State Output Current with VCC = Max, VO = 0.4V−20 µA

LOW Level Output Voltage Applied VIH = Min, VIL = Max


ICC Supply Current VCC = Max, OC = 4.5V,24 40 mA

Dn, Enable = GND




D M 7 4 L S 3 7 3 • D M

7 4 L S 3 7 4


Note 6: CL = 5 pF.




RL = 667Ω

Symbol Parameter From (Input)C

L = 45 pF C

L = 150 pF

UnitsTo (Output) Min Max Min Max

tPLH Propagation Delay TimeData to Q 18 26 ns


tPHL Propagation Delay TimeData to Q 18 27 ns


tPLH Propagation Delay TimeEnable to Q 30 38 ns


tPHL Propagation Delay TimeEnable to Q 30 36 ns


tPZH Output Enable TimeOutput Control to Any Q 28 36 ns

to HIGH Level Output

tPZL Output Enable TimeOutput Control to Any Q 36 50 ns

to LOW Level Output

tPHZ Output Disable TimeOutput Control to Any Q 20 ns

from HIGH Level Output (Note 6)

tPLZ Output Disable TimeOutput Control to Any Q 25 ns

from LOW Level Output (Note 6)







tW Pulse Width Clock HIGH 15ns

(Note 8) Clock LOW 15

tSU

Data Setup Time (Note 7) (Note 8) 20↑ ns

tH Data Hold Time (Note 7) (Note 8) 1↑ ns





D M7 4 L S

3 7 3 • D M7 4 L S 3 7 4





Note 11: CL = 5 pF.


Max Units(Note 9)





VOutput Voltage VIL = Max, VIH = Min

IOL = 12 mA, VCC = Min 0.25 0.4




IOZH Off-State Output Current with VCC = Max, VO = 2.7V20 µA


IOZL Off-State Output Current with VCC = Max, VO = 0.4V−20 µA



ICC Supply Current VCC = Max, Dn = GND, OC = 4.5V 27 45 mA

RL = 667Ω


Min Max Min Max






tPZH Output Enable Time28 44 ns


tPZL Output Enable Time 28 44 nsto LOW Level Output

tPHZ Output Disable Time20 ns


tPLZ Output Disable Time25 ns





D M 7 4 L S 3 7 3 • D M

7 4 L S 3 7 4


20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 WidePackage Number M20B




D M7 4 L S

3 7 3 • D M7 4 L S 3 7 4



Package Number M20D




D M 7 4 L S 3 7 3 • D M 7 4 L S 3 7 4 3 - S T A T

E O c t a l D - T y p e T r a n s p a r e n t L

a t c h e s a n d E d g e - T r i g g e r e d F

l i p - F l o p s




LIFE SUPPORT POLICY















April 1986

Revised March 2000

D M7 4 L S

3 7 3 • D M7 4 L S 3 7 4 3 - S T A T E O c t al D - T y p eT r an s p ar en t L a t ch

e s an d E d g e- T r i g g er e d F l i p- F

l o p s

DM74LS373 • DM74LS374

3-STATE Octal D-Type Transparent Latchesand Edge-Triggered Flip-Flops

General DescriptionThese 8-bit registers feature totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-tively low-impedance loads. The high-impedance state and

increased high-logic level drive provide these registers with

the capability of being connected directly to and driving the

bus lines in a bus-organized system without need for inter-

face or pull-up components. They are particularly attractivefor implementing buffer registers, I/O ports, bidirectionalbus drivers, and working registers.

The eight latches of the DM74LS373 are transparent D-

type latches meaning that while the enable (G) is HIGH the

Q outputs will follow the data (D) inputs. When the enableis taken LOW the output will be latched at the level of thedata that was set up.

The eight flip-flops of the DM74LS374 are edge-triggered

D-type flip flops. On the positive transition of the clock, theQ outputs will be set to the logic states that were set up at

the D inputs.

A buffered output control input can be used to place theeight outputs in either a normal logic state (HIGH or LOWlogic levels) or a high-impedance state. In the high-imped-

ance state the outputs neither load nor drive the bus lines

significantly.

The output control does not affect the internal operation ofthe latches or flip-flops. That is, the old data can beretained or new data can be entered even while the outputs

are OFF.

Featuress Choice of 8 latches or 8 D-type flip-flops in a single

package

s 3-STATE bus-driving outputs

s Full parallel-access for loading

s Buffered control inputs

s P-N-P inputs reduce D-C loading on data lines

Ordering Code:








IDM29901NC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide




D M 7 4 L S 3 7 3 • D M

7 4 L S 3 7 4

Connection Diagrams

DM74LS373 DM74LS374

Function Tables

DM74LS373 DM74LS374

H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don’t Care Z = High Impedance State

↑ = Transition from LOW-to-HIGH level Q0 = The level of the output before steady-state input conditions were established.

Logic Diagrams

DM74LS373

Transparent Latches

DM74LS374

Positive-Edge-Triggered Flip-Flops

Output EnableD Output

Control G

L H H HL H L L

L L X Q0

H X X Z

OutputClock D Output

Control

L ↑ H HL ↑ L L

L L X Q0

H X X Z




D M7 4 L S

3 7 3 • D M7 4 L S 3 7 4









Note 2: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.





Supply Voltage 7V

Input Voltage 7V









tW Pulse Width Enable HIGH 15ns

(Note 3) Enable LOW 15

tSU Data Setup Time (Note 2) (Note 3) 5↓ nstH Data Hold Time (Note 2) (Note 3) 20↓ ns



Max Units(Note 4)




VOL LOW Level VCC = Min, IOL = Max






IOZH Off -State Output Current with VCC = Max, VO = 2.7V20 µA


IOZL Off -State Output Current with VCC = Max, VO = 0.4V−20 µA



ICC Supply Current VCC = Max, OC = 4.5V,24 40 mA

Dn, Enable = GND




D M 7 4 L S 3 7 3 • D M

7 4 L S 3 7 4


Note 6: CL = 5 pF.




RL = 667Ω

Symbol Parameter From (Input)C

L = 45 pF C

L = 150 pF

UnitsTo (Output) Min Max Min Max

tPLH Propagation Delay TimeData to Q 18 26 ns


tPHL Propagation Delay TimeData to Q 18 27 ns


tPLH Propagation Delay TimeEnable to Q 30 38 ns


tPHL Propagation Delay TimeEnable to Q 30 36 ns


tPZH Output Enable TimeOutput Control to Any Q 28 36 ns


tPZL Output Enable TimeOutput Control to Any Q 36 50 ns

to LOW Level Output

tPHZ Output Disable TimeOutput Control to Any Q 20 ns


tPLZ Output Disable TimeOutput Control to Any Q 25 ns








tW Pulse Width Clock HIGH 15ns

(Note 8) Clock LOW 15

tSU

Data Setup Time (Note 7) (Note 8) 20↑ ns

tH Data Hold Time (Note 7) (Note 8) 1↑ ns





D M7 4 L S

3 7 3 • D M7 4 L S 3 7 4





Note 11: CL = 5 pF.


Max Units(Note 9)





VOutput Voltage VIL = Max, VIH = Min

IOL = 12 mA, VCC = Min 0.25 0.4




IOZH Off-State Output Current with VCC = Max, VO = 2.7V20 µA


IOZL Off-State Output Current with VCC = Max, VO = 0.4V−20 µA



ICC Supply Current VCC = Max, Dn = GND, OC = 4.5V 27 45 mA

RL = 667Ω


Min Max Min Max






tPZH Output Enable Time28 44 ns


tPZL Output Enable Time 28 44 nsto LOW Level Output

tPHZ Output Disable Time20 ns


tPLZ Output Disable Time25 ns





D M 7 4 L S 3 7 3 • D M

7 4 L S 3 7 4


20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 WidePackage Number M20B




D M7 4 L S

3 7 3 • D M7 4 L S 3 7 4



Package Number M20D



a l D - T y p e T r a n s p a r e n t L

a t c h e s a n d E d g e - T r i g g e r e d F

l i p - F l o p s



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