ELEC 7770 Advanced VLSI Design Spring 2012 Timing Verification and Optimization

Spring 2012, Feb 6 . . .Spring 2012, Feb 6 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design

Spring 2012Spring 2012 Timing Verification and OptimizationTiming Verification and Optimization

Vishwani D. AgrawalVishwani D. Agrawal

James J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn University, Auburn, AL 36849ECE Department, Auburn University, Auburn, AL 36849

[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr12/course.html


Proof of CorrectnessProof of Correctness

Static timing analysis proves the timing Static timing analysis proves the timing correctness. That is, the circuit is guaranteed to correctness. That is, the circuit is guaranteed to work at the clock rate determined by the critical work at the clock rate determined by the critical path.path.

But the circuit may also work correctly at faster But the circuit may also work correctly at faster speeds.speeds.

Because the critical path identified by STA Because the critical path identified by STA (static timing analysis) may be a “false path”.(static timing analysis) may be a “false path”.

STA overestimates the delay of the circuit.STA overestimates the delay of the circuit.


False and True PathsFalse and True Paths A false path cannot propagate an event and hence A false path cannot propagate an event and hence

cannot affect the timing of the circuit. False paths are cannot affect the timing of the circuit. False paths are dynamically unsensitizable.dynamically unsensitizable.

Dynamically sensitizable path (true path): All off-path Dynamically sensitizable path (true path): All off-path inputs must settle down to their non-controlling values inputs must settle down to their non-controlling values when the event propagates through the path.when the event propagates through the path.

1z

ya

b

c

de

f 1

1 2

3

4

0 1

0

1 1

1

True path of length 4



Static Sensitization of PathStatic Sensitization of Path Static sensitization of path: All off-path inputs can be Static sensitization of path: All off-path inputs can be

simultaneously set to their non-controlling values.simultaneously set to their non-controlling values. Longest path in the following example is statically Longest path in the following example is statically

unsensitizable. Such paths are often referred to, though unsensitizable. Such paths are often referred to, though

not correctly (why?),not correctly (why?), as false paths.as false paths.

1z

ya

b

d e

f1

1 2

3

0

1

False path of length 4


1

11

1


An ExampleAn Example Statically unsensitizable (false) path.Statically unsensitizable (false) path. P. C. McGeer and R. K. Brayton, P. C. McGeer and R. K. Brayton, Integrating Integrating

Functional and Temporal Domains in Logic Functional and Temporal Domains in Logic DesignDesign, Springer, 1991., Springer, 1991.

g

a

b

d

e

f

0

0

1

1

c1

False path of delay 3

1

1

0


Example (Cont.)Example (Cont.) Another statically unsensitizable false path.Another statically unsensitizable false path. P. C. McGeer and R. K. Brayton, P. C. McGeer and R. K. Brayton, Integrating Integrating

Functional and Temporal Domains in Logic Functional and Temporal Domains in Logic DesignDesign, Springer, 1991., Springer, 1991.

g

a

b

d

e

f

1

0

1

1

c1

Two false paths of delay 3

1

00


Example (Cont.)Example (Cont.) Two paths are dynamically sensitizable and will affect the Two paths are dynamically sensitizable and will affect the

timing if both are together faulty.timing if both are together faulty. P. C. McGeer and R. K. Brayton, P. C. McGeer and R. K. Brayton, Integrating Functional Integrating Functional

and Temporal Domains in Logic Designand Temporal Domains in Logic Design, Springer, 1991., Springer, 1991.

g

a

b

d

e

f

0

1

1

c1

False paths of delay 3

1

2 3


Static Sensitization ConditionStatic Sensitization Condition

Off-path inputs

xy

z

There must exist an input vector (PI) that satisfies the following conditions:

∂y/∂x = 1, ∂z/∂y = 1, . . .

Where ∂y/∂x = y(x=1, PI) y(x=0, PI) is Boolean difference


An ATPG MethodAn ATPG Method

xy

z

Stuck-at-0

Path is false if this fault is redundant


Optimism and PessimismOptimism and Pessimism

Dynamicallysensitizable

paths

Staticallysensitizable

Paths(optimistic)

Structural paths analyzed by STA (pessimistic)


Theorem 1Theorem 1

Every statically sensitizable path is dynamically Every statically sensitizable path is dynamically sensitizable.sensitizable.

Proof: Since a vector exists to sensitize the path, Proof: Since a vector exists to sensitize the path, if that vector does not specify the path input, if that vector does not specify the path input, then toggling the primary input at the origin of then toggling the primary input at the origin of the path will propagate an event through the the path will propagate an event through the path.path.

P. C. McGeer and R. K. Brayton, P. C. McGeer and R. K. Brayton, Integrating Integrating Functional and Temporal Domains in Logic Functional and Temporal Domains in Logic DesignDesign, Springer, 1991, p. 35., Springer, 1991, p. 35.


Theorem 2Theorem 2 The longest path in a circuit is dynamically The longest path in a circuit is dynamically

sensitizable iff it is statically sensitizable.sensitizable iff it is statically sensitizable. Proof: Because this is the longest path, all off-Proof: Because this is the longest path, all off-

path inputs will settle to their sensitizing values path inputs will settle to their sensitizing values at the inputs of any gate before the on-path at the inputs of any gate before the on-path event propagates through that gate.event propagates through that gate.

P. C. McGeer and R. K. Brayton, P. C. McGeer and R. K. Brayton, Integrating Integrating Functional and Temporal Domains in Logic Functional and Temporal Domains in Logic DesignDesign, Springer, 1991, p. 37., Springer, 1991, p. 37.


Proof of Theorem 2Proof of Theorem 2

Case 1: Static sensitization does not specify the Case 1: Static sensitization does not specify the value at the path origin.value at the path origin.

Toggling the path origin will propagate an event Toggling the path origin will propagate an event through the path causing dynamic sensitization.through the path causing dynamic sensitization.

Example:Example:

10

Statically sensitized path

A 01 or 10here will propagatethrough the path


Proof of Theorem 2 (Cont.)Proof of Theorem 2 (Cont.)

Case 2: Static sensitization specifies the value at the path origin.Case 2: Static sensitization specifies the value at the path origin. Toggling the path origin will propagate an event through the path Toggling the path origin will propagate an event through the path

causing dynamic sensitization because the event on the longest causing dynamic sensitization because the event on the longest path will see all gates sensitized through shorter paths.path will see all gates sensitized through shorter paths.

Example:Example:

0

1

Statically sensitized path

This eventpropagatedthroughlongest path

Apply 01 event here

Shorter path sets this to1 before the event arrives onthe longest path

01


Proof of Theorem 2 (Cont.)Proof of Theorem 2 (Cont.) Case 3: Longest path is statically unsensitizable.Case 3: Longest path is statically unsensitizable. Toggling the path origin will not propagate any Toggling the path origin will not propagate any

event through the path. Toggling other input only event through the path. Toggling other input only dynamically sensitizes shorter path.dynamically sensitizes shorter path.

Example:Example:

01

Statically unsensitizable path

This event didnot propagatethroughlongest path

Apply 01 events

Shorter path sets this to1 before the event arrives onthe longest path

01

01


Speeding Up a CircuitSpeeding Up a Circuit

a

2

2

2

w

u

v

x

y

z

a

w

u

v

x

y

z

0 1 2 3 4 5 6 7 time

2

2

3

False path



a

2

2

2

w

u

v

x

y

z

a

w

u

v

x

y

z

0 1 2 3 4 5 6 7 time

2

2

3

False path



a

2

2

2

w

u

v

x

y

z

a

w

u

v

x

y

z

0 1 2 3 4 5 6 7 time

2

2

1

Reducing the delay of a false path can increase circuit delay.



a

2

2

2

w

u

v

x

y

z

a

w

u

v

x

y

z

0 1 2 3 4 5 6 7 time

2

2

1

False path


A Delay Optimization AlgorithmA Delay Optimization Algorithm REDUCE_DELAY (Circuit graph (V, E), REDUCE_DELAY (Circuit graph (V, E), εε))

Repeat {Repeat {Compute critical paths and critical delay Compute critical paths and critical delay ΔΔSet output data ready time to Set output data ready time to ΔΔCompute slacksCompute slacksU = vertex subset with slack < U = vertex subset with slack < εεW = select vertices in UW = select vertices in UApply transformation to vertices in WApply transformation to vertices in W

} until (no transformation can reduce } until (no transformation can reduce ΔΔ)) }} G. De Micheli, G. De Micheli, Synthesis and Optimization of Digital Synthesis and Optimization of Digital

CircuitsCircuits, McGraw-Hill, 1994, p. 427., McGraw-Hill, 1994, p. 427.


Example of a Transformation (1)Example of a Transformation (1)

2

2

2

2

2

1

1

1

Δ = 11

a

b c

d e

g

x

y

x = a’ + b’ + c’ + d’ + e’

3



2

2

2

2

2

1

1

1

Δ = 11

a

b c

d e

g

x

y

x = a’ + b’ + c’ + d’ + e’, all inputs are symmetric.

3 Isolate and resynthesize



2

2

2

22

2 1

1

11

Δ = 8

x

y

d

b c

a e

g

3

x = a’ + b’ + c’ + d’ + e’, a and d are interchanged.


32-bit Ripple-Carry Adder32-bit Ripple-Carry Adder

FA0

FA1

FA2

FA31

c0 a0 b0

a1 b1

a2 b2

a31 b31

sum0

sum1

sum2

sum31

c31


One-bit Full-Adder CircuitOne-bit Full-Adder Circuit

ai

bi

XOR

AND

XOR

ANDOR

ci

sumi

Ci+1

FAi


Speeding Up the AdderSpeeding Up the Adder16-bit ripple carry adder

a0-a15

b0-b15

cin

sum0-sum15

16-bit ripple carry adder

a16-a31

b16-b31

0

16-bit ripple carry adder

a16-a31

b16-b31

1

Mu

ltip

lex

er

sum16-sum31, c31

0

1

This is a carry-select adder

ELEC 7770 Advanced VLSI Design Spring 2012 Timing Verification and Optimization

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