Elastic Buffer: data transfer in 2 clock domains

Albert Chun (M.A.Sc. Candidate)

Ottawa-Carleton Institute for Electrical & Computer Engineering (OCIECE)

Ottawa, Ontario, Canada

Wednesday April 17th, 2002

Table of Contents

1.0 Background

2.0 Mechanism

3.0 Block Diagram (2:1 Mux with elastic buffers)

4.0 Required Components

5.0 Clock Divider

6.0 Design Approach

7.0 References

1.0 Background

• Data transfer across 2 clock sources is a common practice in today’s high speed data transmission circuits

• On-chip clock speed is maintained by phase lock loop circuit

• Once “phase locked”, on-chip clock speed equals to incoming reference clock speed; but with constant phase difference

• For high speed applications, data can be buffered with double-edged flip-flops

• Problem occurs when the phase difference is larger than the width of a data bit; we may sample the incoming data signal at an incorrect moment, and lose information!

• One of the methods to eliminate this problem is to utilize an elastic FIFO buffer at the beginning of the data path, hence every data bit will be sampled without loss

2.0 Mechanism

• The goal is to ensure the on-chip clock edge samples the data bit right at the centre of the “bit” (i.e. data eye), without missing any data bit

• Since we cannot control the phase difference, we “stretch” the data bit until it has adequate room around the on-chip clock edge

• We can accomplish this “stretching” by reducing the incoming data stream to lower bit rates

• In order to keep the same throughput, we have to demultiplex the incoming data from a high speed serial format to a lower speed parallel format

• But this is only half the story…

• We need to multiplex these parallel data streams back to a higher speed serial format, for subsequent stages of circuits

3.0 Block Diagram (2:1 MUX with elastic buffers)

div1, div2,div4

div1, div2,div4

Output data at x Mbps

Input data at x/2 Mbps

Input data at x/2 Mbps

Input clock

from PLL

4.0 Required Components

Elastic Buffer

• latches

• flip-flops

• 2:1 muxes

Clock Divider

• flip-flops

• inverters (for single-ended signal implementation only)

5.0 Clock Divider

D Q

Qb

Asynchronous clock divider

• provides div2 & div4 output

• can get I & Q versions

• tap from latch output (of either flip-flop stage)

Synchronous clock divider

• only div4 output available

• can get I & Q versions

• tap from latch output (of final flip-flop)

D Q

Qb

D Q

Qb

D Q

Qb

clk

clk/2

clk/4

clk/4

clk

6.0 Design Approach

• Estimate highest data output rate with 0.35um CMOS technology

• Assign highest data output rate for final 2:1 mux stage

• Utilize 1:4 demux and 4:1 mux stages for elastic buffer

• Investigate advantage/disadvantage of synchronous/asynchronous clock divider for this project

• Implement circuit with CMOS CML circuit

• Implement circuit with standard CMOS circuit (if time permits)

• Schematic-level design, layout, post-layout simulation

7.0 References

• “2.5Gbit/s 16:1 Multiplexer GD16523” data sheet, GiGa (an Intel company), August 2001

• “LXT6282 Octal E1 Digital Interface with CRC-4 Monitoring and Jitter/Wander Suppression” data sheet, Intel, January 2001

• Shing-Chi Wang (NORTEL Networks), “Multiplexers and Demultiplexers”, 2001 GaAs IC Symposium Short Course, 2001