Efficient On-chip ESD Protection Design and Verification ...€¦ · GDS . ESD clamp cell list :...

Renesas System Design Co., Ltd.

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Yoko Otsuka, Yasuyuki Morishita, Junichi Mano, Toshiki Kanamoto

©2014 Renesas System Design Co., Ltd. All rights reserved.

Efficient On-chip ESD Protection Design and Verification Methodology using EDA Tools

AESE2014

2 /22 ©2014 Renesas System Design Co., Ltd. All rights reserved.

Introduction

Efficient ESD Design and Verification Flow

Application Examples

Summary

Outline


Difficulty of ESD Design Check

Automated ESD design check is necessary

Advanced LSI products has multiple power domains for various functional parts. They use many metal layers with high integration. ESD design check is complicated and it wastes a lot of time.

Logic

IP Modules

Chip image

5V I/O Cells 3.3V I/O Cells


Requirements for ESD Design Check

It is important that - the metal resistance is low to protect internal circuits - the metal and via doesn’t fail for ESD current.

Power clamp

Vgs

IO

Rvdd

Rvss

VDD VDDA

VSS VSSA

Power clamp

ESD

⇒ Resistance check

⇒ Current density check


Introduction



Summary

Outline


ESD Verification throughout Design Flow

Design Flow for IC Products

I/O Cell Design

Full Chip Integration

ESD Verification

IP Module Design

ESD design concept

ESD Test Using ANSYS- Apache tools

Chip Level Circuit check

Chip Level Layout check

I/O Cell, IP Module Layout check

I/O Cell, IP Module Circuit check

In-advance ESD verification is important for efficient chip design.


Application ANSYS-Apache Tools

Input Details

I/O Cell Totem - BPA

GDS BPA file

Check current density (CD) easily.

IP Module Full Chip (small)

Totem -PathFinder

GDS ESD clamp cell list ESD Rule

Check resistance and CD between bumps comprehensively.

Totem -Point to Point

GDS

Check resistance between any two points.

Full Chip (large)

RedHawk -PathFinder

GDS LEF, DEF ESD clamp cell list ESD Rule

Check resistance and CD in a large full chip comprehensively.

EDA Tools for ESD Design Verification

Select best tools for several applications.


Renesas original input file enables easy verification.

ESD Static Analysis Solution

Input.file

ploc GDSII gds.config gsr

Requirement file gawk

setup.conf

Database

GDS map

technology

ESD rule ESD clamp

Perl

Totem/PathFinder-S Analysis

Renesas original


Introduction



Summary

Outline

- for I/O Cell - for IP Module - for Full chip



Input Details


GDS BPA file



Totem -PathFinder




GDS


Full Chip (large)

RedHawk -PathFinder


Check resistance and current density in large full chip comprehensively.



Totem BPA Analysis Assign a power source on metal of ESD protection block.

↑ ↓

VSS pin VDD pin

VSS pin VDD pin

1.3A 1.3A

ESD protection

BPA Area


Current Density Check of I/O Cell

Check CD within I/O cells and redesign for error area.

Real metal damage

Metal 3 layers

Metal 2 layers

Error area over current limit is showed with red color.

BPA Result (before and after redesign)

Metal 3 layers

protection



Input Details


GDS BPA file



Totem -PathFinder




GDS


Full Chip (large)

RedHawk -PathFinder





Totem PathFinder Analysis Set Ron for ESD protection cell. It is available to verify resistance and current density comprehensively.

I/O Power clamp

VDD

VSS

Power clamp

Power clamp

VDDA

VSSA

I/O

VDD

VSS

VDDA

VSSA

Set Ron for 1 direction only


Resistance and CD Check of IP Module

Resistance Result Current Density Result

Check resistance and CD between bump and bump along ESD guideline.

Resistance List



Input Details


GDS BPA file



Totem -PathFinder




GDS


Full Chip (large)

RedHawk -PathFinder





Necessary of Point to Point Check

For CDM event, it is important that resistance between internal circuit and ESD protection is low . Because CDM current is very high with short duration.

CDM(500V)

MM(200V) HBM(2000V)

ESD Event

Power clamp

VDD

VSS VSSA

VDDA

CORE area I/O area

Internal circuit


Resistance Check for Internal Circuit

Check resistance and redesign high resistance metal and via from short pass route.

R=13Ω R=1Ω

VDD

VSS VSSA

VDDA

Check Points

Change 1 metal layer to 2 metal layers with wide metal width.

Point to Point Result



Input Details


GDS BPA file



Totem -PathFinder




GDS


Full Chip (large)

RedHawk -PathFinder





Resistance and CD Check of Large Chip

Current Density map

10Ω

Tool ver. V14.1.2

GDS size 279M

CPU Time 6hr

Check resistance and CD between bumps comprehensively. Check current flow uniformity. ( *)

* analysis time for 46 paths

Not enough metal for current uniformity


Introduction



Summary

Outline


Summary

Automated ESD design check is necessary. Because it prevents spending a lot of time and taking a miss for check. Check resistance and current density of ESD path using ANSYS-Apache tools. In-advance ESD verification is important for efficient chip

design.

Select best tools for several applications and use Renesas original input file.

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Efficient On-chip ESD Protection Design and Verification ...€¦ · GDS . ESD clamp cell list :...

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