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EEEE 381 – Electronics I

Lab #6: Frequency Response of CMOS Amplifier

Overview

The objective of this lab is to investigate the frequency response of a CMOS operational amplifier (op-amp) through simulation and experimental measurement.

Theory

At low to moderate frequencies, the internal parasitic capacitances in a MOSFET are too small to have a material impact on the frequency response of a circuit. Recall that the impedance of a capacitor varies inversely with frequency and the magnitude of the capacitance. For small capacitance values and low frequencies, then, the internal parasitic capacitances behave essentially like open circuits and they are omitted from the small-signal MOSFET model.

At high frequency, however, the effect of the internal capacitances becomes significant, and the small-signal MOSFET model must be augmented to include their effects. The MOSFET can be represented at high frequency using the model shown in Figure 1.

Figure 1. High-Frequency Small-Signal MOSFET Model

Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 2017 Page 1 of 10Rochester Institute of Technology Teaching Assistants — Office: 09-3248

Gate-to-source capacitance Cgs and gate-to-drain capacitance Cgd are related to SPICE model parameters CGSO and CGDO, respectively. The source-body capacitance Csb and drain-body capacitance Cdb represent the capacitances of the reverse-biased pn junction formed between each of the source/drain diffusions and the body, respectively. Recall that the small-signal substrate (body) connection is always at small-signal ground since NMOS and PMOS substrates are connected to the lowest and highest DC supply voltages, respectively.

This lab will investigate the frequency response of the two-stage CMOS op-amp that was designed and tested in the previous lab. The two-stage amplifier is shown in Figure 2. Specific values of R, RD7, and/or RD8 were determined as part of Lab #5.

Figure 2. Two-stage CMOS amplifier

The 100 uF capacitors in this circuit are not really necessary because this is a DC amplifier. However, at frequencies of 1Khz and higher they can be considered “shorts”. Op amps are often compensated (made more stable… less likely to go into oscillation) by placing a capacitor in the signal path that will cause the gain to decrease at higher frequencies. A capacitor between the gate and drain of M7 is a good choice because there is voltage gain between the input and output of the common source PMOS amplifier. Miller’s theorem says that an equivalent capacitance Ceq = C multiplied by (1-Av) and placed from the input to ground. The internal capacitances of the transistors in this circuit are very small, in the few Pico Farad range for total capacitance. Thus placing a 2nF capacitor from gate to drain of M7 will be the dominate capacitance determining the high frequency response. If the gain is -9 V/V then the Miller Capacitance is 20nF giving a high frequency corner at 1/(ReqCeq) where Req is the equivalent resistance “seen”

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from the gate of M7 to ground which is ro of the differential amplifier, 25Kohms. The corner frequency value is 1/(2nF x 10 x 25K) = 2000 r/s = 318hz. The bode plot for this amplifier is shown in figure 3 below.

Figure 3 shows representative magnitude (top) and phase (bottom) plots for this op-amp. It can be seen from Figure 3 that at the point where the gain magnitude is unity, or 0 dB, there is a phase shift of roughly –220, or a phase margin of –40 compared to a critical value of –180, which is indicative of an unstable amplifier. The phase margin is generally required to be more than +45. The requirement for stability can be stated as the following: the gain curve should cross the 0 dB level before the phase curve reaches –180 (preferably –135 or –120, for phase margins of 45 or 60, respectively). In its present form, this amplifier would be considered to be unstable, although the instability problem can be easily fixed. Phase margin can be improved by “increasing the compensation”, wherein the position of a pole is moved. Stability and compensation will be studied in Electronics II. The compensation capacitance should be larger.

Figure 3. Examples of magnitude and phase plots

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Pre-Lab

(1) Use PSPICE to simulate the frequency response of the circuit. Obtain the magnitude response, the phase response, the phase margin, and the unity-gain bandwidth.

a) See appendix on using SPICE model RIT4007N7 and RIT4007P7

b) Under Part properties set the following for NMOS, L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.059 NRS=0.059

c) Under Part properties set the following for PMOS, L=10u W=360u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.027 NRS=0.027

d) Some hints for determining gain, unity-gain bandwidth (the frequency at which the gain has dropped to unity, or 0 dB), and phase margin are given below:

Gain For the gain, perform an AC sweep (use the VAC source = 1V). Choose Logarithmic Sweep type, and under that choose Decade, with a frequency

range of 1Hz–100MHz. Use Points / Decade = 10. Run SPICE then add TRACE for gain in dB. See below: D(V(Output)/V(Input)) Select Plot and Add Plot to window then add TRACE for phase in degrees.

P(V(Output)/(V(Input))

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Unity-gain bandwidth For the unity-gain bandwidth, observe the frequency where the gain becomes 0 dB.

Phase Margin For Phase margin determine the phase in degrees when the gain becomes 0dB.

(2) (Optional) If you would like to see the effect of compensation, try adding a capacitor of 20 nF — between the gate and drain of M7, then re-simulating to see the effect on gain and phase. This compensation technique takes advantage of the Miller effect to magnify the compensation capacitance saving area on the integrated circuit chip.

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Lab Exercise

(1) Measure the magnitude and phase at the output of the two-stage CMOS amplifier, varying the frequency of the small-signal input (shown as 1 kHz in Figure 2). The frequency of vsig

should be varied from 1 kHz to a frequency that is sufficiently high to ensure that the magnitude of the voltage gain drops to unity (0 dB) — i.e., until the output signal amplitude is equal to the input signal amplitude. Most of the function generators go to up to 15 MHz. (Don’t forget that the input is not 1 V in magnitude.)

The frequencies should be spaced roughly equally in the log -frequency domain — e.g., at 1 kHz, 10 kHz, 100 kHz, etc. Measurements should be made at a minimum of five frequencies so as to allow the subsequent construction of representative magnitude and phase plots like those shown in Figure 3.

Use a sinusoidal signal vsig from the signal generator of no more than 200 mV amplitude (recall that there is substantial gain in the amplifier). Measure the peak-to-peak voltage amplitudes of the input (vid) and output (vo) waveforms at each measurement frequency. Note that the input to the differential amplifier vid is not the same as the signal source vsig. Also, measure the phase difference between each pair of waveforms at each measurement frequency. Calculate the gain magnitude for each of the frequencies using

Gain dB = 20 log10( vo

vid).

(2) (Optional) If you would like to see the effect of compensation, try putting a capacitance — e.g., 20 nF — between the gate and drain of M7, then re-measuring to see the effect on gain and phase. This compensation technique takes advantage of the Miller effect to magnify the compensation capacitance to an effective level that is actually needed for stabilization of the circuit.

Analysis of results

(1) Based on your measurements, construct Bode magnitude and phase plots like those shown in Figure 3. Make sure the frequencies are spaced out in the log frequency domain. You may need to determine where the graph crosses the 0 dB level by extrapolation if the frequency generator does not go high enough in frequency.

(2) From your magnitude response plot, determine the upper 3-dB frequency, fH. Compare this value to your value from pre-lab simulations. Also, determine the unity-gain frequency and the phase margin of the amplifier.

(3) Determine the gain-bandwidth product of the amplifier.

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Appendix A — SPICE Instructions

Please refer to the following for assistance in modifying the MbreakN MOSFET so that it represents the NMOS FETs in the CD4007 chip.

We want to place the MbreakN Schematic symbol on our schematic then edit and display the properties to represent the CD4007 transistors. We also want to change the name of the spice Model from MbreakN to RIT4007N7.

Finally, we want to let SPICE know where to find the text file that has the SPICE MODEL in it. That is done by editing the SPICE simulation profile. Under the Configuration Files Tab, select Include, and then Browse to the Location of the file where the SPICE model is. (Note: you should have already placed the text file that has the RIT4007N7 SPICE model in it on your computer in some location)

Right Click on the transistor and select “Edit Properties”, Pivot, Display, Apply

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These are two of the several SPICE models in the text file “RIT_SPICE_Models.txt” provided on the lab webpage. You should download the entire text file and place it on your computer. You can include all the models by telling SPICE the location of the downloaded file as shown on the page above (page 7). SPICE will actually only use the models called for by the devices in your schematic.

*SPICE MODELS FOR RIT DEVICES AND LABS - DR. LYNN FULLER 1-11-2017*LOCATION DR.FULLER'S COMPUTER*and also at: http://people.rit.edu/lffeee**-----------------------------------------------------------------------*Used in Electronics II for CD4007 inverter chip*Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.059 NRS=0.059.MODEL RIT4007N7 NMOS (LEVEL=7+VERSION=3.1 CAPMOD=2 MOBMOD=1+TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8 +VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)**Used in Electronics II for CD4007 inverter chip*Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=0.027 NRD=0.027.MODEL RIT4007P7 PMOS (LEVEL=7+VERSION=3.1 CAPMOD=2 MOBMOD=1+TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8+VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)*-----------------------------------------------------------------------

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Enlarged CD4007 Pin Out

Check-Off Sheet

A. Pre-Lab

PSPICE simulation of the frequency response of the two-stage CMOS amplifier, resulting in magnitude and phase response plots.

B. Experimental

Two-stage CMOS amplifier built and debugged (may have been retained from Lab #5).

Measurements of magnitude and phase taken at a minimum of five logarithmically-spaced frequencies. Measurements must be taken at frequencies that are sufficiently high to show the upper 3-dB frequency and the unity-gain frequency.

TA Signature: ____________________________ Date: ___________________________

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