EEE2243Digital System DesignChapter 6: Datapath Component

by Muhazam Mustapha, February 2011

Learning Outcome

• By the end of this chapter, students are expected to understand the design, operation and block diagram of the following datapath components:– Register and register file– Shifter, counter, incrementer– Comparator– Adder, subtractor, multiplier and ALU

Chapter Content

• Register and Register File

• Shifter

• Counter, Incrementer and Timer

• Comparator

• Adder, Subtractor, Multiplier

• Arithmetic and Logic Unit

• Modular Verilog

Datapath Component

Datapath Component• Datapath component is a collection of memory

and computation circuits that when put together and with proper control, can perform a larger scale of operation

• In previous chapters we have covered many of the components like:– Counter, Decoder and Multiplexer

• We will go into more details on the components that we already covered, and some new ones

Vahid 4.1 pg 167

Register & Register File

Register• A collection of flip-flops used to store data or

maintain states in FSM• In normal operations registers load on every

clock pulse• In datapath operation we need to set the

register to load only when we want it to

DQ

DQ

DQ

DQ

I2I3

Q2Q3 Q1 Q0

I1 I0

clk

4-bit registerload

Conditional Parallel Load• In datapath operation register load operations

are mostly parallel – only communication applications use serial mode load

• The load operation however, needs to be done when a LOAD signal is on

• This can be done in BEHAVIORAL approach using a 2-to-1 mux at D input– diagram on next slide

• The LOAD signal will determine either the flip-flop is to be loaded with new data or maintain current data by feedback

Conditional Parallel Load

1 0

D

Q

Q3

I3

1 0

D

Q

Q2

I2

1 0

Q

Q1

I1

1 0

D

Q

Q0

I0

load

= 0

1 02×1

D

Q

Q3

I3

loadload

1 0

D

Q

Q2

I2

1 0

D

Q

Q1

I1

1 0

D

Q

Q3

I3

1 0

D

Q

Q2

I2

1 0

D

Q

Q1

I1

1 0

D

Q

Q0

I0

load

= 1

(b)

(c)(a)

1 0

D

Q

Q0

I0

I3 I2 I1 I0

Q3 Q2 Q1 Q0

D

Vahid Figure 4.1 pg 169

Parallel Register Example

Q3 Q2 Q1 Q0

a3 a2 a1 a0

I3 I2 I1 I0

Q3 Q2 Q1 Q0

I3ld1 I2 I1 I0

ld1 ld1

Q3 Q2 Q1 Q0

I3 I2 I1 I0

R1

R0

R2

clk????

????

R1????R2

–>1111

R0

clk

a3..a0

R0

R1

R2

give

n

????

1111

R1????R2

1111–>0001

R0

1111

0001

R10000R2

0001–>1010

R0

0001

1010

R11110R2

1010

R0

1010

1010

R10101R2

1010

R0

1010

1010

R10101R2

1010

R0

(a)

(b)

1111

????

????

????

????

????

0001

1111

1111

0000

0001

0001

1110

1010

1010

0101

1010

1010

0101

1010

1010

1 2 3 4 5

Shift Register• In some applications, datapath operations need

to perform serial computation• This can be done using shift register• Shift register operates by transferring flip-flop’s

bit content to neighboring flip-flop in the same register while maintaining the conditional LOAD operation– Both SHIFT and LOAD operation are conditional– Some shift registers may have parallel LOAD

operation as well

Vahid pg 173

Shift Register

shr_in

• Implementation: Connect flip-flop output to next flip-flop’s input

1 02×1

D

Q

Q3

1 0

D

Q

Q2

1 0

D

Q

Q1

1 0

D

Q

Q0sh

r=11 0

2×1

D

Q

Q3

shr

shr_in

shrshr_in

1 0

D

Q

Q2

1 0

D

Q

Q1 (b)

(c)

(a)

1 0

D

Q

Q0

Q3 Q2 Q1 Q0

Datapath Implementation

Vahid Figure 4.10 pg 174

Rotate Register• Bit coming out from one end will go into the

other end• Exercise: Draw out yourself the datapath

implementation of rotate register

Vahid Figure 4.11 pg 174

More Complicated Register• Behavioral control of register by mux can

already provide us a good number of features• The following is a register with 2 control line:

s1

shr_in

s0

3 2 1

I3

0

D

Q

Q3

Q2 Q1 Q0Q3

I2 I1 I0I3

Q2

03 2 1

I2

0

D

Q

0

Q1

3 2 1

I1

0

D

Q

0

Q0

3 2 1

I0

0

D

Q

0

4×1 shr_ins1s0

(a)

(b)

Functions:

OperationMaintain present valueParallel loadShift rightLoad zero

s00101

s10011

Vahid Figure 4.13 pg 176

Boolean Algebra Approach Register Design• For some performance improvement, Boolean

algebra design can be used, but we won’t go into too much detail:

Q2 Q1 Q0Q3

Q2 Q1 Q0Q3

I2 I1 I0I3

I2 I1 I0I3

s1shr_in

shr_in

shr

shl

ld

s0shl_in

shl_in

s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl

s0 = ld’*shr’*shl + ld

combi-nationalcircuit

Vahid pg 177-178

Register File• In some designs we may require too many

registers• In such designs we might be using too many

wires and may cause congestions or we may exceed the synthesizable limit for no. lines

• This can be solve by sharing lines – BUS• The registers will be accessed through address

and only connect to the bus lines when selected• There will be many High-Z capable connections

Vahid 4.10 pg 225

Register File32

2

32

2

W_data

W_addr

W_en

R_data

R_addr

R_en4x32

register file

Vahid Figure 4.78 (modified), 4.79, 4.80

Register File Timing Diagram

32

2

32

2

W_data

W_addr

W_en

R_data

R_addr

R_en4x32

register file

0:1:2:3:

???9

0:1:2:3:

?22?9

0:1:2:3:

?22?9

0:1:2:3:

?22?9

0:1:2:3:

?221779

0:1:2:3:

?22177555

0:1:2:3:

????

9

3

Z

X

22

1 X

X

X 2 3

X 177 555

Z Z Z9 9 55522

X X3 31

cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6clk

W_data

R_data

W_addr

R_addr

W_en

R_en

1 2 3 654

Vahid Figure 4.82

Shifter

Shifter• Shift register makes transfer between memory

elements (flip-flop) to achieve shifting effect• We can speed up the shift process if we remove

the memory element since we don’t have to wait for the clock pulse to actually make the shift happens

• This fast shifting is required especially if the shifting is done to get the effect of multiplication by powers of 2

• Shifter is the datapath component that does this with only multiplexers – no D flip-flop

Vahid 4.8 pg 210

Shifter

<<1

Symbol

i2

q3 q2 q1 q0

in

i3 i1 i0

Left shifter

0 1 0 1 0 1 0 1

in

sh

i3

q3 q2 q1 q0

i2 i1 i0

Shifter with left shift or no shift

inL

i3

q3 q2 q1 q0

i2 i1 i0

inR

2 0s0s1

shLshR

1 2 01 2 01 2 01

Shifter with left shift, right shift, and no shift

Counter, Incrementer & Timer

Modularized Counter• In the previous chapter we designed counter to

just count the clock pulses• As a datapath component, counter needs

control lines so it can be integrated into a bigger design

• We will see more modularized counter design as a datapath component

Vahid 4.9 pg 215

Modularized Up Counter

ld4-bit register

Ctc

4

4 4

4

cnt

4-bit up-counter

+1

• Regular up counter can be modularized to have– Registers to keep count value– Incrementer– Terminal count detector – for up counter, it is an AND

gate as we assume the terminal count is all ones

cnttc C

4-bit up-counter

4

0000

01

00010010001101000101...11100 111110 00000001

Vahid pg 216

Incrementer• Incrementer is an adder whose job is to always

add 1 to its input• It is natural to design incrementer using FULL

adder setting one of the addend to a constant 1• However, a better design will be using cascaded

HALF adders with a 1 addend at LSB– This can be done since the second addend is

basically zero (except at LSB), hence lifting its need as one of full adder inputs which means we can reduce the full adder to half adder

– This results in a simpler circuit

Incrementer

0011 +0001

0011 + 1 +0000

equivalent

a3

co s

FA

co

a2

s3 s2 s1

ciba

co s

FA

ciba

a1

co s

FA

ciba

s0

a0 0

co s

FA

ciba

000 1

a3

co s

H A

co

a2

s3 s2 s1

ba

co s

H A

ba

a1

co s

H A

ba

s0

a0 1

co s

HA

ba

equivalent

Modularized Down Counter• Modular down counter

may have– Registers to keep count

value– Decrementer– Terminal count detector

– for down counter, it is a NOR gate as we assume the terminal count is all zeros

ld4-bit register

Ctc

4

4 4

4

cnt

4-bit down-counter

–1

Decrementer• Decrementer is a subtractor whose job is to

always minus 1 from its input• Decrementer can be designed using full adder

by setting one of the addend to all 1-s– This is true because subtracting by 1 is equivalent to

adding with 2’s complement of 1, and 2’s complement of 1 is a binary number with all 1-s

a3

co s

FA

co

a2

s3 s2 s1

ciba

co s

FA

ciba

a1

co s

FA

ciba

s0

a0 0

co s

FA

ciba

111 1 There is a way to design decrementer using HALF SUBTRACTOR (HS), but we are not going into detail about it as it is not so behavioral design friendly as HS is not well accepted as datapath component

Up/Down Counter• To make it a more useful counter in datapath

circuit, we might want to add more control to the counter

• One possible control is to control the direction counting – either up or down

• This can be done adding another DIR (direction) control line

• DIR will be used to multiplex the:– feedback input to register – either from incrementer

or decrementer– terminal count detecter – either from AND or NOR

gate

Up/Down Counter

4-bit register

Ctc

4

44 44

4

dir

4-bit up/down counter

4 4

–1 +1

1 02x1

1 04-bit 2x1

Vahid pg 217

Timer• Timer is just a counter that is clocked by a

KNOWN clock frequency• Normally it is an up counter, with additional

controls of:– count (CNT) – only count if CNT is 1– clear (CLR) – synchronously reset timer if CLR is 1

Vahid pg 222

Comparator

Equality Comparator• Comparator is a datapath component that test

the values of its two inputs for equality, less than or greater condition

• Equality comparator just test for equality• Obviously equality test can be done by

comparing the equality of the two inputs bit-by-bit

• Comparison can be done bit-by-bit by 2-input XNOR gates, then combine the output by an AND

Vahid 4.4 pg 191

Equality Comparator

a3b3 a2b2 a1b1 a0b0

eq(a)

(b)

a3a2a1a0 b3

eq

b2b1b0

4-bit equality comparator

0 1 1 00 1 1 1

01 1 1

0

• Example comparing 0110 to 0111:

Magnitude Comparator• Magnitude comparator gives all possible

equality, less than or greater than condition• Algorithm to compare A and B starting at MSB:

– If the bit are the same repeat to compare next LSB– Else if bit A is 1 and bit B is 0 then stop by giving

condition A > B– Else if bit A is 0 and bit B is 1 then stop by giving

condition A < B

A=1011 B=10011011 1001 Equal

1011 1001 Equal

1011 1001 Unequal

So A > B

Vahid pg 192

Cascade Comparator• From the algorithm in the previous slide, we can

formulate one stage of the bit-by-bit comparison using the following circuit:

a bfrom previous stage

in_eq

in_gt

in_lt

to next stage

out_gt

out_lt

out_eq

Cascade Comparator• At each stage:

– out_gt = in_gt + (in_eq * a * b)• A>B (so far) if already determined in higher stage, or if higher

stages equal but in this stage a=1 and b=0

– out_lt = in_lt + (in_eq * a * b)• A<B (so far) if already determined in higher stage, or if higher

stages equal but in this stage a=0 and b=1

– out_eq = in_eq * (a XNOR b)• A=B (so far) if already determined in higher stage and in this stage

a=b too

in_gtin_eqin_lt

out_gtout_eqout_lt

IgtIeqIlt

Stage 3

a3 b3

a b

in_gtin_eqin_lt

out_gtout_eqout_lt

Stage 2

a2 b2

a b

in_gtin_eqin_lt

out_gtout_eqout_lt

Stage 1

a1 b1

a b

in_gtin_eqin_lt

out_gtout_eqout_lt

AgtBAeqBAltB

Stage 0

a0 b0

a b

Cascade Comparator• Example comparing 1011 to 1001:

in_gtin_eq

in_lt

out_gtout_eq

out_lt

01

0

Stage3

a3 b3

a b

in_gtin_eq

in_lt

out_gtout_eq

out_lt

Stage2

a2 b2

a b

in_gtin_eq

in_lt

out_gtout_eq

out_lt

Stage1

a1 b1

a b

in_gtin_eq

in_lt

out_gtout_eq

out_lt

AgtBAeqB

AltB

Stage0

a0 b01 1 0 0 1 0 1 1

a b

(a)

=

0

1

0

in_gt

in_eqin_lt

out_gt

out_eqout_lt

Stage3

a3 b3

a b

in_gt

in_eqin_lt

out_gt

out_eqout_lt

Stage2

a2 b2

a b

in_gt

in_eqin_lt

out_gt

out_eqout_lt

Stage1

a1 b1

a b

in_gt

in_eqin_lt

out_gt

out_eqout_lt

AgtB

AeqBAltB

Stage0

a0 b01 1 0 0 1 0 1 1

a b

(b)

=

0

1

0

01

0

Cascade Comparator• Example comparing 1011 to 1001 (continue):

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Stage3

a3 b3

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Stage2

a2 b2

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Stage1

a1 b1

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

AgtB

AeqB

AltB

Stage0

a0 b0

1 1 0 0 1 0 1 1

a b

(c)

1

0

0

>

01

0

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Stage3

a3 b3

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Stage2

a2 b2

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Stage1

a1 b1

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

AgtB

AeqB

AltB

Stage0

a0 b0

1 1 0 0 1 0 1 1

a b

(d)

0

1

0

01

0

Comparator Application• Minimum of 2 numbers:

MIN

IgtIeqIlt

AgtBAeqBAltB

010

A

A B

B

8-bit magnitude comparators I1 I0

2x1 mux8-bit

C

8

88 8 8

8

8

8

C

A BMin

(a)

(b)

Adder, Subtractor & 2’s Complement, Multiplier

Half Adder• Half adders add two 1 bit inputs, then generate

1 bit sum and 1 bit carry

a b

c

c s

a b

s

Half Adders0110

c0001

b0101

a0011

Inputs Outputs

Truth Table Block Diagram Circuit

Full Adder• Full adders add two 1 bit inputs and one carry-in

then generate 1 bit sum and 1 bit carry-out

co s

a b

Full Adder

Truth Table

Block Diagram

Circuits

s01101001

co00010111

ci01010101

b00110011

a00001111

Inputs Outputs

ci

co

ciba

s

Full adder

Larger Adder – Ripple Carry• Arbitrary no. bit

adder can be constructed by cascading half adder and full adder as follows:

• This is called carry ripple technique as the carry is being transferred from one adder to the next one

a3

co s

FA

co

b3 a2b2

s3 s2 s1

ciba

co s

FA

ciba

a1b1

co s

FA

ciba

s0

a0b0

co s

HA

ba

a3

co s

FA

co

b3 a2b2

s3 s2 s1

ciba

co s

FA

ciba

a1b1

co s

FA

ciba

s0

a0b0 0

co s

FA

ciba

OR

Cascading Adders

a3a2a1a0 b3

s3s2s1s0co

s7s6s5s4co

ci

b2b1b0

a7a6a5a4 b7b6b5b4

4-bit adder

a3a2a1a0 b3

s3s2s1s0

s3s2s1s0

co

ci

b2b1b0

a3a2a1a0 b3b2b1b0

4-bit adder

a7.. a0 b7.. b0

s7.. s0co

ci8-bit adder

Subtractor

a3

co s

FA

co

b3

a2

b2

s3 s2 s1

ciba

co s

FA

ciba

a1

b1

co s

FA

ciba

s0

a0

b0

co s

FA

ciba

sub/add

2’s Complement• 2’s comp circuit can be constructed from the

circuit in the previous slide by setting the minuend to 0 (zero)

• Or the following dedicated 2’s comp circuit can be used: