EECE579 Digital Flow

7/30/2019 EECE579 Digital Flow

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EECE579: Digital Design Flows

Usman AhmedDept. of ECE

University of British Columbia



Implementing Digital Circuits

Custom

Standard Cells Compiled Cells Macro Cells

Cell-based

Gate ArraysStructured ASICs FPGA's

Array-based

Semicustom

Digital Circuit Implementation Approaches



Implementing Logic Circuits

HDL

Logic Synthesis

Floorplanning

Placement

Routing

Tape-out

Circuit Extraction

Pre-LayoutSimulation

Post-LayoutSimulation

Structural

Physical

BehavioralDesign Capture

D e s i g n I t

e r a t i o n



Standard Cell Design

• Library of cells thatimplement differentgates

• Cells can have differentwidth but all cells havesame height

(hence Standard Cells)

• Many variants of thesame cell




• Logic SynthesisTransform the HDLdescription into librarycells

• Placement

Where to place a cell ?

• Routing

Connect the placed cells.




Optimizations:• Gate Resizing

• Buffer Insertion

• In-place Re-synthesis



Standard Cell Design: An Example




• Routing channel canbe narrowed if moreinterconnect layersare available



Standard Cell Design: NewGeneration

• Cell-structure hidden under

interconnect layers



Standard Cell Design: Summary

• Used only for the high-speed or low-power applications

• Very expensive, andtime consuming

• (> $2M just for the maskcosts)

• Very high re-spin cost



FPGAs

• FPGA: Field-Programmable Gate Array

CircuitDescription

Expensive

Chip

Manufacturing

Gate

Array



What’s Inside an FPGA?

•

Logic Blocks

- used to implement

logic

- lookup tables and

flip-flops

Altera: LABs

Xilinx: CLBs




•

I/O Blocks

- interface off-chip- can usually support

many I/O Standards




•

Connection

Block

Logic Block

Switch Block

Routing Track

(Horizontal)

Routing Channel(Vertical) {

TILE



Basic Logic Gate: Lookup-Table

Function of each lookup table can be configured byshifting in bit-stream.

Logic Block:

• InputsB i t - S

t r e am



Logic Clusters

• D Q

D Q

D Q

L o

c a l I n t e r c o n n e c t

Several lookup tables aregrouped into “clusters”

- Typically 8 to 10 lookup

tables per cluster

Connections between lookuptables in the same cluster arefast

Connections between lookuptables in different clusters areslow




•

Connection

Block

Logic Block

Switch Block

Routing Track

(Horizontal)

Routing Channel(Vertical) {



Reconfigurable Logic:

Connect LogicBlocks usingFixed MetalTracks andProgrammableSwitches



Implementing Systems in an FPGA

High-speed I/O

Embedded PowerPC

Embedded memories

Hardwired multipliers

FPGA Fabric

Xilin x Vertex-II Pro



Advantages of FPGAs: • "Instant Manufacturability": reduces time to market

• Cheaper for small volumes because you don’t need to pay for fabrication

• means you don’t need to be a big company to make a chip

• Relaxes Designers -> relaxed designers live longer!

Disadvantages of FPGAs: • Slower than custom or standard cell based chips

• Cannot get as much circuitry on a single chip

• Today: ~ 1M gates is the best you can do

~ 200 MHz is about as fast as you can get

• For large volumes, it can be more expensive than gate arrays andcustom chips



Structured ASICs

• Combines good features of FPGAs andStandard Cell ASICs

All the layers are customized for a circuit

- Standard Cell ASIC

Some layers are generalized while a few

layers are customized for a circuit

- Structured ASIC

All the layers are generalized for any circuit

- FPGA

Interconnect

Layers

Transistors



Logic Blocks

• Choices – Fine Grained

• Basic gates: NAND, NOR, XOR, FF etc.

– Medium Grained

• Lookup Tables – Coarse Grained

• Multi-input, Multi-output blocks (e.g., PLAs)

• Configurability

– SRAM cells – Vias

• Lower Level (e.g., between M1 and M2)

• Upper Level (Via stacks brought up to the configurablelayers)



Routing Fabrics

• Metal and Via Programmable

– More flexibility, more efficiency

– Employed in most structured ASIC offerings

• Via Programmable

– Regular, easy to manufacture

– Metal is fixed and every segment may not be

fully utilizable,→ Can be Inefficient



Design Flows



Implementing Logic Circuits

HDL

Logic Synthesis

Floorplanning

Placement

Routing

Tape-out

Circuit Extraction

Pre-LayoutSimulation

Post-LayoutSimulation

Structural

Physical

BehavioralDesign Capture

D e s i g n I t e r a t i o n

EECE579 Digital Flow

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