EE451/551:Digital Control

Final Exam ReviewFall 2013

Exam Overview

• The Final Exam will consist of four/five questions for EE451/551 students based on Chapters 2‐7 and a bonus based on Chapters 8‐9 (students are free to work as many of the problems as they can).

• The example problems that follow are representative of what you will see on the exam…  

P.1: Relating Time and Frequency Domain Specifications

21

1 11. Time constant,

0.8 2.52. Rise time, , note: this is a linear approx.

1 0.73. Time delay, , note: this is a linear approx.

4. Percent overshoot, 100%

5. Peak time,

n

rn

dn

a

T

T

PO e

T

2% 5%4 36. Settling time, or

7. Steady-state error, ( ) See Chapter 3

pd

s sn n

ss

T T

e e

Design Example Relating Specifications•

•

2%

Design a closed loop system response that approx.

a second order system with peak time, 0.89s,

4and settling time 1.14 s. From the specs.,

we have the constraints:

1

pd

sn

n

T

T

2 2

2

2

( ) 2

40.89 and 1.14

Solving these eqns. simultaneously yields 5 and 0.707desired closed-loop poles are located at:

1 3.54 3.54

the CP is given by cl n n

n

n

cl n n d

s s s

s j j j

2 7.08 25.06s s

Controller Design Example #1•

1Given the plant: ( ) 1

design a lead cascade controller of the form:

( )

that places the desired closed-loop system poles at:

p

leadc

lead

G ss s

K s zG s

s p

2

3.54 3.54

( ) 7.08 25.06(see prior design example for related time-domain specs.)

cl

cl

s j

s s s

Controller Design Example #1•

•

•

It is clear from a basic RL plot of the plant that the desiredclosed poles cannot be achieved by gain alone and that theresulting loci must be biased to move further into the left-halfplane (see prior

example for RL plot of this plant)

Given these observations and the RL plot rules, it isreasonable to propose a lead compensator of the form:

1 ( )

7.08

This results in t

c

K sG s

s

he following Type 1 loop gain:

( )7.08

KL ss s

Controller Design Example #1•

•

3.54 3.54

3.54 3.54 3.54 3.54

The location of the controller pole should be obviousfrom the RL rules, but can be calculated from the AC as:

( )

7.08

The control

cl

cl cl

s j

leads j s j

lead

L s

s s p

p

3.54 3.54

3.54 3.54

ler gain can be calculated from the MC as:

( ) 1

1 25.06( )

cl

cl

s j

s j

K L s

KL s

Design Verification Using Coefficient Matching •

•

•

•

2

It has been shown that the desired closed-loop characteristicpolynominal (CP) is given by: ( ) 7.08 25.06Based on the proposed lead compensator form, we can calculatethe re

cl s s s

sulting loop gain as:

1( ) 1

If we select 1 as noted previously, this results in a closed-loop CP of the form (see prior controller topology analysis slide):

lead

lead lead

lead

K s z KL ss p s s s s p

z

2 ( )Comparing coefficients of the two CPs yields: 7.08 and 25.06

cl lead lead

lead

s s s p K s p s K

p K

Calculation of the Steady‐State Error •

•

•

0 0

The steady-state error to a unit step input is given by:1 lim ( )

1

where is the position error constant given by:

25.06 lim ( ) lim7.08

ss step t step p

p

p s s

e e tk

k

k L ss s

1 01

Note: this result is due to the pole at zero in the loop gain!

It can also be shown that is finite, yet non-zero

using the results of Chapter 3

ss stepp

ss ramp

ek

e

P.2: Sample Period Selection•

•

•

2

Based on the loop gain ( ) and the cascade control topology(see prior analysis), we have:

( ) 25.06 ( )( ) 7.08 25.06

which agrees with the prior design specifications develop

cllead

L s

Y s KH sR s s s p K s s

ed

We can use the ( ) associated with ( ) to selecte anappropriate sample rate for the related discrete time controller

2by noting from Chapter 3 that 50 100

Since the closed-loop 1

cl cl

d s d

d n

s H s

T

2 3.54, an appropriatesample period for the desired closed-loop system dynamics isgiven by the interval 0.02 0.04T

Converting Gc(s) to Gc(z)•

2 11 1100

1

If we select 0.02, we can use the inverse of the bilineartransform to calculate ( ) as shown:

25.06 1 23.64 23.17( ) ( )7.08 0.8678

Note: This transformati

c

c c zsT z zs

z

TG z

s zG z G ss z

on is commonly performed using aCAD package, like the c2d() command in Matlab, as shownin the scripts posted on the class web site that solve each of theChapter 5 controller examples in the lecture notes using Matlab

Discrete Controller Implementation•

1

1

1

The cascade controller is physically implemented in hardwarein the discrete time using the invere-z TF as shown:

( ) 23.64 23.17 23.64 23.17( )( ) 0.8678 1 0.8678

1 0.8678 ( ) 23.64 23.1

cU z z zG zE z z z

z U z

17 ( )

( ) 23.64 ( ) 23.17 ( 1) 0.8678 ( 1)where ( ) is the control signal and ( ) is the error defined: ( ) ( ) ( )

z E z

u k e k e k u ku k e k

e k r k y k

P.3: Design Example Relating Specifications•

•

2%

Design a closed loop system response that approx.

a second order system with peak time, 0.89s,

4and settling time 1.14 s. From the specs.,

we have the constraints:

1

pd

sn

n

T

T

2 2

2

2

( ) 2

40.89 and 1.14

Solving these eqns. simultaneously yields 5 and 0.707desired closed-loop poles are located at:

1 3.54 3.54

the CP is given by cl n n

n

n

cl n n d

s s s

s j j j

2 7.08 25.06s s

•

•

3.54 0.02

2

If the system is sampled with a period of 0.02,

then 0.9316 and3.54 0.02 0.0708 rad 4

This implies that the discrete CP is given by:

( )

T

1.8586 0.8680

nT

d

cl

T

r e eT

z z r z r z z

2 2 22

22 2 2

o check these results, solve for and :ln 0.9316ln 0.707

ln ln 0.9316 0.0708

1 1ln ln 0.9316 0.0708 50.02

n

n

rr

rT

Design Example Relating Specifications

Direct Digital Controller Design Example #3•

4

1Given the plant: ( ) sampled at 0.02,1 3

1.9475 10 0.9737( )

( 0.9802)( 0.9418)design a lead-lag cascade controller of the form:

( )

p

ZAS

lead lagc

lead

G s Ts s

zG z

z z

K z z z zG z

z p z

2

that places the desired closed-loop system poles at: 0.9316 and 0.0708

( )

0.9293 0.0659while producing zero steady-state error to a s

1.8585 0.8679

lag

cl

cl

p

rz z r z r

z j

z z

tep input.

Controller Design Example #3•

•

•

•

It is clear from a basic RL plot of the plant that the desiredclosed poles cannot be achieved by gain alone and that theresulting loci must be biased to move left into the unit circle(see prior exampl

e for RL plot of the plant ( ))

Given these observations and the RL plot rules, it isreasonable to propose a lead-lag compensator of the form:

( 0.9802) ( 0.9418) ( )1

T

ZAS

clead

G Z

K z zG zz z p

4his results in a Type 1 loop gain of the form:

1.9475 10 0.9737 ( )

1

Applying AC and MC to ( ): 0.8634 and 24.2990

lead

lead

K zL z

z z p

L z p K

P.4: Example of State Equation Soln.•

•

1

2

1

2

11

0 1

0 1

1 0 0

0

1

Given the system with unit step input and (0) [1,0] :

The state transition matrix ( )

can be computed as shown:

T

c n c

xx u

xx

y ux

x

t sI A

L

1

1 1

0

1 1

1 1 11( )

0 1 01

1

c

t

t

s es s st

s e

s

L L

Transfer Function Matrix•

•

Do these results agree with prior sta

Given the prior example, we can compue the system TF and IR as:

1 11 1

( ) 1 011

01

1 1( ) 1 0 ( ) 1

0

0( ) 01( )

00

1

tt

t

s s sH s

s s

se

t t ee

Y sU s

h

te soln., see Matlab verification?>> Ac=[0,1;0,‐1];Bc=[0;1];Cc=[1,0];Dc=[0];>> H_s=tf(ss(Ac,Bc,Cc,Dc))Transfer function:1

‐‐‐‐‐‐‐s^2 + s

>> zpk(H_s)zero/pole/gain:1

‐‐‐‐‐‐‐s (s+1)

Example Discrete State Eqn.•

•

•

0 0

1 1 1

0 0 1

1 1

0

Given the sampled data system with 0.1 and1

( ) , find the discrete state space representation1

As shown previously, ( ) ; therefore,

( )t

t

T

T

p

t

tc

TT

ce T T e

e e

e

e

T

G ss s

t

d

0.1

0 0.1

1 0.0952

0 0.905

0.1 0.00484 0 0.00484

0 0.0952 1 0.0952

Thus, ( ) and

( )

d c T

T

d c c

T

T

B d B

A

Discrete Transfer Function Matrix

•

11

1 0.1052 1.0021 1 1.1073 0.905

0 1.1050 0.905( )

1 0.0952Note: ( )

0 0.905

1 0.09521 1 0.905

1

00.905

k

d k

d n d

k k k kk

zz zI A

z

z z z

z

Discrete Transfer Function Matrix•

1 0.0952

0.004841 1 0.905( )( ) 1 0 0

1 0.0952( )0

0.905

0.004841 0.0952 0.00484 0.

0.09521 1 0.905

Given the prior example, we can compute the system TF and IR as:

z z zY zH z

U z

z

z

z z z

0.004841 0.1052 1.0021 1 1.1073 0.9051 0

0.09520 1.1050 0.905

0 ( )

9675

1 0.905

( )

0.1002 1( ) 0.1054 0.9050 0.0052 ( )k

k

k

k k k k

k

z z

h k

k k

P.5: Direct Controller Design By Synthesis•

•

•

It is often possible to design the controller z-TF directly fromthe given plant z-TF and the desired closed-loop z-TF as shown:

( ) ( )( )1 ( ) ( )

( )1( )( ) 1 ( )

This can le

c ZAScl

c ZAS

clc

ZAS cl

G z G zH zG z G z

H zG zG z H z

ad to some unique controller designs, only foundin the discrete domain such as Deadbeat Controllers thatdeliver finite settling time; the trick is to design controllersthat are implementable, e.g, are causal and stable!

This requires the proper selection of ( )clH z

Rules for Selecting Hcl(s)•

•

Use the following rules for selecting ( ) to ensure theresulting ( ) is implementable:1. ( ) must have the same pole-zero deficit as ( ) to ensure causality2. ( ) must contain as zero

cl

c

cl ZAS

cl

H zG z

H z G z

H z

s all of the zeros of ( ) that are outside the unit circle to ensure stability3. Zeros of 1 ( ) must include all of the poles of ( ) outside the unit circle to ensure stability4. (1)

ZAS

cl ZAS

cl

G z

H z G z

H

1 to ensure 0

Obviously, performance of the resulting controller ( ) relies on an accurate model of the plant ( )

ss step

c

ZAS

e

G zG z

Rules for Selecting Hcl(s)•

2

2 2

If all of the poles and zeros of ( ) are inside the unit circle;we can consider a desired analog prototype ( ) of the form:

( )2

which is mapped to

ZAS

cl

ncl

n n

cl

G zH s

H ss s

H

2

21 1 0

12

1 0

1 0

1

sin , 2 cos ,

( ) using as:

( )

where

and the gain is selected to ensure that (1) 11

n n nT T Tnd d

d

sT

cl

cl

e T e T e

z z eK zH z

z z

K H

K

Rules for Selecting Hcl(s)

•

21 1 0

21 0

12

1 1 0

0 0

1 2

1 ( )

( )1 ( )

Assuming the plant has the form ( )

with all poles/zeros inside the unit circle, by synthesis design:

1( )

cl

cl

cl

ZAS

cZA

z K zH z

z z

H z K zH z z K z

G z zG z

z p z p

G zG

1 1 2

20 0 1 1 0

12

1 0

( )( ) 1 ( )

( )( ) , as desired!1 ( )

cl

S cl

cl

K z z p z pG z z z K z

H zz H z

K zL zH zL z z z

Example Based on Ch5 Example #2 •

•

4

2

1Given the plant: ( ) sampled at 0.02,1 3

1.9475 10 0.9737( )

( 0.9802)( 0.9418)and a desired analog prototype ( ) of the form:

25 ( )7.071 25

The fo

p

ZAS

cl

cl

G s Ts s

zG z

z zH s

H ss s

llowing controller results from the synthesis designtechnique outlined above (see Ch6 Ex6.m):

47.8419 ( 0.9802)( 0.9418) ( )( 0.9737)( 1)( 0.8681)

_

cz z zG z

z z z

Bonus: