1

EE241 Spring 2010EE241 - Spring 2010Advanced Digital Integrated Circuits

Lecture 7: Variability

AnnouncementsHomework 1 posted, due Feb 18Project proposals due today

TitleHalf a pageFive (or more) references

2

2

OutlineLast lecture

Gate delaysStatic timing

This lectureIntroduction to variability

3

Design VariabilityDesign Variability

Sources and Impact on Design

3

5

Roadmap Acknowledges VariabilityInternational Technology Roadmap for Semiconductors2005 data

Node year 2007 2010 2013 2016 2019

DRAM ½ pitch [nm] 65 45 32 22 16

Total gate CD 3 [nm] 2.6 1.9 1.4 0.9 0.6

Lith h 3 [ ] 2 1 4 1 0 7 0 5

6

Lithography 3 [nm] 2 1.4 1 0.7 0.5

LER 3 [nm] 2 1.4 1 0.7 0.5

http://www.itrs.net/Common/2005ITRS/Home2005.htm

4

VariabilityNature of process variability

Within-die (WID), Die-to-die (D2D), Wafer-to-wafer (W2W), Lot-to-lot (L2L)Systematic vs randomSystematic vs. randomCorrelated vs. non-correlated

Spatial variability/correlationDevice parameters (CD, tox, …)Supply voltage, temperature

Temporal variability/correlation

7

Within-node scaling, Electromigration, Hot-electron effect, NBTI, self-heating, temperature, SOI history effect, supply voltage, crosstalk [Bernstein, IBM J. R&D, July/Sept 2006]

Known vs. unknown

Systematic and Random Device VariationsParameter Random Systematic

Channel Dopant Concentration Nch

Affects ϭVT [1] Non uniformity in the process ofdopant implantation, dosage, diffusion

G O S /S O & S O / S f fGate Oxide Thickness Tox

Si/SiO2 & SiO2/Poly-Si interface roughness[2]

Non uniformity in the process of oxide growth

Threshold Voltage VT(non Nch related)

Random anneal temperature and strain effects

Non-uniform annealing temperature[5](metal coverage over gate)Biaxial strain

Mobility μ Random strain distributions Systematic variation of strain in the Si due to STI, S/D area, contacts, gate density, etc

8

Gate Length L Line edge roughness (LER)[3] Lithography and etching:Proximity effects, orientation[4]

[1] D. Frank et al, VLSI Symposium, Jun. 1999 .[2] A. Asenov et al, IEEE Trans on Electron Devices, Jan. 2002.[3] P. Oldiges et al, SISPAD 2000, Sept. 2000.[4] M. Orshansky et al, IEEE Trans on CAD, May 2002.[5] Tuinhout et al, IEDM, Dec 1996

5

Sources of VariabilityTechnology

Front-end (Devices)Systematic and random variations in Ion, Ioff, C, …

Back-end (Interconnect)Systematic and random variations in R, C

EnvironmentSupply (IR drop, noise)

9

Temperature

Spatial Variability

Fab to fab Temperature

Global Local

Deployed environment

Lot to lot

Across wafer

Across reticle

Metal polishing

Transistor Ion, IoffLine-edge roughness

Dopant fluctuation

10

106 103 100 10-3 10-6 10-9

Across chipAcross block

After RohrerISSCC’06 tutorial

Film thickness

Spatial range [m]

6

Temporal Variability

Tech. node scaling Temperature

Technology Environment

Within-node scaling

Electromigration

NBTI

Hot carrier effect

Data stream

SOI history effectSelf heating

Supply noise

11

1012 103 100 10-3 10-6 10-12

Tooling changesLot-to-lot

After RohrerISSCC’06 tutorial

Coupling

Temporal range [s]10-9109 106

Charge

Systematic vs. Random VariationsSystematic

A systematic pattern can be traced down to lot-to-lot, wafer-to-f ithi ti l ithi di f l t t l twafer, within reticle, within die, from layout to layout,…

Within-die: usually spatially correlatedRandom

Random mismatch (dopant fluctuations, line edge roughness,…)Things that are systematic, but e.g. change with a very short time

t t (f t d thi b t it) O d ’t d t d it

12

constant (for us to do anything about it). Or we don’t unedrstand it well enough to model it as systematic. Or we don’t know it in advance (“How random is a coin toss?”).

Unknown

7

Corners

Within wafer

Within die

13

TypicalSlow Fast

Dealing with Systematic Variations

14Lin, DAC’06 tutorial

8

Systematic (?) Temporal VariabilityMetal 3 resistance over 3 months

15P. Habitz, DAC’06 tutorial

Chip Yield Depends on Inter-Gate Correlation

Variation remains constant with correlated gates, = 1

20%

d1 d2 dn

n stages

D D

1 / sqrt(n)0%

5%

10%

15%

0 2 4 6 8 10

/m

ean

of to

tal d

elay Variation is reduced with

non-correlated gates, = 0

16

Yield = Pr (sum of n delays < clock period) = 0 gives highest yield through averaging

0 2 4 6 8 10

Number of stages (n)

Non-correlated gates in a path reduce impact of variation

9

17

Chip Yield Depends on Inter-Path CorrelationMean delay increases as K increases for uncorrelated paths

D D

K u

ncor

rela

ted

path

s

Normalized Critical Path Delay

Nor

mal

ized

PD

F

0.8 0.9 1 1.1 1.20

K =1K =2K =10000

aP bP cPD D

a1 b2 c1D D

18Bowman et al, JSSC, Feb 2002 .

Yield = Pr (max delay of K paths < clock period) K = 1 results in highest yield

yMax delay of P paths

Correlated paths reduce impact of variation

10

Technology VariabilityLithographyDopantsLine edge roughnessFilm thicknessesNBTI

19

Optical Lithography: Variability Causes

i193 (immer.)=193nm

20

11

Lithography: Density EffectsIsolated

Dense Masks

Resist exposure thresholdLiso

Ldense

21

Denser features: More accurate line width and less variation. Dense lines are wider than isolated lines.

Brunner, ICP’2003

Lithography: OpticsDefocusLens aberrations:

Spherical aberrationsAstigmatismComa

22

Spherical aberrations - affect the reticle-level featuresStepper dependent

Coma affects individual featuresChip-location dependent

12

Lens Aberrations – Coma EffectComa effect: optical aberration due to lens imperfection.Causes mirrored structures to display non equivalent properties S t ti hift b t th 2 l t

Image of a circular dot shows a tail

Systematic shift between the 2 layouts

23

prints differently from

Step-and-Scan LithographySlit of light

Mask moved to the rightMask

Light sourceSlit direction:

Lens aberration in the slitCD’s more correlated to the right

Wafer moved to the left

slit

scan

Wafer

Optics

Scan direction:Dosage, scan speed and other fluctuationsCD’s less correlated

24

to the left

13

Lithography: FlareLight scattering and reflectionsMore stray light under dark features in the mask

Local flare depends on the density of chrome in the maskSurface

scattering

Resist exposure threshold

CD

Intensity

25

LensReflections With flare

No flare

Processing: Line-Edge Roughness

•Sources of line-edge roughness:• Fluctuations in the total dose due to quantization

26

• Fluctuations in the total dose due to quantization• Resist composition• Absorption positionsEffect:• Variation (random) in leakage and power

14

Random Dopant FluctuationsNumber of dopants is finite

27

Frank, IBM J R&D 2002

Random Dopant Fluctuations

Lg = 17nm, VDS = 0.7V Lg = 11nm, VDS = 0.7V

28VT = 23mV VT = 52mV

15

Oxide ThicknessSystematic variations +Roughness in the Si./SiO2 interfaceS ll ff t th RDFSmaller effect than RDF

29

Asenov, TED’2002

Negative Bias Temperature InstabilityPFET VTh’s shift in time, at high negative bias and elevated temperaturestemperaturesThe mechanism is thought to be the breaking of hydrogen-silicon bonds at the Si/SiO2 interface, creating surface traps and injecting positive hydrogen-related species into the oxide.

30

oxide.Also other charge trapping and hot-carrier defect generationSystematic + random shifts

Tsujikawa, IRPS’2003