EE2356 LAB Manuel 2014-15

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Ex. No:

Date :

STUDY OF 8085 MICROPROCESSOR.

AIM:

To study the architecture of 8085 Microprocessor.

MICROPROCESSOR ARCHITECTURE:

The Microprocessor is a programmable digital device designable with Register flip-flops

and timing elements. Data manipulation and communication is determined by the logic design

of the Microprocessor is called rchitecture.

MICROPROCESSOR UNIT:

The Microprocessor unit is designed as a group of device input of the function with

necessary set of control signals.

8085 MICROPROCESSOR:

The 8085 Microprocessor is an 8 bit general purpose Microprocessor! capable ofaddressing "# $% of memory. The chip has #0 pins and re&uired as '5 (. )t has a *ingle

processor supply and operates with + , single phase cloc.

8085 BUS ORGANIZATION:

The 8085 Microprocessor perform different operation using three sorts of

communication lines called %uses.

ADDRESS BUS:

The address bus is a group of /" lines! generally identify as 0-/5. The address bus is in

uni-direction. The bits following one direction from the Microprocessor unit to peripheral

devices or1 memory devices are called unidirectional

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DATA BUS:

The data bus is a group of 8 lines used to flow. These lines are bidirectional in which the

data flows in both the direction between the Microprocessor unit and the memory peripheral

devices. The Microprocessor unit uses this bus to transfer the binary information.

CONTROL BUS:

The control bus is compressed of various lines with carry synchroniation symbols. The

Microprocessor unit uses such lines to provide timing signals.

ACCUMULATOR:

This is an 8 bit register that is a part of 234 this register is used to store 8 bit data to

perform arithmetic and logical operation. This accumulator is identified as register .

FLAGS:

The 23 includes %67s that are set or reset according to the result of an operation. TheMicroprocessor unit uses this to test the data conditions. The 8085 flags indicate 5 different

types of results.

SIGN FLAG:

fter the eecution of an arithmetic and logical operation of a bit or if the result is 9/7!

the flag is used with signed numbers in the given byte.

ZERO FLAG:

The ero flag is set when the 23 operation byte results is ero and reset if the results is

not ero. The flag is modified by the result in accumulator.

PROGRAM STATUS ORD:

This is nothing but the combination of an accumulator and the flag registers. The

accumulator forms the higher bytes and the flag registers forms the lower bytes.

RESULT:

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Ex. No : !

Date :

A"#t$%et#& o'e"at#o() *)#(+ 8085

,8 -#t a#t#o(/8 -#t )*-t"a&t#o(/8 -#t %*t#'#&at#o(/8 -#t #1#)#o(2

AIM:

To write an assembly language program for adding! subtracting! multiplying : division

two 8 bit numbers using 8085 microprocessor it.

APPARATUS RE3UIRED:

S.No A''a"at*) Re4*#"e 3*a(t#t

/. 8085 Microprocessor it /;. ower supply -

ALGORITHM FOR 86BIT ADDITION:

/. *tart the program.

;. 2oad the first data in the accumulator.

+. Move the content of to % register.

#. 2oad the second data in the accumulator.

5. )nitialie the carry with ero.

". dd the content of % register to the accumulator.

then store the result in address which is specified.

8. )f the carry is =/> then increment the ? register and store the result.@. *top the program

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FLO CHART FOR 8 BIT ADDITION:

DATA CHEC7 MAP FOR 8 BIT ADDITION:

MEMORY ADDRESS

DATA !

,ITHOUT

CARRY2

DATA

,ITH

CARRY2

)A3T8;00,

8;0/,

05

0#

66

0+

B3T3T8+00,*3M1

8+0/,?RRC1

0@

00

0;

0/

MANUAL CALCULATION:

PROGRAM FOR 86BIT ADDITION:

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MEMORY LABEL MNEMONICS OPCODE COMMENTS

8500 *TRT 2D 8;00,850+ MB( %!850# 2D 8;0/,850< M() ?!00850@ DD %850 A? 2BB/850D )AR ?850E 2BB/ *T 8+00,85// MB( !?85/; *T 8+0/,85/5 *TB ,2T

FLO CHART FOR 8 BIT SUBTRACTION:

ALGORITHM FOR 8 BIT SUBTRACTION:

/. *tart the program.

;. 2oad the first data in the accumulator.

+. Move the content of to % register.#. 2oad the second data in the accumulator.

5. *ubtract the content of % register from the accumulator.

". )f the borrow is =0> then go to step

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MEMORY

ADDRESS

DATA !

,ITHOUT BORRO2

DATA

,ITH BORRO2

)A3T8;00,

8;0/,

B3T3T 8+00,

8+0/,MANUAL CALCULATION:

PROGRAM FOR 8 BIT SUBTRACTION:


8500 *TRT 2D 8;00,850+ MB( %!850# 2D 8;0/,850< M() ?!00850@ *3% %850 A? 2BB/850D )AR ?850E 2BB/ *T 8+00,85// MB( !?85/; *T 8+0/,85/5 *TB ,2T

FLO CHART FOR 8 BIT MULTIPLICATION:

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ALGORITHM FOR 86BIT MULTIPLICATION:

*tart the program.

2oad the first data into the accumulator.

Move the content of accumulator to the % register.

2oad the second data into the accumulator.

Move the content of accumulator to the ? register. Decrement the content of % register by one.

dd the ? register content with accumulator.

Decrement the content of % register : then repeat the steps < : 8.

Else store the result in the memory location mentioned.

*top the program.

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DATA CHEC7 MAP FOR 8 BIT MULTIPLICATION:

MEMORY

LOCATION

DATA! DATA

)A3T 8;00,

8;0/,

B3T3T 8+00,Reminder1

8+0/,Fuotient1

MANUAL CALCULATION:

PROGRAM FOR 8 BIT MULTIPLICATION:


8500 *TRT 2D 8;00,850+ MB( D!850# 2D 8;0/,

850< MB( %!8508 D?R D850@ M() ?!00850% L DD %850? A? 85/0 ,L!28506 )AR ?85/0 L! D?R D85// AG 850% ,L285/# *T 8+0085/< MB( !?85/8 *T 8+0/

85/% ,2T

FLO CHART FOR 8 BIT DI9ISION:

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ALGORITHM FOR 8 BIT DI9ISION:

*tart the program.

2oad the first data in the accumulator.

Move the content from memory address to register and increment the ,2 pair.

Move the content from memory address to % register : initialie the ? register.

?ompare the 8 bit instructions in and % registers. *ubtract % register from

accumulator : increment the value in ? register.

)ncrement the ,2 pair and move the content in accumulator to memory.

*top the program.

DATA CHEC7 MAP FOR 8 BIT DI9ISION:

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MEMORY

LOCATION

DATA! DATA

)A3T 8;00,

8;0/,

B3T3T 8+0/Reminder1

8+0;Fuotient1

MANUAL CALCULATION:

PROGRAM FOR 8 BIT DI9ISION:


8500 *TRT 2D 8;00850+ MB( D!850# 2D @;0/850< M() ?!00850@ 2/ *3% D850 )AR ?

850% ?M D850? A? 850@2/18506 *T 8+0085/; MB( !?85/+ *T @+0/85/" ,2T

RESULT:

Ex (o:

Date:

PROGRAM ITH 80856ASCENDING AND DESCENDING ORDER

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AIM:

To write an assembly language program for the ascending and descending order of 8-bit

numbers using 8085 microprocessor it.

APPRATUS RE3UIRED:

S.NO NAME OF ITEMS 3UANTITY

/.

;.

8085-Microprocessor it

ower supply

/

ALGORITHM: ,ASCENDING ORDER2

/. Het the numbers to be sorted from the memory locations.;. ?ompare the first two numbers and if the first number is larger than second then

interchange the number.

+. )f the first number is smaller! go to step #.

#. Repeat steps ; and + until the numbers are in re&uired order.

RESULT OF ASCENDING ORDER :

MEMBRC2B?T)BA

)A3T 8/00-!58/0/-058/0;-58/0+-!08/0#-0

B3T3T 8/00-058/0/-!08/0;-!5

8/0+-08/0#-5MODEL CALCULATION

PROGRAM: ,ASCENDING ORDER2

ADD

RESSOPCODE LABEL MNEMONICS COMMENTS

8000 M() %!0# ?omparison of A-/ Aumbers5Aos1800; 2BB + 2I) ,!8/008005 M() ?!0#

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800< 2BB; MB( !M8008 )AI ,800@ ?M M800 C LOOP!,80!2800D MB( D!M

800E MB( M!

8006 D?I ,

80/0 MB( M!D80// )AI ,

80/; 2BB/ D?R ?

80/+ AG 2BB;800

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Aumbers5Aos1800; 2BB+ 2I) ,!8/008005 M() ?!0#800< 2BB; MB( !M8008 )AI ,

800@ ?M M800 NC LOOP!,80!2800D MB( D!M

800E MB( M!

8006 D?I ,

80/0 MB( M!D80// )AI ,

80/; 2BB/ D?R ?

80/+ AG 2BB;800

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To write an assembly language program to search the minimum and maimum number

in a group of data using 8085 microprocessor it.

APPRATUS RE3UIRED:

S.NO NAME OF ITEMS 3UANTITY

/.

;.

8085-Microprocessor it

ower supply

/

ALGORITHM :, SEARCH THE MINIMUM NUMBER2

1. Place all the elements of an array in the consecutive memory locations.

2. Fetch the rst element from the memory location and load it in theaccumulator.3. Initialize a counter (register) with the total numer of elements in anarray.!. "ecrement the counter y 1.#. Increment the memory $ointer to $oint to the ne%t element.&. 'om$are the accumulator content with the memory content (ne%telement).. If the accumulator content is smaller then move the memory content(largest

element) to the accumulator. *lse continue.

+. "ecrement the counter y 1.,. -e$eat ste$s # to + until the counter reaches zero1. /tore the result (accumulator content) in the s$ecied memory location.

-*/0 F /*4-'5 5* 6I7I606 7068*-9

MEMBRC2B?T)BA

DT/ DT ;

)A3T 8/008/0/

8/0;8/0+8/0#

;5/0

05+0/5

;%56

#D+?/

B3T3T 8;00 05 !A

MODEL CALCULATION:

PROGRAM: ,SEARCH THE MINIMUM NUMBER26SMALLEST NUMBER

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ADDRESS OPCODE LABEL MNEMONICS COMMENTS

8000 2I) ,!8/00,800+ MB( %!05 ?omparison of 5 Aos8005 DE? %

800" MB( !M800< 2BB/ )AI ,

8008 ?M M800@ C AHEAD,800D2800? MB( !M800D ,ED D?R %

800E AG 2BB/800

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PROGRAM: ,SEARCH THE MA

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To rotate and eecute an assembly language program to perform instruction.

RT3* REF3)REDJ

/. 8085 it;. ower chord

2HBR)T,MJ

rogram using R2?J

/. *tart the program;. 2oad the input and add them+. Then the input values are rotated using R2?#. *top the program

rogram using RR?J

/. *tart the program;. 2oad the input and add them+. Aow the input is rotated using RR?#. *top the program

rogram using R2J

/. *tart the program;. 2oad the input and add them+. Then the input is rotated using rotate accumulator left through carry#. *top the program

rogram using RRJ

/. *tart the program;. 2oad the input data and add them+. Then the input is rotated using rotate the accumulator right through carry#. *top the program

RBHRM 3*)AH R2?J

6emory

address

6nemonics $code 'omments

+1 :I 5+#+13 6; 48+1! I7: 5+1# 4"" 6+1& -'+1 /4 +&+14 5

rogram using RR?J

6emory 6nemonics $code 'omments

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address+1 :I 5+#+13 6; 46+1! I7: 5+1# 4"" 6+1& --'+1 /4 +&+14 5

rogram using R2J

6emory4ddress


+1 :I 5+#+13 6; 46+1! I7: 5+1# 4"" 6+1& -4

+1 /4 +&+14 5

RBHRM 3*)AH RRJ

6emory4ddress


+1 :I 5+#+13 6; 46+1! I7: 5+1# 4"" 6+1& -4-+1 /4 +&+14 5

R2?J

I7P0 0P06emoryaddress

"ata 6emoryaddress

data

RR?J


data 6emoryaddress

data

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R2J


data 6emoryaddress

data

RRJ


data 6emoryaddress

data

RESULT:

E

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Memoryaddress

2abel Mnemonics Bpcode ?omments

8/00 2D 8;008/0+ *3) +0

8/05 ?) 08/0< ? 2BB8/0 *3) 0

DATE:

AIM:

To study the operation of the 8 channel selection and analog to digital converter details.

APPARATUS RE3UIRED:

/. 8 channel D? trainer it /;. ?RB /

+. atch chords as Re&

PROCEDURE:

/. ?onnect the ;"pin 6R? to it and insert power cable.

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;. *witch BA the trainer it.

+. ?hec all 8 channel input7s and measure it.

#. Enter the given D? program into the MKM? it.

5. )f the channel selection is pb; to pb0 L0 0 0 the ?,0 will connect to the M3I output

line. Aow we get to ?,0 corresponding digital value see in 2?D. *imilarly ?,0 to

?,

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?alculate voltage vs digital count.

LEJg

;500mvK/@mv O /+/.5

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ADC INTERFACE

RESULT:

Ex.No : ?

Date :

INTERFACING 8?@ ITH 8085 MICROPROCESSOR

,$EC%BRD AD D)*2C )ATER6?E2

AIM:

To write an assembly language rogram to interface eyboard.

APPARATUS RE3UIRED:

S.No APPARATUS 3UANTITY

/. 8085 Microprocessor it /;. ower supply /+. )nterface it /

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7EYBOARD PROGRAME FOR 8085:

@000 +E /; M() ! /;

@00; +; 0/ "0 *T "00/

@005 +E +E M() ! +E

@00< +; 0/ "0 *T "00/

@00 +E 0 M() ! 0

@00? +; 0/ "/ *T "00/

@006 0" 08 M() %! 08

@0// +E 00 loopJ M() ! 00

@0/+ +; 00 "0 *T "000

@0/" 05 D?R %

@0/< ?; // @0 AG loop

@0/ + 0/ "0 2/J2D "00/

@0/D E" 0< A) 0 allowing the flip-flop to toggle on every cloc pulse. Then the synchronouscounter follows a predetermined se&uence of states in response to the common cloc signal!advancing one state for each pulse.

The and $ inputs of flip-flop 66% are connected directly to the output Fof flip-flop 66!but the and $ inputs of flip-flops 66? and 66D are driven from separate AD gates whichare also supplied with signals from the input and output of the previous stage. Theseadditional AD gates generate the re&uired logic for the $ inputs of the net stage.

)f we enable each $ flip-flop to toggle based on whether or not all preceding flip-flopoutputs F1 are =,)H,> we can obtain the same counting se&uence as with the asynchronouscircuit but without the ripple effect! since each flip-flop in this circuit will be cloced ateactly the same time.

Then as there is no inherent propagation delay in synchronous counters! because all thecounter stages are triggered in parallel at the same time! the maimum operating fre&uency of
http://www.electronics-tutorials.ws/sequential/seq_2.htmlhttp://www.electronics-tutorials.ws/sequential/seq_2.html

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this type of fre&uency counter is much higher than that for a similar asynchronous countercircuit.

6-#t S(&$"o(o*) Co*(te" a1eo"% T#%#(+ D#a+"a%.

%ecause this #-bit synchronous counter counts se&uentially on every cloc pulse the resultingoutputs count upwards from 0 0000 1 to /5 //// 1. Therefore! this type of counter is alsonown as a 6-#t S(&$"o(o*) U' Co*(te".

,owever! we can easily construct a 6-#t S(&$"o(o*) Do( Co*(te"by connecting theAD gates to the F output of the flip-flops as shown to produce a waveform timing diagramthe reverse of the above. ,ere the counter starts with all of its outputs ,)H, //// 1 and itcounts down on the application of each cloc pulse to ero! 0000 1 before repeating again.

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DESIGN O* S+I*T REGISTER

,)i$ D)t) Moeme"t T'rou#' A S'it Re#iter

?loc ulse Ao F F% F? FD

0 0 0 0 0

/ / 0 0 0

; 0 / 0 0

+ 0 0 / 0

# 0 0 0 /

5 0 0 0 0

Aote that after the fourth cloc pulse has ended the #-bits of data 0-0-0-/ 1 are stored in theregister and will remain there provided clocing of the register has stopped. )n practice theinput data to the register may consist of various combinations of logic =/> and =0>.?ommonly available *)B )?7s include the standard 8-bit

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1. Serial-in to Serial-out (SISO) Shift Register

This )$#t "e+#)te"is very similar to the *)B above! ecept were before the data was readdirectly in a parallel form from the outputs Fto FD! this time the data is allowed to flowstraight through the register and out of the other end. *ince there is only one output! theDT leaves the shift register one bit at a time in a serial pattern! hence the name Se"#a6#(to Se"#a6O*t S$#t Re+#)te"or SISO.

The *)*B shift register is one of the simplest of the four configurations as it has only threeconnections! the serial input *)1 which determines what enters the left hand flip-flop! theserial output *B1 which is taen from the output of the right hand flip-flop and these&uencing cloc signal ?l1. The logic circuit diagram below shows a generalied serial-inserial-out shift register.

/-bit Seri)0-i" to Seri)0-out S'it Re#iter

Cou may thin what7s the point of a *)*B shift register if the output data is eactly the sameas the input data. Pell this type of S$#t Re+#)te"also acts as a temporary storage device oras a time delay device for the data! with the amount of time delay being controlled by thenumber of stages in the register! #! 8! /" etc or by varying the application of the cloc pulses.?ommonly available )?7s include the

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/-bit P)r)00e0-i" to Seri)0-out S'it Re#iter

s this type of shift register converts parallel data! such as an 8-bit data word into serial

format! it can be used to multiple many different input lines into a single serial DT streamwhich can be sent directly to a computer or transmitted over a communications line.?ommonly available )?7s include the

EE2356 LAB Manuel 2014-15

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