EE201: Digital Circuits and Systems Programmable Logic Devices
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EE201: Digital Circuits and Systems 5 Digital Circuitry page 1 of 17 EE201: Digital Circuits and Systems Section 6 – Memory Programmable Logic Devices http://www.educypedia.be/electronics/digitalprog.htm http://www.powershow.com/view/140a81-MTlkM/Programmable_Logic Can implement logic by a number of methods: • SSI (Discrete Gates) – Need lots of ICs • MSI (Logic Functions) – needs fewer ICs but still difficult to minimise • PLDs – Single device usually. o More reliable, difficult to copy • Gate Array – More expensive than PLDs but higher performance and more options o More flexible • ASIC (Application Specific IC) o Standard Cells – higher initial costs o Custom Logic – highest initial costs o ASIC requires high volume to make worthwhile o Long turnaround
Transcript of EE201: Digital Circuits and Systems Programmable Logic Devices
EE201: Digital Circuits and Systems 5 Digital Circuitry page 1 of 17
EE201: Digital Circuits and Systems
Section 6 – Memory
Programmable Logic Devices http://www.educypedia.be/electronics/digitalprog.htm http://www.powershow.com/view/140a81-MTlkM/Programmable_Logic
Can implement logic by a number of methods:
• SSI (Discrete Gates) – Need lots of ICs • MSI (Logic Functions) – needs fewer ICs but still
difficult to minimise • PLDs – Single device usually.
o More reliable, difficult to copy • Gate Array – More expensive than PLDs but higher
performance and more options o More flexible
• ASIC (Application Specific IC) o Standard Cells – higher initial costs o Custom Logic – highest initial costs o ASIC requires high volume to make worthwhile o Long turnaround
EE201: Digital Circuits and Systems 5 Digital Circuitry page 2 of 17
PROM
Programmable OR array
Fixed
AND
array
A4
A3
A2
A1
A0
31
30
1
0
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Blow fuses on all non required connections
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PROM Design Example: BCD to Gray Code Converter Connect address [A3 – A0] to inputs [A, B, C, D] & data o/ps to [W, X, Y, Z]
Without PROM, this decoder would need several ICs. PROM is well suited to those apps where every possible input combination (AND term) is needed, eg. Code converters, data storage. Drawbacks: Each new i/p needs no. of Memory cells to be doubled No of i/ps & o/ps fixed As memory size increases, so do cost, power, delay. PLA or PAL may be more flexible & cost effective.
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
W 0 0 0 0 0 1 1 1 1 1 X X X X X X
X 0 0 0 0 1 1 0 0 0 0 X X X X X X
Y 0 0 1 1 1 1 1 1 0 0 X X X X X X
Z 0 1 1 0 0 0 0 1 1 0 X X X X X X
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PLA – Programmable AND and OR arrays
Inputs
Outputs
Prog.AND-array
Prog.OR-array
..
..
..
..
..
..
..
..
..
..
..
..
.. .. .. .. .. ..
.. .. .. .. .. ..
Only subset of possible AND terms provided. Each AND gate has connections to each i/p. By leaving appropriate fuse intact, any i/p or its complement can be present in any AND term.
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PLA Eg
Unwanted connections are "blown"
Equations
Programming
1 = asserted in term 0 = negated in term - = does not participate
1 = term connected to output 0 = no connection to output
Input Side:
Output Side:
Outputs Inputs Product t erm
Reuse of
t erms
A 1 - 1 - 1
B 1 0 - 0 -
C - 1 0 0 -
F 0 0 0 0 1 1
F 1 1 0 1 0 0
F 2 1 0 0 1 0
F 3 0 1 0 0 1
A B B C A C B C A
F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A
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Alternative representation for PLAs Short-hand notation so we don't have to draw all the wires!
Notation for implementing F0 = A B + A' B' F1 = C D' + C' D
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Another PLA Example: Magnitude Comparator
EQ NE LT GT
ABCD
ABCD
ABCD
ABCD
AC
AC
BD
BD
ABD
BCD
ABC
BCD
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
K-map for EQ
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 1 1
1 0 1 1
1 1 0 1
1 1 1 0
K-map for NE
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 0 0 0
1 0 0 0
1 1 0 1
1 1 0 0
K-map for L T
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 1 1
0 0 1 1
0 0 0 0
0 0 1 0
K-map for GT
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PAL has programmable AND-array, but fixed OR-array.
A given column of the OR array has access to only a subset of the possible product terms
PALs simpler to understand and use than PLAs and have performance advantages: a fuse array has high capacitance which causes delay. Reducing no. of AND terms reduces cost and power consumption. First PALs suffered from restrictions of fixed i/p and o/p nos. And fixed o/p polarity.
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PAL
TruthTable K-maps
W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D'
Minimized Functions:
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
W 0 0 0 0 0 1 1 1 1 1 X X X X X X
X 0 0 0 0 1 1 0 0 0 0 X X X X X X
Y 0 0 1 1 1 1 1 1 0 0 X X X X X X
Z 0 1 1 0 0 0 0 1 1 0 X X X X X X
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
K-map for W
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
K-map for X
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
K-map for Y
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
K-map for Z
Programmed PAL:
4 product terms per each OR gate
Design Example: BCD to Gray Code Converter
A B C D
0
0 0 0
0 0
A B C D
A BD
BC
BC
B
C
BCD
AD
BCD
W X Y Z
EE201: Digital Circuits and Systems 5 Digital Circuitry page 10 of 17
PROM
Not unlike a PLA structure with a fully decoded
AND array!
ROM vs. PLA: ROM approach advantageous when (1) design time is short (no need to minimize output functions) (2) most input combinations are needed (e.g., code converters) (3) little sharing of product terms among out put functions ROM problem: size doubles for each additional input , can't use don't cares PLA approach advantangeous when (1) design tool like espresso is available (2) there are relatively few unique minterm c ombinations (3) many minterms are shared among the output functions PAL problem: constrained fan-ins on OR planes
Memory array
2 n words by m bits
m output lines
n address lines
Decoder 2 n word lines
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Registered (Sequential) PAL:
16R4 PAL:
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22V10
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22v10 o/p macrocell
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Complex PLD
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Xilinx XC3020:
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X3000 series Configurable Logic Block
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FPGA Design:
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