GROUP 5

PROJECT REPORT ON

DESIGNING A MULTIPLEXER TO MEASURE AN ARRAY OF FETS

EE-584INTRODUCTION TO VLSI DESIGN AND TESTING

INSTRUCTOR: DR ELIAS

NAVEEN VELICHETI

RAMA KRISHNA NIMMAGADDA

RAKESH KANDIBANDA

SRI HARSHA YENUGANTI

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TABLE OF CONTENTS

1. OBJECTIVE ............................................................................................................. 22. BLOCK DIAGRAM ................................................................................................... 2

Fig 2.1: Block diagram of the MUX used to select an array of FETs................................................... 23. MOSFET CURRENT DEPENDENCE ON W/L.......................................................... 34. MULTIPLEXER INTRODUCTION.............................................................................. 3

Fig 4.1: Block diagram of a MUX ........................................................................................................ 3Fig 4.2: 2X1 MUX using Transmission Gates ...................................................................................... 4Table 4.1: Truth table of a 2X1MUX .................................................................................................... 5Fig 4.3: Schematic of a 2X1 MUX using Transmission gates............................................................... 5

5. CASCADING OF MULTIPLEXERS............................................................................. 5Fig 5.1: 4X1 MUX constructed from 3 2X1 MUX................................................................................. 6Fig 5.2: 16X1 constructed using 5 4X1 MUX ....................................................................................... 7

6. DESIGNING A 2X1 TRI-STATE OUTPUT MUX....................................................... 8Table 6.1: Truth table for a Tri-State Output MUX.............................................................................. 8Fig 6.1: 4X1 MUX realized from 2 2X1 MUX ...................................................................................... 8Fig 6.2: Circuit to create high impedance state in the MUX ................................................................ 9Fig 6.3: Schematic of a 2X1 Tri-state output MUX ............................................................................ 10Fig 6.4: Schematic of a 4X1 MUX using 2 2X1 Tri-State output MUX .............................................. 11Fig 6.4: Symbol created for a 4X1 MUX ............................................................................................ 12Table 6.2: Comparison of MUX performance with and with out Tri-State logic................................ 13Fig 6.5: Comparison of MUX performance with and with out Tri-State logic ................................... 13

7. SCHEMATIC AND SIMULATIONS .......................................................................... 14Fig 7.1: Circuit used to find current mismatch ................................................................................... 15

TABLE 7.1: % ERROR FOR DIFFERENT W/LS.............................................................. 17FIG 7.2: % ERROR FOR DIFFERENT W/LS................................................................... 17

Fig 7.3: Output current from the individual FETs.............................................................................. 18Fig 7.4: Output current measured at the MUX output........................................................................ 18Fig 7.5: Comparison of Output - individual FETs and MUX ............................................................. 19

8. LAYOUT ................................................................................................................ 19FIG 8.1: TRANSMISSION GATE WITH FOLDED TRANSISTORS....................................... 20FIG 8.2: LAYOUT OF A 4X1 MUX................................................................................ 219. CORNER ANALYSIS............................................................................................... 2210. CONCLUSION .................................................................................................... 23

Table 10.1: User Table to select the FETs.......................................................................................... 23REFERENCES................................................................................................................. 23

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1. ObjectiveThe objective of the project is to design a Multiplexer to select a FET from an

array of FETs. Each of the FET to be selected will have different W/L ratio. The output from the Multiplexer should ideally be the same as the output would be when the FET was directly connected.

In other words, the project is to design a MOS transistor with user selectableW/L’s. This selection is made using a Multiplexer with the provided select pins.

2. Block Diagram

Fig 2.1: Block diagram of the MUX used to select an array of FETs

Source, Gate and Drain pins are provided to the output along with the select lines to select the desired FET. Bulk of the FETs is connected internally to the required potential level, such that no I/O pin is required for the bulk.

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3. MOSFET Current dependence on W/L

For a P-channel MOSFET operated in triode or ohmic region the current flowing through the device is given by the equation,

2)(.

2DS

DSTHNGSnD

VVVV

L

WKPI for VGS ≥ VTHN and VDS≤VGS-VTHN

[1]

For a MOSFET operated in saturation region, the current flowing through is given by the equation,

2.2 THNGS

nD VV

L

WKPI for VDS ≥ VGS-VTHN and VGS ≥ VTHN

From both the equations it can be concluded that the current flowing through a MOSFET is directly proportional to the Width to Length ratio of the MOSFET.

L

WI D

So as different FETs are selected using the multiplexer, the current flowing from each of the FTEs will be different. The Multiplexer designed for this purpose should offer minimum load, such that ideally the same current can be observed at the output of the MUX.

4. Multiplexer Introduction

Multiplexer is a circuit which makes the output equal to one of the inputs based on the select lines.

Fig 4.1: Block diagram of a MUX

Control/select linesm

MUX Out

NData Lines

4

The number of control lines is related to the number of inputs by,N = 2m

Where, N number of inputs that can be selected m number of select lines

Two transmissions gates can be used to construct a 2X1 MUX as shown in the Fig 4.2

Fig 4.2: 2X1 MUX using Transmission Gates

Dout

S

S

A

B

S

5

S Dout0 B1 A

Table 4.1: Truth table of a 2X1MUX

Fig 4.3: Schematic of a 2X1 MUX using Transmission gates

5. Cascading of MultiplexersA 4x1 MUX can be realized by cascading three 2X1 Multiplexers as shown in the

Fig 5.1.

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Fig 5.1: 4X1 MUX constructed from 3 2X1 MUX

So, inputs to a 4X1 MUX has 2 transmission gates as load.

Similarly a 16X1 MUX can be realized by cascading 5 4X1 MUX as shown in the Fig. 5.2. A 16X1 MUX offers a load of 4 transmission gates to its inputs.

Do

D1

D2

D3

S0

S0Dout

S1

7

Fig 5.2: 16X1 constructed using 5 4X1 MUX

D0D1D2D3

D4D5D6D7

D8D9D10D11

D12D13D14D15

4:1MUX

4:1MUX

4:1MUX

4:1MUX

S0S1

S0S1

S0S1

S0S1

Out4:1MUX

S3 S4

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6. Designing a 2X1 TRI-State output MUX

A Tri-State MUX is one which along with driving the data (either 0 or 1) to the output can also result high impedance state. The following is the truth table of a 2X1 Tri-State output MUX.

S1 S0 Dout0 0 D00 1 D11 0 X1 1 X

Table 6.1: Truth table for a Tri-State Output MUX

By selecting S1 = 0 the MUX sends out either D0 or D1 to the output depending on S0, where as if S1=1 the MUX results in an high impedance state.

By using two 2X1 Tri-State MUX, a 4X1 MUX can be realized by wired ANDing each of the output as shown in the fig.

Fig 6.1: 4X1 MUX realized from 2 2X1 MUX

Do

D1

D2

D3

So S1

S0 S1 Dout

9

The circuit implementing the Tri-State MUX is shown in the Fig. 6.2. When S1=0 the transmission gate T is ON and the pass gate P is OFF, resulting in normal operation. And when S1=1, the gate T is OFF and P is ON, resulting in a high impedance state. For a 2X1 MUX 4 similar circuits are required to drive the MUX into high impedance state.

Fig 6.2: Circuit to create high impedance state in the MUX

The advantage of using the Tri-State configured MUX is that the number of transmission gates that loads the inputs of the MUX can be reduced drastically by removing the unwanted gates from the picture by driving them to high impedance state.But this is achieved at the cost of increased complexity of the circuit .

When the circuit shown in fig.5.2. is used, the number of transmission gates in the load of the inputs of the multiplexer reduces to 2 with tri-state logic when compared to 4 incase of normal transmission gate logic. This is achieved by driving the other transistors that are not in the path of the desired input to output into high impedance state.

TS1

Vdd

P

Din Dout

S0

S1

10

Fig 6.3: Schematic of a 2X1 Tri-state output MUX

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Fig 6.4: Schematic of a 4X1 MUX using 2 2X1 Tri-State output MUX

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A symbol is created from the schematic such that it can be directly instantiated to use in the later part of the project. Fig 6.5 shows the symbol created for a 4X1 MUX using a Tri-state 2X1 output MUX.

Fig 6.4: Symbol created for a 4X1 MUX

A 16X1 MUX is designed using both the tri-State logic and normal cascaded logic, and the results observed are tabulated as follows:

Output at MUX with tri-State logic

Output at MUX without tri-state logic

W/L of Input FETS

Currents at the outputs of

Individual FETs (uA)

Current (uA)% error

ΔI / ICurrent (uA)

% errorΔI / I

1.05/0.5 12.26 12.25 0.08 12.24 0.165/1 20.7 20.69 0.05 20.68 0.1010/1 43 42.97 0.07 42.93 0.1615/1 65.36 65.3 0.09 65.22 0.2120/1 87.73 87.64 0.10 87.4 0.3825/1 110.1 109.9 0.18 109.6 0.4530/1 132.5 132.2 0.23 131.7 0.6040/1 177.3 176.8 0.28 175.8 0.8550/1 222 221.2 0.36 219.5 1.13

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60/1 266.8 265.1 0.64 263.3 1.3180/1 356.3 353.2 0.87 349 2.05100/1 445.9 440.4 1.23 432.9 2.92120/1 535.4 526.9 1.59 507.7 5.17140/1 625 611.6 2.14 559.3 10.51170/1 759.3 729.5 3.92 647.9 14.67200/1 893.6 821.1 8.11 753.3 15.70

Table 6.2: Comparison of MUX performance with and with out Tri-State logic

It can be clearly observed that the percentage error in the output current has reduced considerably when tri-state logic is used than without tri-state logic. The percentage error has reduced to almost half with the new circuit, a considerable increase in the output currents. In this case the output currents almost equaled the currents from FET’s with less than 5% error for most of the cases. The plot of the percentage error with varying W/L in both the cases is given in Fig 6.5.

Fig 6.5: Comparison of MUX performance with and with out Tri-State logic

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7. Schematic And Simulations

A 16X1 MUX is created using 5 4X1 MUX as shown in the Fig 7.1, different FETs of varying W/L are connected as the inputs to the MUX, and the current flowng at the output of the MUX is measured.

The aim of the project is to drive the current from the FET with selected W/L to the output of the multiplexer. But here the multiplexer is in the load of the transistors .Multiplexer provides a path from the VDD to ground through the selected transistor. In this process the output from the transistor must not be degraded due to the presence of the MUX in the load. We must select the W/L of the transistors in the MUX so that the currents from the transistors without load must be equal to that with load . To verify this the following circuit is taken. The elements on the left are individual transistors with no load and connected to supply and ground. All the transistors are driven with the same input. But due to different W/L’s of the transistors the output current varies proportionally. The circuit on the right is with multiplexer in the load of the transistors.

15

Fig 7.1: Circuit used to find current mismatch

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For different W/L of the transistors in the MUX the output currents are noticed. The percentage mismatch in the output current for different W/L ratios in the MUX is given in the Table 7.1.

Output at 16X1 MUX (240/0.5)Using Tri-State 2X1W/L of individual

FETSIndividual FET Current (uA)

Current (uA) % error1.05/0.5 12.26 12.25 0.08

5/1 20.7 20.69 0.0510/1 43 42.97 0.0715/1 65.36 65.3 0.0920/1 87.73 87.64 0.1025/1 110.1 109.9 0.1830/1 132.5 132.2 0.2340/1 177.3 176.8 0.2850/1 222 221.2 0.3660/1 266.8 265.1 0.6480/1 356.3 353.2 0.87

100/1 445.9 440.4 1.23120/1 535.4 526.9 1.59140/1 625 611.6 2.14170/1 759.3 729.5 3.92200/1 893.6 821.1 8.11

Output at 16X1 MUX (200/0.5)Using Tri-State 2X1

Output at 16X1 MUX (170/0.5)Using Tri-State 2X1

W/L of individual

FETS Current (uA) % errorCurrent

(uA)% error

1.05/0.5 12.25 0.08 12.25 0.085/1 20.67 0.14 20.66 0.1910/1 42.91 0.21 42.89 0.2615/1 65.2 0.24 65.18 0.2820/1 87.42 0.35 87.41 0.3625/1 109.7 0.36 109.6 0.4530/1 132 0.38 131.8 0.5340/1 176.3 0.56 176.1 0.6850/1 220.5 0.68 220.3 0.7760/1 264.6 0.82 264.1 1.0180/1 352.1 1.18 351.1 1.46

100/1 438.6 1.64 436.3 2.15120/1 523.6 2.20 514.7 3.87140/1 601.4 3.78 576.5 7.76170/1 692 8.86 656.6 13.53200/1 772.7 13.53 751.9 15.86

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Output at 16X1 MUX (140/0.5)Using Tri-State 2X1

Output at 16X1 MUX (100/0.5)Using Tri-State 2X1

W/L of individual

FETS Current (uA) % error Current (uA) % error1.05/0.5 12.24 0.16 12.24 0.16

5/1 20.64 0.29 20.63 0.3410/1 42.87 0.30 42.85 0.3515/1 65.14 0.34 65.11 0.3820/1 87.37 0.41 87.3 0.4925/1 109.5 0.54 109.3 0.7330/1 131.7 0.60 131.5 0.7540/1 175.9 0.79 175.2 1.1850/1 219.8 0.99 218.7 1.4960/1 263.3 1.31 261 2.1780/1 348.9 2.08 333.1 6.51100/1 427.8 4.06 386.7 13.28120/1 487.8 8.89 450.7 15.82140/1 540.9 13.46 510.3 18.35170/1 637.1 16.09 588.4 22.51200/1 724.6 18.91 662 25.92

Table 7.1: % Error for different W/Ls

Fig 7.2: % Error for different W/Ls

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At a W/L of 240/0.5 a reasonable match of both the outputs is observed. So the the transmission gates attached to the inputs are selected to have a W/L of 240/0.5.

Fig 7.3: Output current from the individual FETs

Fig 7.4: Output current measured at the MUX output

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Fig 7.5: Comparison of Output - individual FETs and MUX

8. Layout

A folded transistor of width 10 and 24 fingers is used to draw the layout of the NMOS and PMOS transistors in the transmission gates, Thus each has an W/L of 240/0.5. Fig 8.1 shows the layout of the transmission gate.

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Fig 8.1: Transmission gate with folded transistors

Using these transmission gate a 4X1 Multiplexer is drawn whose layout is shown below. This layout uses 4 transmission gates of each W/L = 240/0.5. The 4X1 transistor intern has two Tri-State output 2X1 MUX.

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Fig 8.2: Layout of a 4X1 MUX

The layout of the final 16X1 MUX using the 4X1 MUX is to be routed in the bounding with proper I/O connections.

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9. Corner AnalysisSilicon fabrication processes vary wildly in an unpredictable manner. Circuits can

vary from predicted physical values in a number of ways, ultimately affecting the transistors themselves, the wires that interconnect them, or both. Circuits may be required to operate in wide variety of temperature conditions and input voltage levels. Process variability also comes into play. The variability in silicon fabrication processes, variation in temperatures and supply voltages, and the ability to account for these variations becomes the priority in maintaining the designers' intended performance.

So the circuit is simulated for wide range of temperatures, for varying W/L’s and for different input voltage levels. Each one of there is considered a corner and analysis of the circuit at all of these corners is done with appropriate models. The different types of corner analyses done and their results are presented below.

1. Variation of output with Temperature2. Variation of output with supply voltage.3. Slow-Slow and Fast-Fast corners .

Simulations for varying supply voltage (1.5v to 5v), Temperature ranges (-50 oC to 150 oC) and for different process models (typi_typi, fast_fast, and slow_slow) is under progress.

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10.ConclusionA 16X1 MUX is designed to select an array of FETs each having variable W/L

ratio. The following is the selection table to select different FETs

S3 S2 S1 S0W/L of the selected

FET0 0 0 0 1.05/0.50 0 0 1 5/10 0 1 0 10/10 0 1 1 15/10 1 0 0 20/10 1 0 1 25/10 1 1 0 30/10 1 1 1 40/11 0 0 0 50/11 0 0 1 60/11 0 1 0 80/11 0 1 1 100/11 1 0 0 120/11 1 0 1 140/11 1 1 0 170/11 1 1 1 200/1

Table 10.1: User Table to select the FETsThe output current mismatch is made sure that it wont exceed 5%. And for lower W/L the mismatch is very less (with in 1%). The circuit is tested for different process corners and the operating conditions of the design is yet to be discussed.

References

[1] CMOS Circuit Design, Layout and Simulation (2nd ED.) - R. Jacob Baker, IEEE Press, page 144 and page 378.