EE 434 Lecture 9 - Iowa State...
Transcript of EE 434 Lecture 9 - Iowa State...
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EE 434Lecture 9
IC Fabrication Technology
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Quiz 7 The layout of a film resistor with electrodes A and B is shown. If the sheet resistance of the film is 40 �/�, determine the resistance between nodes A and B.
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And the number is ….
631
24578
9
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Quiz 7 Solution
NS =9+9+3+2(.55)=22.1
RAB=R�NS=40x22.1=884�
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• Silicon Wafers made by pulling silicon crystals from molten silicon• Mask costs are high for state of the art processes (over $1M)
and mask quality is critical• Reticles rather than masks are regularly used although distinction
in terminology between mask and reticle is usually not made • Etching used to selectively remove materials during processing
– Wet etches– Dry etches
• Photolithographic process is used repeatedly in existing IC fabrication flows
• Thin films characterized by sheet resistance form resistors thatmay be desired or unwanted
Review from Last Time
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IC Fabrication Technology• Crystal Preparation• Masking• Photolithographic Process• Deposition• Etching• Diffusion• Oxidation• Epitaxy• Polysilicon• Contacts, Interconnect and
Metalization• Planarization
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Diffusion• Controlled Migration of Impurities
– Time and Temperature Dependent– Both vertical and lateral diffusion occurs– Crystal orientation affects diffusion rates in lateral and vertical
dimensions– Materials Dependent– Subsequent Movement– Electrical Properties Highly Dependent upon Number and
Distribution of Impurities– Diffusion at 800oC to 1200oC
• Source of Impurities– Deposition– Ion Implantation
• Only a few Ao deep• More accurate control of doping levels• Fractures silicon crystaline structure during implant• Annealing occurs during diffusion
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DiffusionSource of Impurities Deposited on Silicon Surface
Before Diffusion
After Diffusion
p- Silicon
p- Silicon
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DiffusionSource of Impurities Implanted in Silicon Surface
Before Diffusion
After Diffusion
p- Silicon
p- Silicon
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Diffusion
Implant
Before Diffusion
After Diffusion
Lateral Diffusion
p- Silicon
p- Silicon
p- Silicon
p- Silicon
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IC Fabrication Technology• Crystal Preparation• Masking• Photolithographic Process• Deposition• Etching• Diffusion• Oxidation• Epitaxy• Polysilicon• Contacts, Interconnect and Metalization• Planarization
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Oxidation
• SiO2 is widely used as an insulator– Excellent insulator properties
• Used for gate dielectric– Gate oxide layers very thin
• Used to separate devices by raising threshold voltage– termed field oxide– field oxide layers very thick
• Methods of Oxidation– Thermal Growth (LOCOS)
• Consumes host silicon• x units of SiO2 consumes .47x units of Si• Undercutting of photoresist• Compromises planar surface for thick layers• Excellent quality
– Chemical Vapor Deposition• Needed to put SiO2 on materials other than Si
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Oxidation
SiO2
Thermally Grown SiO 2 - desired growth
Photoresist
Patterned Edges
X
0.47 X
p- Silicon
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Oxidation
SiO2
Thermally Grown SiO 2 - actual growth
Photoresist
Patterned Edges
Bird’s Beaking
p- Silicon
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Oxidation
Thermally Grown SiO 2 - actual growth
Patterned Edges
NonplanarSurface
p- Silicon
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Oxidation
Shallow Trench Isolation (STI)
p- Silicon
Photoresist Pad Oxide
Silicon Nitride
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Oxidation
Shallow Trench Isolation (STI)
p- Silicon
Pad OxideSilicon Nitride
Etched Shallow Trench
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Oxidation
Shallow Trench Isolation (STI)
p- Silicon
Pad OxideSilicon Nitride
CVD SiO2
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Oxidation
Shallow Trench Isolation (STI)
p- Silicon
Planarity Improved Planarization Target
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Oxidation
Shallow Trench Isolation (STI)
p- Silicon
After Planarization
CVD SiO2
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IC Fabrication Technology• Crystal Preparation• Masking• Photolithographic Process• Deposition• Etching• Diffusion• Oxidation• Epitaxy• Polysilicon• Contacts, Interconnect and Metalization• Planarization
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Epitaxy
• Single Crystaline Extension of Substrate Crystal– Commonly used in bipolar processes
– CVD techniques– Impurities often added during growth
– Grows slowly to allow alignmnt with substrate
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Epitaxy
p- Silicon
Original Silicon Surface
Epitaxial Layer
epi can be uniformly doped or graded
Question: Why can’t a diffusion be used to create the same effect as an epi layer ?
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IC Fabrication Technology• Crystal Preparation• Masking• Photolithographic Process• Deposition• Etching• Diffusion• Oxidation• Epitaxy• Polysilicon• Contacts, Interconnect and Metalization• Planarization
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Polysilicon
• Elemental contents identical to that of single crystaline silicon– Electrical properties much different– If doped heavily makes good conductor– If doped moderately makes good resistor– Widely used for gates of MOS devices– Widely used to form resistors– Grows fast over non-crystaline surface– Silicide often used in regions where resistance must
be small• Refractory metal used to form silicide• Designer must indicate where silicide is applied (or blocked)
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Polysilicon
Single-Crystaline Silicon
Polysilicon
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IC Fabrication Technology
• Crystal Preparation• Masking• Photolithographic Process• Deposition• Etching• Diffusion• Oxidation• Epitaxy• Polysilicon• Contacts, Interconnect and Metalization• Planarization
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Contacts, Interconnect and Metalization
• Contacts usually of a fixed size– All etches reach bottom at about the same time
– Multiple contacts widely used– Contacts not allowed to Poly on thin oxide in
most processes– Dog-bone often needed for minimum-length
devices
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Contacts
Vulnerable to pin holes
A A’
Unacceptable Contact
B
B’
Acceptable Contact
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Contacts
Acceptable Contact
B
B’
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Contacts
2�1.5�
2�
1.5�
Design Rule Violation
2�
“Dog Bone” Contact
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Contacts
CommonCircuit Connection
Standard Interconnection Buried Contact
Can save area but not allowed in many processes
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Metalization
• Aluminum widely used for interconnect
• Copper finding some applications• Must not exceed maximum current density
– around 1ma/u
• Ohmic Drop must be managed
• Parasitic Capacitances must be managed• Interconnects from high to low level metals
require connections to each level of metal
• Stacked vias permissible in some processes
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Multiple Level Interconnects
3-rd level metal connection to n-active without st acked vias
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Multiple Level Interconnects
3-rd level metal connection to n-active with stack ed vias
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Interconnects
• Metal is preferred interconnect– Because conductivity is high
• Parasitic capacitances and resistances of concern in all interconnects
• Polysilicon used for short interconnects– Silicided to reduce resistance– Unsilicided when used as resistors
• Diffusion used for short interconnects– Parasitic capacitances are high
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Resistance in Interconnects
L
W
H
A
B
BA
R
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Resistance in Interconnects
L
W
HA
B
BD
R
D
�AL
R =
A=HW
� independent of geometry and characteristic of the process
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Resistance in Interconnects
L
W
HA
B
D
��
���
�==H�
WL
�AL
RH << W and H << L in most processesInterconnect behaves as a “thin” filmSheet resistance often used instead of conductivity to characterize film
R�=�/H R=R�[L / W]
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Resistance in Interconnects
R=R�[L / W]
L
W
The “Number of Squares” approach to resistance determination in thin films
1 2 3 21NS = 21
L / W=21
R=R�NS
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Resistance in Interconnects
R=R�13.25
Corners Contribute about .55 Squares
Fractional Squares Can Be RepresentedBy Their Fraction
In this example:
NS=12+.55+.7=13.25
The “squares” approach is not exact but is good enough for calculating resistance in almost all applications
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Capacitance in Interconnects
Metal 1
Metal 2
Substrate
A1
A4
A2
A3
A5
Equivalent Circuit
C12=CD12 A5
C1S=CD1S (A1+A2+A5)
C2S=CD2S (A3+A4)
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Capacitance in Interconnects
C=CDACD is the capacitance density and A is the area of the overlap
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Capacitance and Resistance in Interconnects
• See MOSIS WEB site for process parameters that characterize parasitic resistances and capacitances
www.mosis.org
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IC Fabrication Technology
• Crystal Preparation• Masking• Photolithographic Process• Deposition• Etching• Diffusion• Oxidation• Epitaxy• Polysilicon• Contacts, Interconnect and Metalization• Planarization
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Planarization
• Planarization used to keep surface planar during subsequent processing steps– Important for creating good quility layers in
subsequent processing steps
– Mechanically planarized