EDA TOOLS. Why EDA? Imagine a Intel based micro processor having 1.5 million transistors. Would it...

EDA TOOLS

Why EDA?

Imagine a Intel based micro processor having 1.5 million transistors. Would it be feasible to design such a complex system with help of truth table and K-maps?

Obviously Impossible.

Continued

Today’s semiconductors and electronic systems are complex that designing them would be impossible without electronic design automation (EDA). This primer provides a comprehensive over view of the electronic design process, then describes how design teams use Cadence tools to create the best possible design in the least amount of the time.

Digital Design Flow

Verilog/VHDL Library

Std., Cell. Library

Tech file For layout

values

Look upTable fortiming

Tech fileFor RCParasite

extraction

Design Analysis

Design Specification

Synthesis

Design Implementation using HDL

Simulation

Timing Analysis

Place & Route

Extraction

Verification

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Design Analysis

This is a very crucial step in digitaldesign where the design functionalityis stated.

Like if we are making a processor,what type of functionality is expected??

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Design SpecificationThis step involved stating in definite terms the performance of the chip.

Like if we are making a processor,data size, processor speed, special functions, power etc. is clearly statedat this point. Also somewhat it is decided,the way to implement the design.

So, it deals with architectural part of the design at highest level possible.

Based on these foundation , the wholedesign is built

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

HDL

Hardware Description Language is usedto run the simulations.

It is very expensive to build the entire chip and then verify the performance of the architecture. Imagine if after designinga chip for a whole year, the chip fabricated,does not come even closer to the statedspecifications.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

HDL (contd.)

Hardware description languages providesa way to implement a design without goinginto much architecture, simulate and verifythe design output and functionality.

For eg. rather than building a mux designin hardware, we can write verilog code and verify the output at higher levelof abstraction.

Examples of HDL: VHDL, Verilog HDL

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

HDL (Contd.)

At this time we can see the designin the form of Source Codes.

It seems more of the softwarevisualization of the circuit.

The simulated code is taken to Synthesis to generate the LogicCircuit.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Synthesis

Imagine the use of K-Maps and TruthTables to make and implement a digitaldesign.

If you notice, most of the digital designsare build up of some basic elements or components like gates, registers, counters,adders, subtractors, comparators, RAM,ROM etc.

It forms the fundamentals of Logic Synthesis using EDA tools.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Synthesis (Contd.)

Standard Cell Library is the collectionof such building blocks which comprisesmost of the digital designs.

These cell libraries are fabricationtechnology specific.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Synthesis ( Contd.)

After the RTL simulation, the HDL,code is taken as input by SynthesisTool and converted to Gate level.

At this stage that the digital designbecomes dependent on the fabrication process.

At the end of this stage, we have the logic circuit I.e. in terms of gates and memories.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Synthesis ( Contd.)

What synthesis does is , when it encounters a specific constructin HDL it replaces it with the corresponding Standard Cell Component from the library tobuild the entire design.

Like if we use a for loop , it getsconverted to counter and a combinational circuit.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Synthesis ( Contd.)

The output of synthesis is a gatelevel netlist.

Netlist is an ASCII file whichenlists and indicates the devicesand the interconnections betweenthem.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Simulation

After the netlist is generated as partof synthesis, this netlist is simulatedto verify the functionality of thisgate level implementation of design.

Till this level we just dealt with functionality part. Now each steponward deals with performancepart too.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Timing Analysis

RTL and Gate Level simulationdoesn’t take into account the physicaltime delay in signal propagation fromone device to another and through the device.

This time delay is dependent on the fabrication process adopted.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Timing Analysis (Contd.)

Each component in standard celllibrary is associated with some specific delay.

Delay Lookup Tables list the delays associated with the components.

Delays are in the form of rise time, fall time and turn offtime delays.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification


Most of the digital designs employconcept of timing by using clocks.This makes the circuits synchronous.

Consider an AND gate with two inputs,x and y. If at time t = 1 ns, x is available,and y comes 1 ns later, what would be the output. This mismatch in timingleads to erroneous performance of design.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification


In timing analysis, using Delay Lookup Tables, all the inputsand outputs of components areverified with timing introduced.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Place & Route

This is the actual stage wherethe design implemented atsemiconductor layout level.

This the stage which really requires more knowledge ofsemiconductor physics thandigital design.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Place & Route (Contd.)

Semiconductor layout has to followcertain design rules to lay devicesat semiconductor level.

These design rules are fabrication process dependent.

The layout uses layers as p/n diffusion,nwell, pwell, metals, via, iso etc. Rules involving min. spacing, and electrical relation between two layersare known as DESIGN RULES.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Place & Route (Contd.)

Placement and Routing involveslaying of the devices, placing themand making interconnection betweenthem, following the Design Rules.

The result is the design implementedin the form of semiconductor layers.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Extraction

Once the layout is made, there alwaysis parasitic capacitances and resistancesassociated with the design.

This is because of the compact layoutsto make the chips smaller. More you makecompact layout more will it introducethese parasitic components. Theseinterferes in the functioning and performance of the circuit in terms of timing, speed and power consumption.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Extraction (Contd.)

Due to these factors it becomes verymuch important to extract these devicesfrom layout and check the design forperformance and functionality.

Extraction would extract from the layout,the devices formed because of junctionsof different semiconductor and metallayers and the interconnections.

Design Analysis


Synthesis


Simulation

Timing Analysis

Place & Route

Extraction

Verification

Verification

Verification would either be the tape out stage of the chip or the stagewhere design is again taken back through the same flow for optimization or modification.

It verifies the extracted view of thechip for performance and functionality.

Major Companies in EDA Tools

• Cadence Design Systems• Synopsys• Avanti• Tanner

Cadence is the world's largest provider of electronic design automation (EDA) products and services. Our end-to-end solutions help computer, communication, and consumer electronics companies create high-performance systems and integrated circuits (ICs) in the shortest possible time. Cadence is a global company with 5,700 employees in over 30 major locations, and revenues of nearly $1.3 billion in 2000.

CadenceFact sheet

History of Cadence

Cadence Design Systems, Inc. was established in 1988 through the merger of two EDA pioneers—ECAD, Inc. and SDA Systems. Through innovative product development, strategic partnerships, and highly successful business mergers, Cadence has become the industry's leading supplier of EDA software technology and services.

•System-level Design•Functional Verification•Emulation and Acceleration•Synthesis/Place-and-Route•Analog, RF, and Mixed-signal Design•Custom IC Layout•Physical Verification and Analysis•IC Packaging•PCB Design

Cadence Design Technologies

Cadence Design FlowDigital Design:

StandardCell Library

Pearl Static Timing Analysis

Silicon EnsemblePlacement & Route

Hyper Extract Tech. Rules verification

Ambit Synthesis

NC-Verilog

NC - Verilog





Ambit Synthesis

NC-Verilog

NC-Family of Simulators

The Cadence NC family of simulators (NC-Sim, NC-Verilog®, NC-VHDL and the Verilog® and VHDL Desktop simulators) provides a single-kernel simulator that can verify both mixed-language and mixed-signal designs.

NC – Verilog (Contd.)





Ambit Synthesis

NC-Verilog

Advantage

Works on the principle of NativeCompilation.

Unlike other compilers it compilesHDL code directly to machine executable codes, rather than goingthrough the intermediate conversion to C.

It decreases:Compilation time, Memory requirement and use of system resources

NC – Verilog (Contd.)





Ambit Synthesis

NC-Verilog

Key Features

Fastest mixed-language simulation available due to unique NC architecture Powerful integrated debug and analysis environment Mixed-language, mixed-signal, and system-level support

Ambit Buildgates Synthesis





Ambit Synthesis

NC-Verilog

Key Features

BuildGates® Synthesis can synthesize multimillion-gate designs very rapidly.

BuildGates features high-capacity and high-performance timing analysis.

.

Ambit Buildgates Synthesis





Ambit Synthesis

NC-Verilog

BuildGates® Synthesis can synthesize multimillion-gate designs very rapidly.

BuildGates features high-capacity and high-performance timing analysis.

.

Ambit Buildgates SynthesisContd.





Ambit Synthesis

NC-Verilog

Key Features

Provides productive multimillion-gate synthesis through higher capacity and faster runtimes Delivers accuracy and reduced iterations through integrated sign-off static timing analysis Reduces IC power consumption with the Low-power Synthesis Option .

Ambit Buildgates SynthesisContd.





Ambit Synthesis

NC-Verilog

Optimized Design

It can optimize the design for:• Speed • Size • Power Consumption.

Static Timing Analysis (Pearl)

In this era of high performance electronics, timing continues to be a top priority and designers are spending increased effort addressing IC performance.

Two Methods are employed for Timing Analysis:

Dynamic Timing AnalysisStatic Timing Analysis

Static Timing Analysis (Pearl)(Contd.)

Traditionally, a dynamic simulator has been used to verify the functionality and timing of an entire design or blocks within the design.

Dynamic timing simulation requires vectors, a logic simulator and timing information. With this methodology, input vectors are used to exercise functional paths based on dynamic timing behaviors for the chip or block.

Dynamic Timing Analysis


The advent of larger designs and mammoth vector sets make dynamic simulation a serious bottleneck in design flows.

Dynamic simulation is becoming more problematic because of the difficulty in creating comprehensive vectors with high levels of coverage.

Time-to-market pressure, chip complexity, limitations in the speed and capacity of traditional simulators -- all are motivating factors for migration towards static timing techniques.

Dynamic Timing Analysis: Limitations


STA is an exhaustive method of analyzing, debugging and validating the timing performance of a design.

First, a design is analyzed, then all possible paths are timed and checked against the requirements.

Since STA is not based on functional vectors, it is typically very fast and can accommodate very large designs (multimillion gate designs).

STA is exhaustive in that every path in the design is checked for timing violations.


Limitations:

STA does not verify the functionality of a design. Also, certain design styles are not well suited for static approach. For instance, dynamic simulation may be required for asynchronous parts of a design and certainly for any mixed-signal portions.

Silicon EnsemblePlace & Route

Future Trends

• Verilog AMS• CCAR (Cadence Chip Assemble Router)• VCC• Testbuilder for Verification• PKS (Physically Knowledgeable Synthesis)• ATS

EDA TOOLS. Why EDA? Imagine a Intel based micro processor having 1.5 million transistors. Would it...

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