Silvaco EDA Demo
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Transcript of Silvaco EDA Demo
SILVACO, Inc., a Delaware corporation headquartered in Santa Clara, California, is the
leading supplier of Technology Computer Aided Design (TCAD) software, and a major
supplier of Electronic Design Automation (EDA) software for circuit simulation and design of
analog, mixed-signal and RF integrated circuits.
What we Offer ?
Silvaco delivers & supports TCAD & Integrated EDA software products in following
segments.
1) TCAD - Complete family of 2D and 3D process, device and stress simulation products.
2) Analog/Mixed-Signal/RF - Complete family of full-chip and circuit simulation products
for analog, mixed-signal, and RF.
3)Custom IC CAD - PDK-based design flow with schematic, layout, physical verification,
and parasitic extraction.
4)Digital CAD - Cell/core library characterization, place and route, and Verilog simulation
products.
Introduction to Silvaco EDA
Silvaco provides Integrated Flow(Single vendor), tools which work together, easy to install,
easy to maintain, easy to operate.
Silvaco provides Front-end PDK for Schematic driven circuit simulator environment with
accuracy, performance to provide complete analog/mixed-signal/RF design flow.
Silvaco provides BACK-end PDK for Fast layout Editing with Integrated DRC/LVS, PCell
Scripting.
All data is present in Silvaco's Foundry PDK which is important for Foundry Interface.
Silvaco has developed 5 set of Demo Process design kits
1)Analogue Demo PDK
2)Logic Demo PDK
3)Mixed-Signal Demo PDK
4)Radio Frequency Demo PDK
5)MOSIS SCMOS PDK
These PDKs enable educational institutions, design Service providers & fabless companies to
be immediately productive in using Silvaco's Integrated IC design capture, Simulation,
Layout & verification tools on Linux, Solaris & Windows platform.
In this article we will demonstrate how to design & Implement a CMOS Inverter.
Circuit Schematic Capture with Gateway
Schematic Editor & Simulator Front End Requirements
What circuit designers need?
Edit/View Schematics in a user-friendly environment.
Create netlists for simulators and layout-vs-schematic tools
Manage files for multiple designers and projects
Gate Schematic capture & Editor
GATEWAY is a schematic capture tool and is the entry point for the IC design flow.Gateway
is the entry point of the design as its main purpose is generating a netlist that can be loaded
into circuit simulators.
Gate way Schematic editor is
• Powerful frontend schematic editor & viewer.
• Integrated with Smartspice & Smartview.
• Creates multi-sheet, multi-view, hierarchical, Flat Designs.
• Generate both schematic netlist & LVS netlist from the same schematic.
• Hierarchical DC bias for all currents & voltages.
• Gateway supports importing/exporting of EDIF(Electronic design Interface Format)
version 2 0 0 files.
• Ability to switch processes & run process variant simulation on same schematic.
Gateway features easy & flexible way of library management. Create a Workspace, Click on
File-->New-->Workspace . After Saving your Workspace we need to add the library which is
necessary for our simulation.
The image below for this Demo shows the Necessary Library file that has to be added.
The following necessary library will be added, all those symbol libraries will appear which we
will be using in our CMOS inverter design which is shown in Symbol/Options dock window as
shown in above fig.
Next we create a new schematic for our CMOS Inverter design
Click on File--->New--->Schematic
Save the Schematic as CMOS Inverter
The above image shows you the schematic of CMOS Inverter Circuit.
Gateway offers 3-level circuit check functions(check this level. check this level & below,
Check all levels) if there is any errors/warnings designers can easily locate them by double
clicking the error/warning message in the Output/Probe/Errors dock window
Once the Check all level verification is completed simulation of CMOS inverter is done by
SmartSpice which is Integrated with Gateway.
What is this SmartSpice?
SMARTSPICE is a high quality, commercial grade, general purpose circuit simulation program
for nonlinear DC, nonlinear transient, and linear AC analyses.
SmartSpice easily fits in to your analog design flow, supports foundry supplied device models.
SmartSpice is 100% HSPICE compatible for netlists, models, analysis features & result.
What are the features of SmartSpice? Model & Simulation Accuracy. Advanced stepping algorithm & automatically adapt to circuit topology.
Handles 1st, 2nd, 3rd derivatives.
Berkeley style of model interface.
Support of standard compact models. Berkeley SPICE model compatibility include following models
� BJT/HBT: Gummel-Poon, Quasi-RC, VBIC, MEXTRAM,
MODELLA, HiCUM
� MOSFET: LEVEL 1, LEVEL 2, LEVEL 3, BSIM1, BSIM3,
BSIM4, MOS 11, MOS 20, EKV, HiSIM, PSP, HVMOS, LDMOS
� TFT: Amorphous and Polysilicon TFT models:
Berkeley, Leroux, RPI
� SOI: Berkeley BSIM3SOI PD/DD/FD, UFS, LETISOI
� MESFET: Stats, Curtice I & II, TriQuint
� JFET: LEVEL 1, LEVEL 2
� Diode: Berkeley, Fowler-Nordheim, Philips JUNCAP/Level 500
� FRAM: Ramtron FCAP
Support of Verilog-A language for behavioural description.
Speed, Convergence, Capacity. 2 to 5 times faster than any other SPICE simulator.
Multiple-thread functionality for multiple CPU cores.
Three direct & 2 iterative solvers designed for optimal simulation performance of circuit topologies.
SmartSpice-64 offers capability limited based on the available memory.
Multi-million transistor circuits are easily simulated
Circuit debugging.
Gateway can generate 2 types of netlists
SmartSpice Netlist for circuit simulation.
Guardian Netlist for LVS Verification.
Clicking on Simulation->Edit control File an SEdit window will pop out in which designers
can specify analysis statement, options, parameters, the necessary model files are included
We can create a symbol for CMOS Inverter circuit which is easy for Post-layout simulation.
Click on tools & then click on Generate Symbol
The above image shows the representation of the Schematic Inverter in Symbol for which is
used for other simulation purpose which will be discussed later.
Next we need to analyse the DC, AC & Transient characteristics of CMOS Inverter.
Create a new schematic file & save it as Inverter_trans.schr
You can see the CMOS Inverter design for transient response
After this the simulation is ready to be launched. The waveform of simulation is shown in fig
below
Layout and Verification Once the circuit schematic is working, we can proceed to the layout design and its
verification. Like in Gateway and Smartspice, the demo PDK has provided necessary
files and settings for layout design and verification. Designers may go through the
documentations which are shipped in the PDK package for more details.
Layout generation is done through expert.
What is Expert? Expert Layout Editor enables mask designers to achieve maximum density and performance
in analog and digital layouts.
Expert’s high-productivity design environment offers fast layout viewing, full editing
features, large capacity, and powerful scripting for automation with parameterized cells.
In our CMOS Inverter Design Start expert tool.
Click on File->New
Save the project as CMOSInverter.eld
Select the technology file as SCMOS.tcn
Load the Pcell Library scoms_subm_pcells to facilitate the design. The Pell library contains
those frequently used cells such as MOS, BJT, N-well/Substrate Connection etc.
Chose the corresponding Guardian DRC rule file "mosis-cmos-drc.dsf"
Configure the Guardian LPE(Hipex) extraction technology to use LISA script file.
"inverter_c.cmd" & "inverter_r.cmd"
Figure above shows you the CMOS inverter layout.
After finishing the layout design, we can proceed to do the DRC check whether there is
violation of design rules. Open DRC script panel load "mosis-cmos-drc.dsf" & run the check
Expert-->Verification-->DRC-->DRC run setup-->Enable “Command progress bar” and “Script progress bar”.
Once the layout becomes DRC error free, we can extract netlist from layout so that we
can use it compare with the schematic netlist generated from Gateway.
Click Verification-->Extraction-->Setup-->Technology as shown below
After this extraction is invoked from Verification-->Extraction-->Hipex-Net-->Run the netlist
extracted from the layout can be viewed from Verification-->Extraction-->Hipex-Net-->View
netlist
Previously we mentioned that Gateway can generate two netlist formats: Smartspice
and Guardian; for LVS we will use the Guardian netlist. By now we have both netlists
ready: netlist extracted from layout and the netlist generated from schematic.
Invoke Guardian LVS from Expert-->Verification-->Launch LVS.
In the following Project Setting dialogue, browse & select netlist from schematic & layout
respectively Click OK when the input files have been selected.
Click Run LVS button to start LVS. From the LVS log file it can be seen that this layout
successfully passed the LVS verification.
So the Netlist matches & the LVS verification is successfully completed.
Extraction & Post layout verification Since the LVS verification has been passed, normally we assume that the performance
of the layout design should be quite close to what we expect from the schematic
design. We can do a simulation with the netlist from layout extraction (Hipex-Net), i.e.
the netlist that we used just now for LVS.
Also, we may consider the parasitics effect of the layout. For example if we want to
see the impact of parasitics capacitance, we can run a Hipex-C extraction from
Expert-> Verification -> Extraction -> Hipex-C-> Run. After the extraction
process finishes, we can view the extracted netlist with parasitic capacitance included
It can be opened from Expert-> Verification ->Extraction -> Hipex-C->View
Netlist
we can see that the Hipex-C has generated the capacitance elements into the netlist.