ECEN 248 Lab7_report

8/10/2019 ECEN 248 Lab7_report

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Objectives:The objective of this lab is to learn a higher level of abstraction that is called behavioral Verilog

and this is used to improve the productivity and simplicity of a circuit because it just describesthe behavior rather than notating what specific gates are being used. This will be used and then

demonstrated using logic synthesis which will use the written code to create a circuit that can be

implemented. This is also our first real time working with the Xilinx board and we will learn toimplement our programs and use the boards switches to demonstrate the programs

functionality.

Design://two_one_mux_behavioral`timescale 1 ns / 1 ps`default_nettype none

module two_one_mux(Y, A, B, S);

output reg Y; //output

input wire A, B, S; //inputs including select bit//behavioral begin-end blockalways@(A or B or S)

beginif(S==1'b0) //one bit binary value of zero

Y=A; //if S=0 then Y=Aelse //any other value

Y=B; //if S=1 then Y=Bend

endmodule

//four_bit_mux`timescale 1 ns/ 1 ps`default_nettype none

module four_bit_mux(Y, A, B ,S);//four bit 2:1 mux

output reg [3:0] Y; //output is 4-bit wide reginput wire [3:0] A, B; //inputs for A and B are 4-bit wiresinput wire S; //select is only 1-bit wide

always@(A or B or S)begin

if(S==1'b0) //one bit binary value of zeroY=A; //if S=0 then Y=A

else //any other valueY=B; //if S=1 then Y=B

end

endmodule


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//mux_4bit_4to1`timescale 1 ns/ 1 ps`default_nettype none

module mux_4bit_4to1(Y, A, B, C, D, S);

output reg [3:0] Y; //setting the inputs and outputsinput wire [3:0] A, B, C, D; //each LEDinput wire [1:0] S;

always@(*)case (S) //behaviorally describing which binary responds to which LED

2'b00: Y = A;2'b01: Y = B; //each 2-bit binary has a letter output connected to an LED2'b10: Y = C;2'b11: Y = D;

endcase

endmodule

//two_four_decoder`timescale 1 ns/ 1 ps`default_nettype none

module two_four_decoder(input wire [1:0] W, //initializing input and output while also defining the moduleinput wire En,output reg [4:0] Y

);

always@(En or W)begin

if(En == 1'b1)

case(W) //case statement about the input2'b00: Y = 4'b0001; //for each 2-bit binary input it is matched with the 4-bit equivalent2'b01: Y = 4'b0010;2'b10: Y = 4'b0100;2'b11: Y = 4'b1000;

endcaseelse

Y = 4'b0000; //anything else is zeroend

endmodule

//four_two_encoder

`timescale 1 ns/ 1 ps`default_nettype none

module four_two_encoder( //defining the module and the wiresinput wire [3:0] W,output wire zero,output reg [2:0] Y

);assign zero = (W == 4'b0000);


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always@(W)begin

case(W) //case statement about the input4'b0001 : Y = 2'b00; //assigning 2-bit output for a 4-bit input4'b0010 : Y = 2'b01;4'b0100 : Y = 2'b10;4'b1000 : Y = 2'b11;default Y = 2'bXX; //defaults to 2-bit dont care

endcaseend

endmodule

//priority_encoder`timescale 1 ns/ 1 ps`default_nettype none

module priority_encoder( //defining the module with input and outputsinput wire [3:0] W,output wire zero,

output reg [2:0] Y);

assign zero = (W == 4'b0000); //initializing W at zero

always@(W)begin

casex(W)4'b0001 : Y = 2'b00; //first case is the full 4-bit number4'b001X : Y = 2'b01; //cuts off 4-bit number after a 1 appears4'b01XX : Y = 2'b10; //less significant bits become dont cares 4'b1XXX : Y = 2'b11;default Y = 2'bXX; //Defaults to 2-bit dont care

endcase

end

endmodule

Results:The screenshots of the waveforms of each source code can be seen in figures 7.1-7.6. Each code

worked in the manner that it was supposed to work, however it took a bit of looking into the test

bench code in order to understand how each code was supposed to work in conjunction with theXilinx board. Some of the test benches had coded the North-South-East-West buttons as the

switches while some of the test benches had coded the switches as the switches. Other than that

slight difference in what I had expected for the board which was purely a stylistic choice on the

programmers part, it was very standard and each code worked properly. In each waveform eachtest can be shown as passing and giving the proper output, and the only ones that show a red part

are the ones that involved having an output entirely consisting of dont care bits (figures 7.5

and 7.6.)


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Figure 7.1: 2 to 1 Multiplexer

Figure 7.2: Four bit Multiplexer


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Figure 7.3: 4-bit 4:1 Multiplexer

Figure 7.4: 2:4 Decoder


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Figure 7.5: 4:2 Encoder

Figure 7.6: Priority encoder


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Conclusion:This lab was very informative on how to program a physical circuit board and I gainedfamiliarity with the programs associated with the process of programming the Xilinx. I learned a

lot about how to download the program onto the board the proper way and also a lot about how I

shouldnt download it. I also learned a lot about behavioral programming and how it can be far

more efficient than structural or dataflow programming because it allows for me to just give a setof inputs and the corresponding outputs and it will create the proper circuit to give those outputs.

While this was not a very labor intensive lab, it was highly informative and useful in learning

how to program in Verilog and how to use the Xilinx board to demonstrate the code and presentthe information in an understandable fashion.

Questions:

1. Code is listed in the design section of this lab.2. Screenshots are provided in the results section in Figures 7.1-7.63. //2:1 Mux Structural

`timescale 1 ns/ 1 psmodule two_one_mux(Y, A, B, S);

output wire Y; //declaring variables to be usedinput wire A, B, S;

wire notS; //declaring wireswire andA;wire andB;

not not0(notS, S); //declaring logic gates and what variables are used within themand and0(andA, notS,A);and and1(andB, S, B);or or0(Y, andA, andB);

endmodule //end of module

//2:1 Mux Behavioral`timescale 1 ns / 1 ps`default_nettype none

module two_one_mux(Y, A, B, S);

output reg Y; //output

input wire A, B, S; //inputs including select bit//behavioral begin-end block

always@(A or B or S)begin

if(S==1'b0) //one bit binary value of zeroY=A; //if S=0 then Y=A

else //any other valueY=B; //if S=1 then Y=B

end

endmodule


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Above are shown the two different ways that I have programmed a 2:1 Multiplexer using

Verilog. The first way is my source code from Lab 6 using structural programming for

the mux and it programs each specific logic gate with specific inputs and outputs basedon the layout of the circuit. The second way is source code from earlier in this lab using

behavioral programming to create the same circuit, but the behavioral programming just

dictates what the inputs could be and what the output is in each case without explainingthe inner workings of the multiplexer. Advantages of the first one would include easyprogramming if a schematic has already been obtained because then it is just coding the

specific gates, also this makes it easier to manage what the inner workings of the circuit

are for whatever reason such as cost and efficiency. Advantages of the second one isexactly the opposite of why the first would be used; we dont care about the inner

workings, we just care about the output of the circuit being correct so we let the program

decide what functions it wants to use and just dictate what it has as an output. This

behavioral method makes it easier to program more intricate circuits because it isnt asimportant to have every gate specifically coded and that wastes time and space in the

code seeing as it is very possible that there is a more efficient way to design the circuit

than the way that is shown in a structural program.4. Bread-boarding and using an FPGA both have their own purposes and their own merits, Iprefer the FPGA because I dont like fighting with wires, but it isnt always the best

choice. Bread-boarding is great for seeing physically what is happening within the circuit.

I can look at a bread-board and see all of the different inputs and outputs and knowexactly what is going where and it makes it easier to spot bugs. Having a physical

representation of the circuit can be very informative of what is happening. For example,

for research I had to help build a solar charging circuit and this involved putting manydifferent components on a board and allowed for a very visual way of viewing the inner

workings of the circuit and we were able to see why it was or wasnt working based on

the components. The same goes for digital logic circuits. Where a program is much easier

to use and download onto and FPGA board and it obtains the same result, but sometimes

at the cost of not actually understanding the inner workings of the circuit itself.

Student Feedback:

1. The lab manual was once again extremely informative and useful. I like that I am actuallylearning how to use the software and program in Verilog. There wasnt anything that Ididnt really like about the assignment.

2. The lab manual was, once again, flawless. No need for improved clarity. Bravo, ECEN248 lab writers, youve outdone yourselves again and I highly appreciate the amount of

detail. It is nice to follow a lab that has outlined everything you need to do andthroughout the entire lab it says places where you might get confused and how to remedy

that. It has its own safeguard against stupid mistakes; incredible I tell you!3. No need to improve this lab. It is informative and easy to follow the instructions and on

top of that it is actually a very useful tool for learning Verilog.

ECEN 248 Lab7_report

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