ECE 551: Digital System Design & Synthesis
description
Transcript of ECE 551: Digital System Design & Synthesis
![Page 1: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/1.jpg)
1
ECE 551: Digital System Design & Synthesis
Spring 2003
Lecture Materials Prepared by: Charles Kime, Kewal Saluja and Michael Schulte
![Page 2: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/2.jpg)
1/16/2003 ECE 551 Spring 2003 2
ECE 551: Digital System Design & Synthesis
Lecture Set 1:oIntroductionoOverview of Contemporary Digital Design
oPragmatics 1
![Page 3: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/3.jpg)
1/16/2003 ECE 551 Spring 2003 3
ECE 551 - Digital System Design & Synthesis Lecture 1.1 - Introduction
Overviewo Course Purposeo Course Topicso Course Toolso Course Info
![Page 4: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/4.jpg)
1/16/2003 ECE 551 Spring 2003 4
Course Purpose To provide knowledge and experience in
performing contemporary logic design based on o Hardware description languages (HDLs)o HDL simulationo Automated logic synthesis o Timing analysis
With consideration for o Practical design and test issueso Chip layout issueso Design reuse for system-on-a-chip (SoC)
![Page 5: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/5.jpg)
1/16/2003 ECE 551 Spring 2003 5
Course Topics Pragmatics of Digital Design Hardware Modeling with the Verilog HDL Event-Driven Simulation and Testbenches Verilog Language Constructs and Delay Behavioral Descriptions in Verilog An Overview of VHDL Logic Synthesis and Timing Physical Design and Design Reuse
![Page 6: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/6.jpg)
1/16/2003 ECE 551 Spring 2003 6
Course Tools Modelsim HDL Simulation Tools
(Mentor) Design Analyzer Synthesis Tools
(Synopsys) G11 Technology Library (LSI Logic)
![Page 7: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/7.jpg)
1/16/2003 ECE 551 Spring 2003 7
Course InformationCourse Conduct Standard ReferenceThe above plus all other course
material can be found at http://courses.engr.wisc.edu/ecow/get/ece/551/kime/
Be familiar with all!
![Page 8: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/8.jpg)
1/16/2003 ECE 551 Spring 2003 8
Lecture 1.2 – Contemporary Digital Design Overview
o Layout Liteo Application Specific Integrated Circuit
(ASIC) Technologieso IC Costso ASIC Design Flows
The Role of HDLs and Synthesis The Role of IP Cores and Reuse The Role of Physical Design
o Summary
![Page 9: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/9.jpg)
1/16/2003 ECE 551 Spring 2003 9
Layout Lite - 1 IC are produced from masks that
correspond to geometric layouts produced by the designer or by EDA tools.
In CMOS, a typical IC cross-section:
Substrate
Oxide
Transistor
Metal 3
Metal 2
Metal 1
PolysiliconDiffusion
Channel
![Page 10: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/10.jpg)
1/16/2003 ECE 551 Spring 2003 10
Layout Lite - 2 The layout corresponding to the cross-section:
o The transistor is outlined in broad yellow lines.o Everything else is interconnect.
Channel
Transistor
![Page 11: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/11.jpg)
1/16/2003 ECE 551 Spring 2003 11
IC Implementation Technologies
STANDARDIC
FULLCUSTOM
SEMI-CUSTOM
FIELDPROGRAMMABLE
STANDARDCELL
GATE ARRAY,SEA OF GATES
ASIC
FPGA PLD
![Page 12: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/12.jpg)
1/16/2003 ECE 551 Spring 2003 12
Distinguishing Features of IC Technologies - 1
Implementation technologies are distinguished by:o The levels of the layout 1) transistors
and 2) interconnect that are: Common to distinct IC designs (L1) Different for distinct IC designs (L2)
o The use of predesigned layout cells Predesigned cells are used (P1) Predesigned cells are not used (P2)
![Page 13: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/13.jpg)
1/16/2003 ECE 551 Spring 2003 13
Distinguishing Features of IC Technologies - 2
Implementation technologies are distinguished by:oMechanism used for instantiating
distinct IC designs: Metallization (M) Fuses or Antifuses (F) Stored Charge (C) Static Storage (R)
![Page 14: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/14.jpg)
1/16/2003 ECE 551 Spring 2003 14
Technologies in Terms of Distinguishing Features - 1Full Custom – P2, M
oTransistors – L2, Interconnects – L2Standard Cell – P1, M
oTransistors – L2, Interconnects – L2Gate Array, Sea of Gates – P1, M
oTransistors – L1, Interconnects – L2
![Page 15: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/15.jpg)
1/16/2003 ECE 551 Spring 2003 15
Technologies in Terms of Distinguishing Features - 2FPGA – P1, F or R
oTransistors – L1, Interconnects – L1PLD – P1, F or C
oTransistors – L1, Interconnects – L1
![Page 16: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/16.jpg)
1/16/2003 ECE 551 Spring 2003 16
Technologies in Terms of Shared Fabrication Steps
Custom Fabricated Layerso Full Custom and Standard Cells – all layers are
custom fabricatedo Gate Arrays and Sea of Gates – only interconnect
(metallization) layers custom fabricatedo FPGAs and PLDs – nothing is custom fabricated
Consequences due to economy-of-scale:o Fab costs reduced for Gate Arrays and Sea of Gateso Fab costs further reduced for FPGAs and PLDs
![Page 17: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/17.jpg)
1/16/2003 ECE 551 Spring 2003 17
Layout Styles - 1 Technologies in terms of layout
styles:Adjustable Spacing
Megacells
Standard Cell
Gate Array - Channeled
…
…Fixed Spacing
Base Cell
![Page 18: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/18.jpg)
1/16/2003 ECE 551 Spring 2003 18
Layout Styles - 2 Technologies in terms of layout
styles:
…Base Cell
Gate Array - Channel-less
(Sea of Gates)
Gate Array - Structured …
…Fixed Embedded Block
![Page 19: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/19.jpg)
1/16/2003 ECE 551 Spring 2003 19
IC Costs - 1 An example: 10,000 gate circuit [1]
o Fixed costs Standard Cell - $146,000 Gate Array - $86,000 FPGA - $21,800
o Variable costs Standard Cell - $8 per IC Gate Array - $10 per IC FPGA - $39 per IC
![Page 20: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/20.jpg)
1/16/2003 ECE 551 Spring 2003 20
IC Costs - 2 An example: 10,000 gate circuit
0500,000
1,000,0001,500,0002,000,0002,500,0003,000,0003,500,0004,000,000
100 1000 10000 100000
StandardCellGateArrayFPGA
![Page 21: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/21.jpg)
1/16/2003 ECE 551 Spring 2003 21
IC Costs – 3 Why isn’t FPGA cheaper per unit due to economy-of-scale?
o The chip area required by each of the successive technologies from Full Custom to FPGAs increases for a fixed-sized design.o The larger the chip area, the poorer the yield of working chips during fabricationo Also, due to increased sales, FPGA prices have declined since the mid-90’s much faster than the other technologies.
![Page 22: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/22.jpg)
1/16/2003 ECE 551 Spring 2003 22
Draw DatapathSchematics *
ASIC Design Flow - Traditional
WriteSpecifications
Define SystemArchitecture
Partition - Data-path &Control
Define StateDiag/Tables
Draw ControlSchematics *
IntegrateDesign*
Do Physical Design*
Implement**Steps followed by validation and refinement
![Page 23: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/23.jpg)
1/16/2003 ECE 551 Spring 2003 23
Traditional Flow Problems Schematic Diagrams
o Limited descriptive power
State Diagrams and Algorithmic State Machines
o Limited portability
o Limited complexity o Difficult to describe parallelism
o Limited complexity
Time-Intensive and Hard to Update
![Page 24: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/24.jpg)
1/16/2003 ECE 551 Spring 2003 24
How about HDLs Instead of Diagrams? - 1
Hardware description languages (HDLs)o Computer-based programming languageso Model and simulate the functional behavior and timing of digital hardwareo Synthesizable into a technology-specific netlist
Two main HDLs used by industryo Verilog HDL (C-based, industry-driven)o VHSIC HDL or VHDL (Ada-based, defense/industry/university-driven).
![Page 25: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/25.jpg)
1/16/2003 ECE 551 Spring 2003 25
How about HDLs Instead of Diagrams? - 2 Advantages of HDLs
o Highly portable (text)o Describes multiple levels of abstraction
o Represents parallelism o Provides many descriptive styles
Structural Register Transfer Level (RTL) Behavioral
o Serve as input for synthesis
![Page 26: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/26.jpg)
1/16/2003 ECE 551 Spring 2003 26
How about Synthesis instead of Manual Design? Increased design efficiency
Reduces verification/validation problem
Ability to explore more of overall design space
Are there disadvantages?
Potential for better optimization
![Page 27: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/27.jpg)
1/16/2003 ECE 551 Spring 2003 27
HDL/Synthesis Design Flow - 1
Pre-SynthesisSign-Off
Verification:Functional
DesignSpecification
DesignPartition
Design Entry:HDL Behavioral
Integration
To next pageVerification:Functional
Synthesis andTechnology Map
![Page 28: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/28.jpg)
1/16/2003 ECE 551 Spring 2003 28
HDL/Synthesis Design Flow - 2
ExtractParasitics
Test Generation& Fault Simulation
Verification:Post-Synthesis
Timing Verification:Post-Synthesis
Physical Design
From prior page
Verification:Physical & Electrical Design Sign-Off
![Page 29: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/29.jpg)
1/16/2003 ECE 551 Spring 2003 29
An Example from Industry A G3 wireless processor was designed using
the following methodology: o Entire processor modeled and tested using
VHDL and C-based test programso Processor functionality verified by synthesizing
to an FPGA and running 3G wireless applications at 25 MHz
o Processor timing and design feasibility verified by synthesizing to a standard cell library and running applications at 500 MHz.
o Final version of processor implemented using a mix of standard cell and custom logic to achieve low-power and 800 MHz clock speed.
![Page 30: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/30.jpg)
1/16/2003 ECE 551 Spring 2003 30
Newer Technologies and Design Flows - SOC System-on-a-Chip (SoC)
o Designers use (Intellectual Property – IP) cores RISC Core, DSP, Microcontroller, Memory The main function is to glue many cores and
generate/design only those components for which cores and designs may not be available
Used in ASIC as well as custom design environment
The issues relevant to this will be discussed near the end of the course
![Page 31: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/31.jpg)
1/16/2003 ECE 551 Spring 2003 31
Synthesis andTechnology Map
Contemporary Design Flow - 1
Pre-SynthesisSign-Off
DesignSpecification
DesignPartition
Verification:Functional
To HDL/Synth Design Flow -2
Integration &Verification:Functional
Select IPCores
Design Entry:HDL Behavioral
PreliminaryPhys. Design
![Page 32: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/32.jpg)
1/16/2003 ECE 551 Spring 2003 32
Lecture 1.2 Summary Application Specific Integrated Circuit
(ASIC) Technologies o Provides a basis for what we will design
IC Costs o Gives a basis for technology selection
ASIC Design Flowso Shows the role of HDLs and synthesiso Provides a structure for
what we will learn What we will do
![Page 33: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/33.jpg)
1/16/2003 ECE 551 Spring 2003 33
References
1) Smith, Michael J. S., Application-Specific Integrated Circuits, Addison-Wesley, 1997.
![Page 34: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/34.jpg)
1/16/2003 ECE 551 Spring 2003 34
Lecture 1.3 Pragmatics 1 Pragmatics refers to practical design
choices and techniques Topics
o Cell Librarieso Asynchronous Circuitso Three-State Logic and Hi-Z State
![Page 35: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/35.jpg)
1/16/2003 ECE 551 Spring 2003 35
Cells and Cell Libraries What is a cell? What is a cell library? What appears in the cell library for
each ASIC cell?
![Page 36: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/36.jpg)
1/16/2003 ECE 551 Spring 2003 36
What is a Cell? Cells are the building blocks for digital designs Come in different sizes, shapes and functions
varying from transistors to large memory arrays or even a processor
Typically cells:o Small Scale: AND, OR, NAND, NOR, NOT, AOI, OAI,
Flip-Flops, Latcheso Medium Scale: Multiplexers, Decoders, Adderso Large Scale: Memories, Processors
Provided by ASIC vendors
![Page 37: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/37.jpg)
1/16/2003 ECE 551 Spring 2003 37
What is a Cell Library? A database specifying and describing
the target technology in the form of pre-designed objects called cells. Synthesis target technology.
In-Class Discussion: What are typical components in the database for each cell?
![Page 38: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/38.jpg)
1/16/2003 ECE 551 Spring 2003 38
Asynchronous Techniques Delay-dependent design Combinational hazards Combinational hazard prevention Asynchronous design
![Page 39: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/39.jpg)
1/16/2003 ECE 551 Spring 2003 39
Delay-Dependent Design 1LA
PA
A
A
LA
PA
Example: Level-to-Pulse Converter(Delay-Based)
![Page 40: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/40.jpg)
1/16/2003 ECE 551 Spring 2003 40
Delay-Dependent Design 2 Sometimes useful But should be avoided Time delays vary and so may:
o Failo Produce variable results, e. g. pulse
length
![Page 41: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/41.jpg)
1/16/2003 ECE 551 Spring 2003 41
Delay-Dependent Design 3
LAPA
D
QCClock
Level on LA must be longer than a clock period and must not rise close to the positive clock edge. Ideally, synchronous with Clock.
Level to Pulse Converter (Synchronous)
![Page 42: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/42.jpg)
1/16/2003 ECE 551 Spring 2003 42
Combinational Hazards 1 Example - Hazard in a Multiplexer
A
C
FB
1
1
B
F
![Page 43: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/43.jpg)
1/16/2003 ECE 551 Spring 2003 43
Combinational Hazards - 2
A circuit has a hazard if there exists an assignment of delays such that an unwanted signal transition (glitch), can occur.
Types of changes on combinational circuit inputs :o Single-input change (SIC) o Multiple-input change (MIC)
A SIC static hazard exists on a circuit output if in response to a SIC, the output momentarily changes to the opposite value. o Static 1-hazard – output value to remain at 1o Static 0-hazard – output value to remain at 0
![Page 44: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/44.jpg)
1/16/2003 ECE 551 Spring 2003 44
Combinational Hazards - 3 Classification of Combinational Hazards
o Static – SIC/MIC – output changes when it should remain fixed - output value within the “transition region of input changes is fixed.
o Dynamic – SIC/MIC – output changes three or more times when it should change only once.
o Essential – MIC – output changes when it should remain fixed – output value within the “transition region” of
input changes not fixed.
![Page 45: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/45.jpg)
1/16/2003 ECE 551 Spring 2003 45
Combination Hazards - 4 In-class Example: Illustration of
static, dynamic and essential hazards
![Page 46: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/46.jpg)
1/16/2003 ECE 551 Spring 2003 46
Combinational Hazards - 5 Consequences of Hazards
o Signals with hazards within or entering asynchronous circuits (note that a flip-flop is an asynchronous circuit with respect to its clock signal!)
o Cause incorrect state behavior Extra state changes Incorrect state changes
In-Class Example: Prevention of Hazardso Redundant Logico Delay Dependence
![Page 47: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/47.jpg)
1/16/2003 ECE 551 Spring 2003 47
Asynchronous Design - 1 Which of the following sequential circuits
involve asynchronous design?o A circuit that has no global clock signal involved in
its operation – state changes occur in response to input changes only.
o A D flip-flop circuito A circuit using clock gating on flip-flop clock inputso A circuit with a clock which uses the clear and
preset inputs on the flip-flops for other than initialization.
![Page 48: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/48.jpg)
1/16/2003 ECE 551 Spring 2003 48
Asynchronous Design - 2 Because of the difficulty of eliminating
hazards, it is very difficult to insure correct operation under all timing possibilities
Design must be done manually or by use of very specialized synthesis tools.
Therefore, avoid it if you can! If you truly need it, investigate some of
the more contemporary approaches[1] which avoid some of the many difficulties.
![Page 49: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/49.jpg)
1/16/2003 ECE 551 Spring 2003 49
Three-State and Other Hi-Z States Three-state conflicts Floating three-state nets and inputs Pull-ups and Pull-downs Bus keepers
![Page 50: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/50.jpg)
1/16/2003 ECE 551 Spring 2003 50
Three-State Conflicts - 1 What are they and what are their effects?
o Static – Chip damage or static power consumptiono Dynamic – Dynamic or static power consumption
1
1
1
0
D0
D1
E0
E1
OUT
E0E1
E0E1 1
1
11
0
0
![Page 51: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/51.jpg)
1/16/2003 ECE 551 Spring 2003 51
Three-State Conflicts - 2 How can conflicts be avoided?
o Static – Decoded enable signalso Dynamic – Delay control
1
1
0
D0
D1
E0
E1
OUT
E0E1
E0E1 1
1
01
0
0
![Page 52: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/52.jpg)
1/16/2003 ECE 551 Spring 2003 52
Floating Inputs and Three-State Nets - 1
Floating input values on gates can cause:o static power dissipation o high-frequency switching that induces power
supply noise Floating input values arise from:
o Gate inputs, e. g., for example on exterior of IC, that are not connected
o Lines driven by 3-state buffer or gate outputs, all of which are in the Hi-Z state.
![Page 53: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/53.jpg)
1/16/2003 ECE 551 Spring 2003 53
Floating Inputs and Three-State Nets – 2 How can floating inputs and nets be
avoided?o Use a pull-up or pull-down resistor or
transistor with a fixed gate voltage value. Advantage – simple Disadvantages – static power dissipation and
loading of nodeo On internal lines, particularly buses, use
a bus keeper (weak buffer)
![Page 54: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/54.jpg)
1/16/2003 ECE 551 Spring 2003 54
Non-D flip-flops D Flip-Flops
o Unique characteristic – the typical master-slave DFF is also functionally an edge-triggered DFF.
Non- D Flip-Flops (JK, T, etc.)o In the cell libraries, these flip-flop may be full-
custom designs or may simply consist of a DFF with added logic.
o If it is just a DFF with added logic, you might as well design for a DFF to give the logic optimization software more flexibility.
![Page 55: ECE 551: Digital System Design & Synthesis](https://reader035.fdocuments.in/reader035/viewer/2022062521/56814bb1550346895db88669/html5/thumbnails/55.jpg)
1/16/2003 ECE 551 Spring 2003 55
References
[1] Chris J. Myers, Asynchronous Circuit Design, John Wiley & Sons, Inc., New York, 2001.