ECE 551: Digital System Design &...

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ECE 551: Digital System Design & Synthesis

Lecture Set 99.1: Constraints and Timing

(In separate file)9.2: Optimization - Part 1

(In separate file)9.3: Optimization - Part 2

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ECE 551 - Digital System Design & SynthesisLecture 9.3 - Optimization and Timing Analysis - Part 2

OverviewControlling Hierarchical BoundariesControlling Logic-Level and Gate-Level Optimization

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References

Design Compiler User GuideDesign Compiler Reference Manual: Optimization and Timing Analysis

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Controlling Hierarchical Boundaries

Removing Levels of HierarchyMerging Cells from Different SubdesignsOptimizing Across Hierarchical Boundaries

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Removing Levels of Hierarchy

Optimization does not cross hierarchical boundaries

Potential for preventing effective optimizationParticularly problematic for combinational circuits

TechniquesUngroup before optimizationExplicit Ungrouping during optimizationAutomatic Ungrouping of Small Hierarchies

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Ungroup Before Optimization

Ungroup merges subdesigns into parent cell or designSome subdesigns may lose constraints The default ungroup affects only the top level of the hierarchy within the parent cell or subdesignTo recursively ungroup downward add option -flattenCommand: ungroup -all -flatten Can have list of arguments

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Explicit Ungroup During Optimization

Command: set_ungroup or ungroup _allApplies to specified cells or referenced designsCancelled by set_ungroup (object) false

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Automatic Ungrouping of Small Hierarchies

Set compile_auto _ungroup_num_cells # where # is limit on number of cells to be ungroup. Enter command compile -auto_ungroupCommand begins execution at the bottom of the current hierarchy so is in effect recurs.So ungrouping is recursiveWill not apply ungrouping in cases where:

Wire-load models in hierarchy different than parentCertain constraints are on hierarchical pins

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Merging Cells from Different Subdesigns

Groups cells into new designgroup {cell_1, cell2} -design cell_paircurrent_design = cell_pairungroup -allcurrent design = top design

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Optimizing Across Hierarchical Boundaries - 1

Boundary OptimizationCrosses subdesign boundary through ports looking for:

constantsunconnected pinscomplementing

Commands (in dc_shell)compile -boundary_optimization //on current designset boundary_optimization subdesign_name

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Optimizing Across Hierarchical Boundaries - 2

For constants:Propagate from input ports to contract logic

For unconnected pins:Propagate “x” from output ports to contract logic

For complements:If signal that is complement of one specified on port is available, it will be used if cost reduced

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Controlling Logic-Level and Gate-Level Optimization

ConceptsGoal to first order is reduction of product termsRelates to be delay and area Designs typically hierarchical and consist of structured and random logicDatapaths are often structured logicControl functions such as instruction decoding are structurally random

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Concepts (continued)

For effective optimization, may require application of different optimization techniques

Structured - Preserve and build on existing structureRandom - Remove redundancy and improve the structure

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How Design is Optimized - 1Two Levels

Logic level - Boolean equationsGate level - Interconnection of target library cells

Logic level optimizationFlattening - reducing the equation structure to two levelsStructuring - Finds shared terms to reduce area - typically increases delay if not constrained

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How a Design is Optimized - 2Gate-Level Optimization

Performs mapping of equation representation to available cells in the technology librarySelects cells based on delay constraints or area constraints

Overall OptimizationSee Fig. 4-3 DCRMO (next slide)FlatteningStructuringMapping

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Overall Optimization

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set_flatten & set_structureDefault settings

flatten falsestructure truestructure_boolean falsestructure_timing true- map_effort medium

Default settings for flatten attribute set to trueflatten trueflatten_effort lowflatten_minimize singleflatten_phase falsestructure truestructure_boolean falsestructure_timing true

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About Flattening

Flattening removes all intermediate variables and uses distributive laws to eliminate all parentheses. Result is a two-level sum-of-products formCan be faster due to reduced number of levelsGood way to eliminate bad logic structure; but also way to eliminate good logic structureFlatten random control logic, not highly-structured designs.

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About Flattening (continued)

Not all designs can be flattenedFlatten designs which do not result in a huge number of product terms < 1000Do not flatten designs with 1,000,000 or more product termsDesigns in between are unknown

GuidelinesIf outputs consistently true or false for most input patterns - flattenIf contains many XORs and muxes - don’t flatten

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Effect of Flattening on Speed

Example: Mapped flattened Design without Structuring - Fig. 4-5 DCRMO (see next slide) - three levels + inverters can be fastFlattening may place large loads on inputs resulting in speed reduction.Flattening without and with structuring -Fig. 4-6 DCUG (see slide after next) - one level vs. 5 levels

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Mapped, Flattened Design without Structuring

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Flattening With and Without Structuring

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Enabling & Controlling Flattening - 1

Default - does not flattenIn hierarchical design, flatten by default on the current design only - Exception -use design option with list of designsRemoving: set_flatten false -design TESTReporting Flatten Attributes -report_compile_options

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Setting Flatten Effort -effort option where option is:

low - default - appropriate for flattening most designsmedium - flattens a design beyond where DC can restructure it effectivelyhigh - causes the flattening process to proceed until the design is completely flattened or until workstation runs out of memory. Might never terminate!

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Enabling & Controlling Flattening -3

MinimizationReduces the number and size of product and sum termsResembles Karnaugh map reductionTypes:• single output -default - minimize equations for

individual outputs - no product term sharing• multiple output - minimize with maximum and

shared product terms between outputs - see Fig. 4-7 DCRMO (See next slide).

• none - does not perform minimization

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Single & Multiple Output Minimization

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Phase assignmentFig. 4-8 DCRMO (See next page)Compares and select implementations for both original circuit and its complementComplement handled and the fed into inverter.Well known that “less costly” version among the two

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Phase Assignment

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About StructuringAdds intermediate values and logic structure to design - sub-function factor evaluated and selectedResults in shared termsDefault - timing drivenArea efficient, but may be slower if no delay constraints or if set_structure -timing false.Example - Fig. 4-10 DCRMO (See next slide) -Unconstrained structuring - more area efficient, but has eight levels of logicExample - Fig. 4-11 DCRMO (See slide after next) - Timing Driven Structuring (Default)

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Unconstrained Structuring Example

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Timing-Driven Structuring Example

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Controlling Structuring - 1set_structure - applies only to current design unless -design option where option is list of subcircuitsboolean - optimization uses Boolean relationships that are not typically in our “usual” algebra & don’t care information and reduces circuit area. Examples: a + a = a, a + a’ = 1. Two algorithms

selected by compile_new_boolean_structure

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Controlling Structuring - 2Before v1997.01Introduced in v1997.01

Uses ATPG (Automatic Test Pattern Generation) to manipulate logic networks!Optimizes circuit identifying high fanout nodes and attempting removal.Adds connections that make original nodes redundant

Fig. 4-12 DCRMO (See next slide) -Boolean Optimization Example

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Boolean Optimization Example

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Improving Random Logic Designs

-boolean effort option for compile_new_boolean_structure trueset_structure - boolean -boolean_effort

Used to specify effort for CPU time use for structuring the designs:• low - default - appropriate for most• medium - More than one pass - recommended -

sufficient for optimal results for most design• high - All CPU-intensive strategies, multiple passes

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Controlling Specific Optimization Steps

Global logic restructuring Constant propagation - propagates logic constants to produce simpler logicDeleting unconnected gatesLocal optimizationsCritical path resynthesis (enabled in high-effort compiles only)Gate sizing - upsizes critical path gates and downsizes non-critical path gates

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Optimization Control Strategies for Structured Designs

Structured DesignsDatapath componentsArithmetic circuitsParity circuitsSelection circuits

GoalsAreaSpeed

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Structured Designs: Area Optimization - 1

Choice 1:compile

Is:flatten falsestructure truestructure_boolean falsestructure_timing true- map_effort medium

Generally favors multilevel design but can handle timing constraints

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Choice 2:set_structure falsecompileIs:flatten falsestructure false

Does mapping only Assumes logic-level optimization including structure (and structure_timing) not needed

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Choice 3:set_structure true -boolean true -

boolean_effort mediumcompile

Is:flatten falsestructure truestructure_boolean truestructure_timing true- boolean_effort medium- map_effort medium

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Choice 3: (continued)Does some re-structuringTakes advantage of don’t caresGets rid of some redundancy

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Table 4-3 DCRMO: Comparative Analysis for 32-bit CLA (See next slide)

Default reasonableBoolean optimization betterFlattening tends to destroy original structure, so not as goodIn this case, phasing of only marginal value

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Comparative Analysis for 32-bit CLA - Area

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Structured Designs: Speed Optimization - 1

Choice 1:compile


Timing-driven structuring optimizes critical paths which using structuring to reduce area

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Choice 2:set_structure falsecompileIs:flatten falsestructure false

Does mapping only Assumes logic-level optimization including structure (and structure_timing) not neededSame as Choice 2 for area!

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Choice 3:set_flatten true

set_structure true -boolean true - boolean_effort medium

compile

Is:flatten truestructure truestructure_boolean falsestructure_timing true- map_effort medium

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Choice 3: (continued)Removes existing structureReduces number of levels to improve timingUses timing-driven structuring to further deal with critical delay paths while optimizing area for non-critical paths

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Structured Designs: Speed Optimization - 5Table 4-4 DCRMO: Comparative Analysis for 32-bit CLA (See Next Slide)

Default reasonableFlattening plus structuring reduces delay a bitPhasing reduces delay moreFlattening only is counter-productive• Increases critical path delay and area• Removes structure and does not rebuild

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Comparative Analysis for 32-bit CLA - Speed

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Optimization Control Strategies for Unstructured Designs

Unstructured DesignsNo datapath componentsNo arithmetic circuitsNo large parity circuitsFew selection circuitsRandom control logic

GoalsAreaSpeed

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Unstructured Designs: Area Optimization - 1

Choice 1:compile


Timing-driven structuring optimizes critical paths while using structuring to reduce area

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Choice 2:set_flatten_truecompile


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Choice 3:set_flatten true

set_structure true -boolean true -boolean_effort mediumcompile

Is:flatten falsestructure truestructure_boolean truestructure_timing true-boolean_effort medium-map_effort medium

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Choice 4:set_flatten true -minimize multiple_output -phase

set_structure true -boolean true -boolean_effort mediumcompile

Is:flatten false-minimize multiple_output-phase truestructure truestructure_boolean truestructure_timing true-boolean_effort medium-map_effort medium

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Table 4-5 DCRMO: Comparative Analysis for PLA Design (See next slide)

Default reasonableFlattening with minimizing and structuring reduces area Boolean optimization and phasing gives further area improvement at the expense of delayNot phasing gives delay and slight area improvement!Not structuring is horrible!

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Comparative Analysis for PLA Design

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Unstructured Designs: Speed Optimization - 1

Choice 1:compile


Timing-driven structuring optimizes critical paths which using structuring to reduce area

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Choice 2:set_flatten_truecompile


Flattening provides a new start for structuring which may achieve improved area

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Choice 2 (continued):Removes existing structureReduces number of levels to improve timingUses timing-driven structuring to further deal with critical delay paths while optimizing area for non-critical paths

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Choice 3:set_structure falseset_flatten truecompile

Is:flatten truestructure false

Flattening without structuring reduces path length; area intensive

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Choice 4:set_structure false

set_flatten true - effort mediumcompile

Is:flatten true-effort mediumstructure false

More aggressive flattening without structuring reduces path length; area intensive

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Table 4-6 DCRMO: Comparative Analysis for PLA Design (See next slide)

Default reasonableWith Structuring• Flattening increases delay• Flattening with phasing gives slight delay

improvementWithout Structuring• Flattening reduces delay• Flattening with phasing increases delay!

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Comparative Analysis for PLA Design

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Summary

Many possible routes to chose from in synthesis proceduresDesign needs to be prepared for synthesis (uniquify, don’t touch, ungroup)Separation in synthesis for structured and random logicSpecific choices of optimization setting better for each

ECE 551: Digital System Design &...

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