ECE3829: Advanced Digital System Design using FPGAs 1

ECE 3829: Advanced Digital System Design using FPGAs A term 2017

Exam 3: October 12, 2017 (11.00 to 11.50)

Solutions

This exam is closed book (no books or notes or electronic devices allowed). A page of Verilog notes will be provided. Read each question carefully Use a standard and consistent coding style. Try and answer each question - if you consider any question to be ambiguous then state any assumptions you make.

NAME: ___________________________

ECE Box: ________________________

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Question 1 [15 marks]: Write a Verilog synthesizable description of a circuit with the inputs

and outputs as shown in the block diagram below (the ‘bus’ ports are all 16-bits in size):

When the output enable ‘OE’ signal is high then the ‘B_BUS’ bidirectional port should have the

value of the ‘A_BUS’ input port.

When the ‘OE’ signal is low then the ‘B_BUS’ port should go to tri-state.

On a rising edge of the load signal the value on the ‘B_BUS’ should be loaded into 16 flip-flops.

The output of the flip-flops should be connected to the output port ‘C_BUS’.

Example solution:

A_BUS

LOAD

OE

B_BUS

C_BUS

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Question 2 [30 marks]: Write a Verilog model of an SRAM memory device with the following

specifications:

Address bus: 6 bits.

Data bus: 16 bits

Control signals: CE_N, OE_N, WE_N.

Read operation:

Output the correct data only when OE_N and CE_N are both low, otherwise the data bus should

be set tristate. Delay the output by 70 ns to represent the memory access time.

Write operation:

Write data on the rising edge of WE_N but only if CE_N is low.

Timing check values: Twp: (45ns) minimum pulse width for write enable

Tds : (20ns) minimum time data must be valid before end of write

Tdh : (5ns) minimum time data must be valid after end of write

Include the following in your model:

a) Add two system timing check tasks to check for the data setup and hold times.

b) Write your own Verilog code (not a system task) to check the minimum pulse width for

the write enable and display an error message if this pulse width timing is violated (print

out the simulation time and by what margin the write pulse failed to meet the

specification).

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Example solution (with a few changes):

• Memory array size should be: reg [15:0] sram [0:63].

• Use of parameters was not required (could just use hard coded numbers)

• Toe = 70ns

The write pulse width check error message should be similar to:

$display(“Width of write pulse too short by %dns. Simulation Time = %dns”,

Twp – (Stime – tm_wr_falling), $time);

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Question 3 [30 marks]: An FPGA running off its own local 100MHz oscillator is connected to a

GPS device in another system with its own clock. The GPS device generates a 1PPS (one pulse

per second) signal that is high for approximately 5us duration that it sends to the FPGA. It is

necessary for the FPGA to generate a single 10ns pulse each time it detects the 1PPS pulse.

a) Assume that part of the FPGA has a simple state machine that uses the 1PPS signal to

determine if it should go into one state or another. If the 1PPS signal is not synchronized to

the FPGA clock domain it is possible that the state machine could go into an incorrect state.

Describe carefully how this is possible – include a simple schematic of the state machine

logic and a timing diagram as part of your description.

b) Write a synthesizable module description for the FPGA that will convert the 5us pulse from

the GPS device clock domain into the 10ns pulse inside the FPGA – remember to take into

account the possibility of metastability.

The start of the module description is provided (modify as required):

module short_pulse(

input clk_fpga, // 100 MHz FPGA clock

input pps_long, // long input pulse from GPS device

output pps_short // single 10ns pulse generated

);

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Question 4 [25 marks]: The following assign statement describes combinational logic that takes

in a set of five 8-bit inputs (a, b, c, d, and e) and carries out the operations to produce a 16-bit

output (f).

assign f = ((a | b) + c) * (d & e);

Assume that the four operations take the same amount of time to execute.

Write a synthesizable module description of a pipe-lined version to carry out the same operations

so that new output (f) values can be generated for each new set of input values (a, b, c, d and e).

How many flip-flops will be required to implement this pipe-lined version? _______56______

How many clock cycles will it take to produce a new output from a new set of inputs? ___3___

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