EC1312 Model Key

KEY - EC1312 – DIGITAL LOGIC CIRCUITS

R.M.D. ENGINEERING COLLEGER.S.M. NAGAR, KAVARAIPETTAI – 601 206.

B.E. B.TECH DEGREE MODEL EXAMINATION -FIFTH SEMESTER

ELECTRICAL AND ELECTRONICS ENGINEERING

EC1312 – DIGITAL LOGIC CIRCUITSDuration: 3 Hours Max. Marks: 100

KEY

PART – A (10 X 2 = 20)

1. Convert (53)10 to EX-3 code.

2 532 26 - 1 2 13 - 02 6 - 12 3 - 0

1 - 1

(53)10 = (110101)2

XS3 code equivalent to (53)10 = (110101)2 + (11)2 = (111000) 2

2. What is gray code? What are its applications?

The Gray code is unweighted and is not an arithmetic code; that is, there are no specific

weights assigned to the bit positions. The important feature of the Gray code is that it

exhibits only a single bit change from one code word to the next in sequence. This

property is important in many applications, such as shaft position encoders, where error

susceptibility increases with the number of bit changes between adjacent numbers in a

sequence.

3. What is a priority encoder?

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4. Expand the function f (A, B, C) =A +B’C to standard SOP form?

f (A, B, C ) =A +B'C = A ( B + B')(C + C' ) +( A + A')B'C = ABC + ABC' + AB'C+ AB'C' + AB'C+ A'B'Cf (A, B, C )= ABC + ABC' + AB'C+ AB'C' + A'B'C

5. How many FFs are required to design a mod-7 up down counter?

To design Mod – 7 up down counter, 3 Flip-flops are required.

6. Difference between Moore & mealy type sequential circuits.

Mealy Model:a. In the Mealy model, the outputs are functions of both the present state and inputs. b. The state table of a Mealy model sequential circuit must include an output section

that is a function of both the present state and inputs.c. In a Mealy model, the outputs may change if the inputs change during the

c1ockpulse period.

Moore Model:a) In the Moore model, the outputs are a function of the present state only. b) In the state table of a Moore model sequential circuit, there may be an output

section, but it will be a function of the present state only, because when the outputs are taken directly from the flip-flops, the state table can exclude the output section because the outputs are already listed in the present-state columns of the state table.

c) In a Moore model, the outputs of the sequential circuit are synchronized with the clock because they depend on only flip-flop outputs that are synchronized with the clock

7. What is race around condition?

A race condition is said to exist in an asynchronous sequential circuit when two or more binary state variables change value in response to a change in an input variable. When unequal delays are encountered, a race condition may cause the state variables to change in an unpredictable manner.

If the final stable state that the circuit reaches does not depend on the order in which the state variables change, the race is called a noncritical race. If it is possible to end up in two or more different stable states, depending on the order in which the state variables change, then it is a critical race. For proper operation, critical races must be avoided.

8. What is meant by state assignment?

State-assignment procedures are concerned with methods for assigning binary values to states in such a way as to reduce the cost of the combinational circuit that drives the flip-flops. the binary values of the states are immaterial as long as their sequence maintains the

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proper input-output relationships. For this reason, any binary number assignment is satisfactory as long as each state is assigned a unique number.

9. What are the difference between PLA and PAL?

10. What is the advantage of schottky TTL family?

The use of Schottky transistors in a TTL decreases the propagation delay without a sacrifice of power dissipation.

PART – B (5 X 16 = 80)

11. a) Obtain the minimum sop using QUINE - McCLUSKY method and verify using K-mapF=m0+m2+m4+m8+m9+m10+m11+m12+m13.

Group Column - I Column - II Column - III0 0000 0,2 00-0 0,2,8,10 -0-0 b'd'

0,4 0-00 0,4,8,12 --00 c'd'0,8 -000 0,8,2,10 -0-0

0,8,4,12 --00

2 0010 2,10 -010 b'cd' 8,9,10,11 10-- ab'4 0100 4,12 1-00 bc'd' 8,9,12,13 1-0- ac'8 1000 8,9 100- 8,10,9,11 10--

8,10 10-0 8,12,9,13 1-0-8,12 1-00 ac'd'

9 1001 9,11 10-1 ab'd10 1010 9,13 1-01 ac'd12 1100 10,11 101- ab'c

12,13 110- abc'

11 1011 13 1101

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(OR)

11. b) Reduce the Boolean function using k-map technique and implement using gates, f (w, x, y,z)= m (0,1,4,8,9,10) which has the don’t cares d (w, x, y, z)= m (2,11).

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12. a) i) Design a 2-bit magnitude comparator?

a) ii) Using 8 to 1mux, realize the Boolean function, T = F(w, x, y, z) =m (0,1,2,4,5,7,8,9,12,13)

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(OR)

12. b) Design a 4-bit adder /subtractor-using logic gates and explains its operation.4 Bit Adder and Subtractor:

Full Adder

4 bit adder:

Similarly implement Full Subtractor using the following Equations.

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13. a) i) Summarize the design procedure for synchronous sequential circuit.The design of a clocked sequential circuit starts from a set of specifications and

culminates in a logic diagram or a list of Boolean functions from which the logic diagram can be obtained. In contrast to a combinational circuit, which is fully specified by a truth table, a sequential circuit requires a state table for its specification. The first step in the design of sequential circuits is to obtain a state table or an equivalent representation, such as a state diagram.

A synchronous sequential circuit is made up of flip-flops and combinational gates. The design of the circuit consists of choosing the flip-flops and then finding a combinational gate structure that, together with the flip-flops, produces a circuit that fulfils the stated specifications. The number of flip-flops is determined from the number of states needed in the circuit. The combinational circuit is derived from the state table by methods presented in this chapter. In fact, once the type and number of flip-flops are determined, the design process involves a transformation from the sequential-circuit problem into a combinational-circuit problem. In this way, the techniques of combinational- circuit design can be applied.

Although intended to serve as a guide for the beginner, this procedure can be shortened with experience. The procedure is first summarized by a list of consecutive recommended steps:

1. The word description of the circuit behavior is stated. This may be accompanied by a state diagram, a timing diagram, or other pertinent information.2. From the given information about the circuit, obtain the state table.3. The number of states may be reduced by state-reduction methods if the sequential circuit can be characterized by input-output relationships independent of the number of states.4. Assign binary values to each state if the state table obtained in step 2 or 3 contains letter symbols.5. Determine the number of flip-flops needed and assign a letter symbol to each.6. Choose the t ype of flip-flop to be used.7. From the state table, derive the circuit excitation and output tables.8. Using the map or any other simplification method. derive the circuit output functions and the flip-flop input functions.9. Draw the logic diagram.

The word specification of the circuit behavior usually assumes that the reader is familiar with digital logic terminology. It is necessary that the designer use intuition and experience to arrive at the correct interpretation of the circuit specifications, because word descriptions may be incomplete and inexact. However, once such a specification has been set down and the state table obtained. it is possible to make use of the formal procedure to design the circuit.

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a) ii) Realize D and T flip flops using JK flip flops.

Realization of D flip-flop using JK Flip-flop

Realization of T flip-flop using JK Flip-flop

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(OR)

13. b) A sequential circuit has two D Flip-flops A and B an input x and output y is specified by the following next state and output equations.

A (t+1) = Ax + Bx; B (t+1 ) = Ax; Y = (A+B) x’(i) Draw the logic diagram of the circuit. (ii) Derive the state table. (iii) Derive the state diagram.

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14. a) Minimize the following state table.

(OR)

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14. b) Design an Asynchronous 4 bit up-down counter.

15. a) i) Discuss on the concept of working and applications of ROM, EPROM and PLA.

ROM: A ROM is a memory device that holds a fixed, addressable data set A ROM may be programmed by the designer A ROM has a fixed AND array (that decodes the memory address) followed by a

programmable OR array (outputs)

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For each of a given set of input combinations (address), it generates a multi-bit value which has been programmed into the device

The output functions need to be expressed in canonical minterm form for PROM implementation

o every input variable appears in each product term in its true or inverted form Each minterm is used to represent an address Each address generates a multi-bit output Typical uses include:

o Code converters, Character generators, Data storage tables, Program stores Loaded with tabular data – not Boolean equations

EPROM: Erasable Programmable ROM• Programmable component is a MOS transistor

– Transistor has “floating” gate surrounded by an insulator– (a) Negative charges form a channel between source and drain storing a logic 1– (b) Large positive voltage at gate causes negative charges to move out of channel

and get trapped in floating gate storing a logic 0– (c) (Erase) Shining UV rays on surface of floating-gate causes negative charges to

return to channel from floating gate restoring the logic 1– (d) An EPROM package showing quartz window through which UV light can pass

• Better write ability – can be erased and reprogrammed thousands of times

• Reduced storage permanence – program lasts about 10 years but is susceptible to radiation and electric noise

• Typically used during design development

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8 × 4 ROM

3×8

decoder

Q0Q3

A0

enable

A2

word 0

word 1

A1

Q2 Q1

programmable connection wired-OR

word line

data line

word 2

Internal view


PLA A PLA is a large 2-level AND / OR array with lots of inputs and product terms Most general/flexible device of this architecture

o PROM, PAL, PLA Programmable connections for both AND / OR Uses the sum of products (SOP) form

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(d)

(a)

(b) source drain

+15V

source drain

0V

(c) source drain

floating gate

5-30 min


a) ii) A combinational circuit is defined by the functions. F1 (a, b, c) = (3, 5, 6, 7) and F2

(a, b, c) = (0, 2, 4, 7) implement the circuit with a PLA.

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(OR)

15. b) Explain the characteristics and implementation of the following digital logic families.(i) TTL (ii) CMOS

(i) TTL

The original basic TTL gate was a slight improvement over the DTL gate. As the TTL technology progressed, additional improvements were added to the point where this logic family became the most widely used family in the design of digital systems. There are several subfamilies or series of the TTL technology. The names and characteristics of seven TTL series appear in Table 10-2. Commercial TTL lCs have a number designation that starts with 74 and follows with a suffix that identifies the series type.

Examples are 7404, 74S86, and 74ALS161. Fan-out, power dissipation and propagation delay were defined in Section 10-2. The speed-power product is an important parameter for comparing the various TTL series. This is the product of the propagation delay and power dissipation and is measured in picojoules (pJ). A low value for this parameter is desirable, because it indicates that a given propagation delay can be achieved without excessive power dissipation, and vice versa.

The standard TTL gate was the first version in the TTL family. This basic gate was then designed with different resistor values to produce gates with lower power dissipation or with higher speed. The propagation delay of a transistor circuit that goes into saturation depends mostly on two factors: storage time and RC time constants. Reducing the storage time decreases the propagation delay. Reducing resistor values in the circuit reduces the RC time constants and decreases the propagation delay. Of course, the trade-off is higher power dissipation because lower resistances draw more current from the power supply. The speed of the gate is inversely proportional to the propagation delay.

In the low-power TTL gate, the resistor values are higher than in the standard gate to reduce the power dissipation, but the propagation delay is increased. In the high-speed TTL gate, resistor values are lowered to reduce the propagation delay, but the power dissipation is increased. The Schottky TTL gate was the next improvement in the technology. The effect of the Schottky transistor is to remove the storage time delay by preventing the transistor from going into saturation. This series increases the speed of operation without an excessive increase in power dissipation.

The low-power Schottky TTL sacrifices some speed for reduced power dissipation. It is equal to the standard TTL in propagation delay, but has only one·fifth the power dissipation. Recent innovations have led to the development of the advanced Schottky series. It provides an improvement in propagation delay over the Schottky series and also lowers the power dissipation. The advanced low-power Schottky has the lowest speed-power product and is the most efficient series. It is replacing all other low· power versions in new designs.

All TTL series are available in SSI and in more complex forms as MSI and LSI components. The differences in the TTL series are not in the digital logic that they perform, but rather in the internal construction of the basic NAND gate. In any case, TTL gates in all the available series come in three different types of output configuration:

1. Open -collector output

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2. Totem-pole output3. Three-state (or tristate) output

(ii) CMOS CharacteristicsWhen a CMOS logic circuit is in a static state, its power dissipation is very low. This is because there is always an off transistor in the current path when the state of the circuit is not changing. As a result, a typical CMOS gate has a static power dissipation on the order of 0.01 mW. However, when the circuit is changing state at a rate of I MHz, the power dissipation increases to about 1 mW.

CMOS logic is usually specified for a single power-supply operation over the voltage range between 3 and 18 V with a typical VDD value of 5 V. Operating CMOS at a larger value of supply voltage reduces the propagation delay time and improves the noise margin, but the power dissipation is increased. The propagation delay time with VDD = 5 V ranges from 8 to 50 ns, depending on the type of CMOS used. The noise margin is usually about 40 percent of the VDD supply voltage. The fan-out of CMOS gates is 50 when operated at a frequency of less than I MHz. The fan-out decreases with increase in frequency of operation.

There are several series of the CMOS digital logic family (see Table 2-10). The original design of CMOS ICs is recognized from the 4000 number designation. The 74C series are pin- and function-compatible with TTL devices having the same number. For example, CMOS IC type 74C04 has six inverters with the same pin configuration as TTL type 7404. The performance characteristics of the 74C series are about the same as the 4000 series. The high-speed CMOS 74HC series is an improvement of the 74C series with a tenfold increase in switching speed. The 74HCT series is electrically compatible with TTL ICs., This means that the circuits in this series can be connected to inputs and outputs of TTL ICs without the need of additional interfacing circuits.

The CMOS fabrication process is simpler than TTL and provides a greater packing density. This means that more circuits can be placed on a given area of silicon at a reduced cost per function. This property of CMOS, together with its low power dissipation, excellent noise immunity, and reasonable propagation delay, makes it a strong contender for a popular standard as a digital logic family.

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EC1312 Model Key

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