INTRODUCTION Major advantage of digital over analog is the

ability to easily store large quantities of digital information and data.

Memory – store information in various forms and purposes such as control information, program instruction, data or as temporary storage.

In a digital computer, the internal memory stores instruction that tell the computer what to do under all possible circumstances so that the computer will do its job with a minimum amount of human intervention.

ARCHITECTURE OF MEMORY Primary memory

as internal memory. Communicate constantly with process. are RAM and ROM that operate in fast time but smaller capacity. Any program or data used by the program/process must be

reside in the internal memory. Other name – internal memory, main memory, working memory

and semiconductive memory. Secondary memory (auxiliary mem, disk mem, external

memory) called mass storage with massive amount of data without the

need of electrical power. Operates at slower speed, stores program and data that are not

currently being used by CPU. Typical secondary memory – floppy disk, CD-ROM, magnetic disk,

magnetic tape or MBM. Flash memory with higher speed and lower power consumption,

smaller size and non mechanical operation.

TYPES OF MEMORY

ROM Hold permanent data and data will not lost when electrical

power is turned off. Normal operation – data can only be read from it. No new

data can be written on it. Major used is in microcomputers as storage of program. When microcomputer is on, it immediately begin executing

the program stored in ROM. Other usage – any microprocessor controlled equipment or

any application where the ratio of read operation is higher then write.

Entering data in ROM is called programming / burning and can only be done in factory.

Types MROM – also refer as ROM. Programmable only once. At factory. PROM – programmable only, once. At lab. RMM – programmed and erased.

MROM Its storage location programmed by the manufacturer

according to the customer’s specifications. Process:

Mask (photographic negative) is used to control the electrical interconnections on the chip.

The mask is expensive, so it is economical for very large quantity of the same ROM.

MROM as Off-the-self devices – programmed with commonly used data such as mathematical table or character generator codes.

Disadvantages cannot be reprogrammed if the design is changes.

Overcome : EPROM. expensive for lower / small volume application. Overcome :

PROM.

PROM Programmed by the programmer not the factory. Overcome problem with ROM that expensive for small /

lower volume applications. Fusible-link PROMs is user-programmable. Once programmed, PROM same as MROM. Also called ‘one time programmable ROMs.’ Electrical construction:

Very similar with MROM but the base terminals are replaced by fusible-link.

User selectively blow any of fuse link to produce logic 0. Data is programmed or burned into an address location

by: Applying the address to the address pins. Placing the data at data pins. Applying high-voltage pulse to a special programming pins.

The process of burning and verifying an PROM done by using PROM programmer attach to a computer.

EPROM Erased and programmed as often as desired. Once programmed, EPROM acts as ordinary ROM. The

programming process involves the application of special voltage level to certain pins for an amount of time.

Electronic circuitry to store data: MOS transistor with a silicon gate that has no connection

(floating gate). Normal state – each transistor hold logic 1 (transistor off). Burn state – application of high voltage injects high energy

electrons into the floating gate. The traps energy (charges) keeps transistor on permanently even if the power (high voltage) is removed. Now the transistor hold logic 0.

How to select which address to be programmed with data?

EPROM Erased by exposing it to ultraviolet (UV) light

through a window in the chip in 15 to 20 minutes. The UV light produces a photocurrent from the

floating gate back to the silicon substrate or in other word, removing the stored charges (energy), turning the transistor off and hold logic 1.

The process will erase all cell (transistor) – disadvantages. Overcome by EEPROM.

EEPROM Using same floating-gate structure as EPROM but

with the addition of a very thin oxide region above the drain of MOS transistor. – produces electrical erasability.

Programming : A charge induces onto the floating gate, remain there

(trapped charge) even the power is removed. - (Logic 0) Erasing :

A charge induces onto the floating gate, removed the trapped charge. - (Logic 1)

The charge mechanism used very low current thus the programming and erasing can be done in circuit. – adv.

Other adv – the ability to electrically erase and rewrite individual bytes. (one address)

EAPROM

Allows data alteration at user selected location.

Erasing and reprogramming of data in EAPROM done on board without withdrawing from the socket.

The duration is varied between several ms to several seconds.

Alteration data done by applying electrical pulse.

RAM

Contents of RAM will be read or write many times as computer executes program.

Therefore, it require fast read and write cycle times so it will not slow down the operation. – adv.

Disadv – volatile (lose data when power off). Some CMOS RAMs use small amounts of power in the standby mode that they can be powered from batteries.

SRAM Flip-flops that will stay in given state indefinitely,

as long as the power in not interrupted. Available in bipolar or MOS technology. For higher speed, use BJT RAM. For higher capacity and lower power

consumption, use MOS RAM.

BJT NMOS1. Higher speed than NMOS.

1. Lower speed than BJT.

2. Higher capacity than NMOS.

2. Lower capacity than BJT.

3. More complex than NMOS.

3. Less complex than BJT.

4. Higher power consumption than NMOS.

4. Lower power consumption than BJT.

DRAM Fabricated using MOS technology. MOS technology - high capacity, low power

requirement and moderate operation speed. 1 cell = 1 MOS capacitor sized a few picofarads. Need refreshing circuitry. Due to periodic

recharging memory cells (capacitor). – disadv. Some DRAM have internal refresh control

circuitry by still need time to recharging. Structure of DRAM is in matrix format. Larger capacity (4x than SRAM) and lower power

consumption. (1/6 to 1/2)– adv. Lower cost/bit (20%-25%) – adv.

DRAM SRAM1. Higher capacity than SRAM.

1. Lower capacity than DRAM.

2. Lower power consumption than SRAM.

2. Higher power consumption than DRAM.

3. Need refresh circuitry. 3. No need for refresh circuitry.

4. Used in microcomputer.

4. Used in microprocessor controlled instrument and appliances that need small memory capacity requirement.

5. Cheaper than SRAM. (cost/bit)

5. Expensive than DRAM. (cost/bit)

6. Flip-flop 6. Capacitor

PIN CONNECTION OF RAM From memory capacity:

Address size Data size

Pins of memory chip: Chip capacity : 32 x 4 Data lines / pins (Dn)

4 bits : D0, D1, D2, D3

Address lines / pins (An) 32 memory location. Address lines is A0, A1, A2, A3, A4

Memory capacity / chip capacity 32 x 4 bits = 128 bits 1 byte = 8 bits, 128 bits = ?

2n = 32log 2n = log 32n log 2 = log 32n = log 32 log 2 = 5 A0, A1, A2, A3, A4

PIN CONNECTION OF RAM Control (R/W)

READ : data is output from memory, R/W = 0 WRITE : data is input into memory, R/W = 1

Memory Enable (ME) Enable : ME = 1 Disable : ME = 0

Pins layout:

EXAMPLE A memory chip with capacity of 128k x 8,

determine: Numbers of data lines Numbers of address lines Capacity in bit, byte and kbyte Draw the pins layout block diagram

Determine the capacity in bit, byte and kbyte of the following memory chip: 2k x 4 bits 8k x 6 bits 64k x 16 bits

MEMORY MAPPING A system has the following characteristics:

CPU 8 bit data bus and 16 bit address bus 12kbyte ROM 4kbyte I/O ports 16kbyte RAM

Address size = 2n = 216 = 64k = 65,536 locations with 8 bits data size.

MEMORY MAPPING 12kbyte ROM

Address size = 12288 locations 0 – 12287 = $0000 – $2FFF Address lines = A0 - A13

4kbyte I/O Address size = 4096 locations 12288 – 16383 = $3000 – $3FFF Address lines = A0 - A11

16kbyte RAM Address size = 16384 locations 16384 – 32767 = $4000 – $7FFF Address lines = A0 - A13

Unused ?

2n = 12klog 2n = log 12288n log 2 = log 12288n = log 12288 log 2 = 13.58 ~ 14 A0 – A13

Start address = 0End address = 0 + (12288-1) = 12287

Start address = 12288End address = 12288 + (4096-1) = 16383

MEMORY MAPPING 12kbyte ROM

Address size = 12288 locations 0 – 12287 = $0000 – $2FFF Address lines = A0 - A13

4kbyte I/O Address size = 4096 locations 12288 – 16383 = $3000 – $3FFF Address lines = A0 - A11

16kbyte RAM Address size = 16384 locations 16384 – 32767 = $4000 – $7FFF Address lines = A0 - A13

SOALANb) Based on the memory pin configuration 2k x 8,

determine the numbers of bit for address lines and data lines.

c) Build a memory map by referring to the data below:Address bus = 22 bitData bus = 16 bitROM = 64kRAM = 512kI/O = 12kUnused = ______

A system has the following characteristics: 16 bit data bus and 22 bit address bus 64k ROM 12k I/O 512k RAM

Address size = 2n = 222 = 4M = 4194304 locations with 16 bits data size.

Start address = $000000End address = $3FFFFFF

64k ROM Address size = 65536 locations 0 – 65535 = $0000 – $FFFF Address lines = A0 - A15

12k I/O Address size = 12288 locations 65536 – 77823 = $10000 – $12FFF Address lines = A0 – A13

512k RAM Address size = 524288 locations 77824 – 602111 = $13000 – $92FFF Address lines = A0 – A18

Unused $93000 - $3FFFFF Address lines = A0 – A18

ADDRESS DECODER Accessing memory at one time means we just

need to point to a specific location. Therefore, we need to activate only the appropriate memory chip. This is done by address decoder.

ADDRESS DECODER Decoder is a device to accept n bits of input

and produce 2n bits of output.

2 to 4 decoder

ADDRESS DECODER 3 to 8 decoder

HOW TO DESIGN ADDRESS DECODER`` Identify how many memory chips and its

capacity.

Draw the memory map.

Memory Chip Capacity of ChipPROM - 0 2k x 8PROM - 1 2k x 8PROM - 2 2k x 8PROM - 3 2k x 8

Memory location :Start address = $0000End address = $1FFFSum of location = $2000 = 8192 location

Address lines :2n = 8192n = log 8192 = 13 log 2Memory: A0 – A12

PROM location :2k = 2 x 1024 = 2048 location

Address lines :2n = 2048log 2n = log 2048n log 2 = log 2048n = log 2048 = 11 log 2Each PROM : A0 – A10

HOW TO DESIGN ADDRESS DECODER Address lines table

HOW TO DESIGN ADDRESS DECODER Address lines table

COMPLETE ADDRESS DECODER

TIMING DIAGRAM Static RAM Timing

RAM ICs often used as the internal memory of a computer.

This memory chips have to be fast enough to respond to the CPU read and write commands.

However, computer designer has to be concerned with the RAM’s various time characteristics.

To understand the characteristics, we need to examine the timing diagram.

READ CYCLE At t0, CPU put address at address bus (address input) and R/W* set to 1. After the address bus is stable, CPU set CS* to 0 (active). RAM responds by placing the data onto data output (bus data) at t1. tACC = RAM’s access time. tCO = time from CS* active to data valid in data bus. At t2, CS* is set to 1 (inactive). t1 to t3 is the time for CPU take data from data bus. After tOD, data output will be in Hi-Z. tRC is time for read cycle complete; t0 to t4.

WRITE CYCLE At t0, CPU put address at address bus (address input). CPU wait after tAS to set R/W* and CS* to 0 (active). R/W* and CS* will set low for tw (write time interval). At t1, CPU will set data at data bus (data input). R/W* and CS* need to stay low for tDS(data setup time). For RAM to write data:

Data at data bus must valid for tDH. Address at address bus must valid tAH from t2.

tWC is time for read cycle complete; t0 to t4.

READ AND WRITE CYCLE If memory has tRC of 50ns and CPU can read

one word at one time, CPU can read 20 millions words / second.

DRAM READ/WRITE CYCLES Timing diagram read and write for DRAM is

more complex.

READ CYCLE t0: MUX is driven LOW to apply the row address bits (A0 to A6) to the

DRAM address inputs. t1: RAS is driven LOW to load the row address into the DRAM. t2: MUX goes HIGH to place the column address (A7 to A13) at the

DRAM address inputs. t3: CAS goes LOW to load the column address into the DRAM. t4: The DRAM response by placing valid data from the selected

memory cell onto the DATA OUT line t5: MUX, RAS, CAS and DATA OUT return to their initial state.

WRITE CYCLE t0: The LOW at MUX place the row address at the DRAM

inputs. t1: The LOW at RAS loads the row address into the DRAM. t2: MUX goes HIGH to place the column address at the DRAM

input. t3: The LOW at CAS loads the column address into the DRAM t4: Data to be written are placed on the DATA IN line. t5: R/W is pulse LOW to write the data into the selected cell. t6: Input data are removed from DATA IN. t7: MUX, RAS, CAS and R/W are returned to their initial

states.