E3 239 Advanced VLSI Circuits High-Performance SRAM Design
Transcript of E3 239 Advanced VLSI Circuits High-Performance SRAM Design
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E3 239 Advanced VLSI Circuits
High-Performance SRAM Design
Rahul Rao
IBM Systems and Technology Group
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Introduction to memory
SRAM basics and bitcell array (refresher)
Current Challenges
Alternative Cell Types (6 to 10T), Asymmetric Cells, Sub-
threshold Cells, Low – leakage cells
Impact of Variation, Assist Circuits
BTI and impact on SRAMs
Power
Topics
Slide 1
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Memory Classification revisited
Slide 2
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Technology choices for memory hierarchy
Performance
Cost
~9F2
~4.5F2
Tbits/in2
6-8F2 ~120F2
Cost
NOR FLASH
NAND FLASH
DRAM
SRAM
Hard Disk
Chart: J.Barth
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Cache Sizes
Oracle T5,
ISSCC 2013
IBM System Z,
ISSCC 2013
Co
re L2
Co
re L2
Co
re L2
Co
re L2
Co
re L2
Co
re L2
Co
re
L2 Co
re
L2 Co
re
L2 Co
re
L2 Co
re
L2 Co
re
L2
L3 Cache & Chip Interconnect
8M
L3
Regi
on Mem. Ctrl. Mem. Ctrl.
SM
P L
inks
Accelerato
rs S
MP
Lin
ks P
CIe
IBM POWER8
Hotchips 2013
64kB L1 D$, 512 KB
SRAM shared L2 / core
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Cache size impacts cycles-per-instruction
For a 5GHz processor, scale the numbers by 5x
Several memory blocks in a typical processor core: I$, D$, Address translation
tables, Branch history tables, all in the KB – low MB range
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Embedded DRAM Performance
45nm eDRAM vs. SRAM Latency
00.20.40.6
0.81
1.21.41.61.8
22.2
2.42.62.8
3
1Mb 4Mb 8Mb 16Mb 32Mb 64Mb
Memory Block Size Built With 1Mb Macros
De
lay
(n
s)
eDRAM Total LatencySRAM Total LatencyeDRAM Wire/Repeater DelaySRAM Wire/Repeater Delay
eDRAM Faster than SRAM
Barth ISSCC 2011
Slide 6
Region of interest
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Introduction to memory
SRAM basics and bitcell array (refresher)
Current Challenges
Alternative Cell Types (6 to 10T), Asymmetric Cells, Sub-
threshold Cells, Low – leakage cells
Impact of Variation, Assist Circuits
BTI and impact on SRAMs
Power
Topics
Slide 7
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Memory Architecture
• 2n words of 2m bits each, If n >> m, fold by 2k into
fewer rows of more columns
• Good regularity – easy to design
• Utilization = Cell Area / (Cell + Periphery Area)
row
decoder
column
decoder
n
n-kk
2m bits
column
circuitry
bitline conditioning
memory cells:
2n-k rows x
2m+k columns
bitlines
wordlines
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9
Physical Arrangement
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AL AR
NL NR
PR PL
Large N: Better READ performance. If too large, trip voltage of inverter becomes so low
that cell becomes unstable.
Large A: Better Performance. If too large, storage node voltage goes high during READ,
causing cell flip
Large P: Increase stability. If too large, hard to WRITE
Need to balance all : NR:XR:PR ~ 2:1:1
The Balancing Act
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Access Xr : Off
Data Retained, due
to back-to-back
inverters
Workhorse 6T-Cell
WL=VDD
BL=VDD BLb=VDD
1 0
READ
Iread
WL=0
BL=VDD BLb=VDD
1 0
HOLD
Access Xr
Acess Xr: On
BL, Blb pre-conditioned,
and then floated, one
line discharges thru the
cell (Iread), voltage
sensed, Data Retained
Access Xr: On
Data driven on bit - lines
Data Flipped by over-
coming pull-up / pull –
down Xrs
WL=VDD
BL=GND BLb=VDD
WRITE
1 -> 0 0->1
Pull Up Xr Pull down Xr
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NMOS PMOS
Thin Cell (Litho-Friendly)
R0
MX
MY
R180
Flip
Flip Flip
Cell area vital for density
Cell symmetry equally useful
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Decoders and Drivers
Word line driver layout needs to be pitch matched to SRAM cell
WL driver
WL driver
cell cell cell cell
cell cell cell cell
WL driver
WL driver
cell cell cell cell
cell cell cell cell
Column Circuitry Decoder and
Control
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Column Circuitry for Read and Write
READ WRITE
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Sense Amplifiers bit_bbit
sense sense_b
sense_clk isolation
transistors
regenerative
feedback
clk
BL BLb
Sense-amp provide necessary gain (small input large output) for read If sense_clk arrives too early False read may
happen due to too small difference
If sense_clk arrives too late Too slow
Isolation transistors: Disconnects sense amp to
cutoff large bit line capacitance once sensing
starts
Three- high stack, but no isolation devices needed
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Hierarchical Bit-lines and Pre-Conditioning
Pre-Conditioning
bit bit_b
bit bit_b
Precharge
Equalizer
Hierarchical Bit-lines
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Prevents multiple-bit soft error
Better aspect ratio
selected column non-selected column
WL
Column Select and Half-Select Issue
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Introduction to memory
SRAM basics and bitcell array (refresher)
Current Challenges
Alternative Cell Types (6 to 10T), Asymmetric Cells, Sub-
threshold Cells, Low – leakage cells
Impact of Variation, Assist Circuits
BTI and impact on SRAMs
Power
Topics
Slide 18