Commercial DSP

• TMS320C25----TI• DSP5600--------Motorola• ADSP2100------Analog Device’s

• TI developed first commercial DSP in 1982• TMS32010

TMS320C54XX

• Fixed point DSP• Suitable for audio application• TMS-Texas Manufactured Semiconductor• C-CMOS• 320 is family• 54XX series

Features of 54x DSPs include:• Advanced multi-bus architecture with 3 separate 16-bit data memory buses 1 program memory bus• 40-bit arithmetic logic unit (ALU), including a 40-bit barrel

shifter • two independent 40-bit accumulators (A & B)• 17- × 17-bit parallel multiplier with a 40-bit dedicated adder

for cycle multiply/accumulate (MAC) operation• Compare, select, and store unit (CSSU) • Exponent encoder to compute an exponent value• data address generators(DAGEN) with its own arithmetic unit 8 auxiliary registers(AR0-AR1) & 2 auxiliary register arithmetic

units (ARAU0&ARAU1)• Program address generation unit

Special instructions

• Single-instruction repeat and block-repeat operations for program code

• Block-memory-move instructions for better program and data management

• Instructions with a 32-bit-long word operand• Instructions with two- or three-operand reads• Arithmetic instructions with parallel store and parallel

load• Conditional store instructions• Fast return from interrupt

On-chip peripherals• Phase-locked loop (PLL) clock generator with

internal crystal oscillator or external clock source

• Full-duplex standard serial port• Time-division multiplexed (TDM) serial port• Buffered serial port (BSP)• Multichannel buffered serial port (McBSP)• Direct memory access (DMA) controller• 8-bit parallel host-port interface (HPI)

Bus Structure (16-bit):• Program bus pair (PAB, PB):carries the

instruction code from the program memory.• Three data bus pairs (CAB, CB; DAB, DB; and

EAB, EB): 1. which interconnected to various units within the CPU. 2. pair CAB, CB and DAB, DB are used to read from the data memory, while 3. The pair EAB, EB; carries the data to be written to the memory 4. DAGEN generates 2 data address in 1 cycle

Central Processing Unit (CPU)Contains: • A 40-bit arithmetic logic unit (ALU)• Two 40-bit accumulators• A barrel shifter• A 17 × 17-bit multiplier/adder• A compare, select, and store unit (CSSU)

CPU

Arithmetic Logic Unit (ALU)• perform 2s-complement arithmetic using a 40-

bit ALU & two 40-bit accumulators (ACCA and ACCB).

• The ALU can perform Boolean operations.• The ALU can function as two 16-bit ALUs and

perform two 16-bit operations simultaneously when the C16 bit in status register 1 (ST1) is set.

AccumulatorsThe accumulators, A and B• store the output from ALU or multiplier / adder block• the accumulators can also provide a second input to the ALU or the multiplier / adder.accumulator is grouped as• Guard bits (bits 32–39)• A high-order word (bits 16–31)• A low-order word (bits 0–15)

Barrel Shifter

Barrel Shifter(40-bit)• barrel shifter has a 40-bit input connected to the accumulator or

data memory (CB, DB) and a 40-bit output connected to the ALU or data memory (EB).

• The barrel shifter produces a left shift of 0 to 31 bits & a right shift of 0 to 16 bits on the input data.

• The shift requirements are defined in the shift-count field (ASM) of ST1 or defined in the temporary register (TREG), which is designated as a shift-count register.

• shifter and the exponent detector normalize the values in an accumulator in a single cycle.

• The least significant bits (LSBs) of the output are filled with 0s and the most significant bits (MSBs) can be either zero-filled or sign-extended, depending on the state of the sign-extended mode bit (SXM) of ST1.

• Additional shift capabilities enable the processor to perform numerical scaling, bit extraction,

extended arithmetic, and overflow prevention operations.

MAC

MAC• The multiplier / adder performs 17 × 17-bit 2s-complement

multiplication with a 40-bit accumulation in a single instruction cycle. The multiplier / adder block• Consists : a multiplier, adder, signed/unsigned input control, fractional control, a

zero detector, a rounder (2s-complement), overflow/saturation logic, and TREG.

• The multiplier has two inputs: 1 input from TREG, a data-memory operand, or an accumulator; other is selected from the program memory, the data memory, an

accumulator, or an immediate value. • the multiplier and ALU together execute multiply/accumulate (MAC) computations.• The fast on-chip multiplier allows to perform operations such as convolution, correlation, and filtering efficiently.

Compare, Select, and Store Unit CSSU) • unit (CSSU) performs maximum comparisons between the accumulator’s high and low

words, allows the test/control (TC) flag bit of status register 0 (ST0) and the transition (TRN) register to keep their transition histories, and selects the larger word in the accumulator to be stored in data memory.

3 Control registers

• Status registers (ST0,ST1): contain the status of the various conditions and modes. Bits of ST0&ST1registers can be

• set or clear with the SSBX & RSBX instructions.• PMST: Contains memory-setup status: controls

memory configurations

Status register0 ST0):

• ARP: Auxiliary register pointer.• TC: Test/control flag.• C: Carry bit.• OVA: Overflow flag for accumulator A.• OVB: Overflow flag for accumulator B.• DP: Data-memory page pointer.

Status register1 (ST1)

• BRAF: Block repeat active flag BRAF=0, the block repeat is deactivated. BRAF=1, the block repeat is activated.

• CPL: Compiler mode CPL=0, the relative direct addressing mode using data page pointer

is selected. CPL=1,the relative direct addressing mode using stack pointer is

selected.

• HM: Hold mode indicates whether the processor continues internal execution or acknowledge for external interface

• INTM: Interrupt mode it globally masks or enables all interrupts. INTM=0 all unmasked interrupts are enabled. INTM=1 all masked interrupts are disabled.

• 0: Always read as 0

• OVM: Overflow mode. OVM=1 the destination accumulator is set either the most

positive value or the most negative value. OVM=0 the overflowed result is in destination accumulator.

• SXM: Sign extension mode.• SXM=0 Sign extension is suppressed.• SXM=1 Data is sign extended

• C16: Dual 16 bit/double-Precision arithmetic mode. C16=0 ALU operates in normal 40-bit mode. C16=1 ALU operates in dual 16-bit arithmetic mode.

• FRCT: Fractional mode. FRCT=0 integer multiplication FRCT=1 the multiplier output is left-shifted by 1bit to

compensate an extra sign bit.

• CMPT: Compatibility mode. CMPT=0 ARP is not updated in the indirect addressing

mode. CMPT=1 ARP is updated in the indirect addressing mode.

• ASM: Accumulator Shift Mode. 5 bit field, & specifies the Shift value within -16 to 15 range.

Processor Mode Status Register (PMST)

• INTR: Interrupt vector pointer, point to the 128-word program page where the interrupt vectors reside.

• MP/MC: Microprocessor/Microcomputer mode, MP/MC=0, the on chip ROM is enabled. MP/MC=1, the on chip ROM is enabled.• OVLY: RAM OVERLAY, OVLY enables on chip dual

access data RAM blocks to be mapped into program space

• AVIS: It enables/disables the internal program address to be visible at the address pins.

• DROM: Data ROM, DROM enables on-chip ROM to be mapped into data space.

• CLKOFF: CLOCKOUT off.

• SMUL: Saturation on multiplication.• SST: Saturation on store.

Memory Organization • memory is organized into 3 selectable spaces:

program, data, and I/O spaces• contain both RAM and ROM. RAM can be

either dual-access type (DARAM) or single-access type (SARAM).

• The on-chip RAM for these processors is organized in pages having 128 word locations on each page

• The CPU registers and peripherals registers are all located on page 0 of the data memory