J. Cent. South Univ. (2014) 21: 587−592 DOI: 10.1007/s11771-014-1977-5

Double-gate tunnel field-effect transistor: Gate threshold voltage modeling and extraction

LI Yu-chen(李妤晨), ZHANG He-ming(张鹤鸣), HU Hui-yong(胡辉勇), ZHANG Yu-ming(张玉明), WANG Bin(王斌), ZHOU Chun-yu (周春宇)

Key Laboratory for Wide Band-Gap Semiconductor Materials and Devices,

School of Microelectronics, Xidian University, Xi’an 710071, China

© Central South University Press and Springer-Verlag Berlin Heidelberg 2014

Abstract: The tunnel field-effect transistor (TFET) is a potential candidate for the post-CMOS era. As one of the most important electrical parameters of a device, double gate TFET (DG-TFET) gate threshold voltage was studied. First, a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported. Then, a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film. The model as a function of the drain voltage, the Si layer thickness, the gate length and the gate dielectric was discussed. It is shown that the proposed model is consistent with the simulation results. This model should be useful for further investigation of performance of circuits containing TFETs. Key words: tunnel field-effect transistor; gated P-I-N diode; threshold voltage; modeling; extraction

1 Introduction

In CMOS technology, as the device dimensions have scaled down from micrometer feature size to the nanometer regime, some two-dimensional effects become increasing important. In this view, the exploration of new devices is needed. The tunnel field-effect transistors (TFETs) [1−8], based on band-to-band tunneling (BTBT) mechanism, show great promise, which have the potential for steeper subthreshold slope [9] and lower off-current. Therefore, they seem well adapted to be candidates for low power applications [10]. However, TFETs suffer from a low on-current. Recently, many research groups from across the world have reported many proposed devices designed to overcome the on-state current limitation. Double gate TFET (DG-TFET) with high-κ dielectric is an effective way to improve the on-current, while taking advantage of steeper subthreshold slope and lower off-current [5], and is also compatible with already-existing fabrication technology.

So far, the investigation of TFETs performance and the optimization of TFETs structure are focused on TCAD simulations and experiments. Analytical models

can provide fast results, which should be helpful to design, simulate and fabricate the TFETs. However, there are only fewer models regarding current and subthreshold swing proposed for TFETs [9, 11−12]. The reason is that the physics of TFETs is significantly different from traditional MOSFETs. DG-TFET gate threshold voltage, as one of the most important electrical parameters of a device, is more connected to the nanoscale physics process. Consequently, this parameter deserves our particular attention.

In this work, a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported. The characteristics of DG-TFET were optimized by setting the following parameters: single or double gate, different gate dielectric materials, silicon body thickness and gate length. Due to its different mechanism, the transconductance change (TC) method was used to extract DG-TFET gate threshold voltage based on our simulation results. Then, a simple analytical model for the gate threshold voltage was proposed based on its physical definition and the influence of electrical parameters including the drain bias, the Si layer thickness, the gate length and the gate dielectric on gate threshold voltage VTG were discussed. The model can

Foundation item: Project(P140c090303110c0904) supported by NLAIC Research Fund, China; Project(JY0300122503) supported by the Research Fund for

the Doctoral Program of Higher Education of China; Projects (K5051225014, K5051225004) supported by the Fundamental Research Funds for the Central Universities, China; Project(2010JQ8008) supported by the Natural Science Basic Research Plan in Shaanxi Province of China

Received date: 2012−09−12; Accepted date: 2013−01−11 Corresponding author: LI Yu-chen, PhD; Tel: +86−18192045690; E-mail: yuchenlee09@gmail.com

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predict the improved performance on the physical gate threshold voltage when using high-κ dielectrics and thin Si film and the limited effect on gate threshold voltage when scaling the gate length. It is also shown that the model proposed in this work can be used as an efficient tool for design, simulation and fabrication of DG-TFET. 2 Simulation and gate threshold voltage

extraction

Lateral n-type DG-TFET with a structure shown in Fig. 1 was simulated using Silvaco Atlas. Junctions were ideally abrupt with the doping concentration Ns= 1020 cm−3 in the P+-type source, Nd=1018 cm−3 in the N-type drain and Ni=1016 cm−3 in P－/N－-type body. The gate work function was ΦM=4.5 eV. The simulations used a very fine mesh across the region where the tunneling took place. Gate leakage was neglected in these simulations.

Fig. 1 Schematic representation of N-type DG-TFET

The basic structure of DG-TFET is a gated P-I-N

diode with a lightly P-type or N-type doping for intrinsic region. To switch the device on, the P-I-N diode is reverse biased, and a voltage is applied to the gates (in our simulation as shown in Fig. 1, the source is grounded and a positive voltage is applied to the drain). For N-type DG-TFET, the P+-type region is the source, and the N-type region is the drain. When the positive gate

voltage applied to the N-type DG-TFET increases, the energy barrier width for band-to-band tunneling is narrowing, and the device is in the on-state.

For MOS transistors, the physical definition of the threshold voltage is the gate voltage marking the density of carriers in the inversion channel at the surface equals the doping level in the substrate, φs=2φF. While for tunnel FETs, the physical definition of the gate threshold voltage is the gate voltage which mark the transition between the strong control and weak control of the tunneling energy barrier width at the tunnel junction [13]. Since the mechanism of TFETs is significantly different from traditional MOSFETs, until now the threshold voltage has been extracted using the constant current method at the gate voltage for which Ids=10−7 A/μm [3, 5], arbitrarily value suggested by CMOS experience. The transconductance change method defines the threshold voltage of any non-linear device as the gate voltage, which corresponds to the maximum of the transconductance derivative, i.e., dgm/dVgs ).d/d( 2

gs2DS VI

This derivative method of threshold voltage extraction locates the voltage where there is a transition between strong and weak controls of the tunneling energy barrier width. Thus, the TC method was used to extract the gate threshold voltage (already verified for the MOS-FETs [14]) of DG-TFET in this work.

When changing from the single gate to the double gate structure, the TFETs can benefit from this added gate, such as the on-current can be boosted. This can be seen in Fig. 2(a) for a device with Lg=100 nm, tsi=10 nm, tox=3 nm and εox=21 simulated both as single-gate on SOI and as double-gate. The gate threshold voltage can also be reduced by using the double gate configuration as shown in Fig. 2(b), in which the gate threshold voltage was extracted using TC method. By the careful choice of a gate dielectric, the on-state current can be improved and the gate threshold voltage can decrease. As shown in Figs. 3(a) and (b), current increases as the gate dielectric

Fig. 2 IDS versus Vgs (Transfer characteristics for double and single gate TFET): (a) Vds=1 V; (b) VTG extraction: dgm/dVgs

(dIDS2/dVgs

2)

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constant increases, while threshold voltage decreases. DG-TFET characteristics are sensitive to the Si layer thickness, as shown in Figs. 4(a) and (b) in which on-current increased and the gate threshold voltage decreased with the thinner Si layer. There is little effect on the transfer characteristic of DG-TFET as long as the

device is longer than some critical length at which too much P-I-N leakage current occurs in the off-state, as shown in Fig. 5(a). In Fig. 5(b), the derivatives of transconductance for Vds=1 V were reported. We can see that the gate length has limited effect on the gate threshold voltage.

Fig. 3 IDS versus Vgs (Transfer characteristics for DG-TFETs with three different gate dielectrics): (a) Vds=1 V; (b) VTG extraction:

dgm/dVgs (dIDS2/dVgs

2)

Fig. 4 IDS versus Vgs (Transfer characteristics for DG-TFETs with three different Si film thicknesses): (a) Vds = 1 V and εox = 21;

(b) VTG extraction: dgm/dVgs (dIDS2/dVgs

2)

Fig. 5 IDS versus Vgs (Transfer characteristics for DG-TFETs with three different gate lengths): (a) Vds = 1 V and εox = 21; (b) VTG

extraction: dgm/dVgs (dIDS2/dVgs

2)

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3 Gate threshold voltage modeling

Analytical gate threshold voltage model can provide fast results, which is useful to design, simulate and fabrication of TFETs. In this part, DG-TFET gate threshold voltage model was mainly studied. DG-TFET gate threshold voltage VTG is the gate voltage, which marks the transition between the strong control and weak control of the tunneling barrier width at the tunnel junction. This inflection point in tunneling barrier width at the tunnel junction is defined as wbs [13,15]. In order to derive the gate threshold voltage model, the quasi-two-dimensional Poisson equation for the channel potential and electric field was solved firstly.

The equations will be established for the N-type DG-TFET as shown in Fig. 1. The gate length (Lg), the gate oxide thickness (tox), the Si film thickness (tsi), the source doping (Ns), the P－or N－ region doping (Ni), the drain doping (Nd) and the gate work function (ΦM) are the input parameters of this proposed model.

By applying Gauss’s law to the lightly P-type doped region as shown in Fig. 1 and neglecting the mobile charge in this region, the following equation can be derived as

gs sf gs sbsi si sfox ox i si

ox ox

( ) ( )( )+ + =

V y V yt E yqN t

y t t

0≤y≤Lg (1) where Esf(y) and φsf(y) are the electric field and potential at the top oxide–semiconductor interface, respectively; φsb(y) is the potential at the bottom oxide–semiconductor interface; gsV Vgs–ΦMS, ΦMS=ΦM–ΦS; ΦS is the semi- conductor work function and can be written as ΦS= χsi+Eg/2+ФF, the permittivities of silicon and oxide are εsi and εox, respectively. η is the channel region spreading parameter that is a weak function of channel doping and thickness, and can be extracted from simulation or experiment. Therefore, η is considered as a constant value for a given technology. (Its value usually varies between 1.0 and 1.3 [16−17]). As long as the doping level is less than 1017 atoms/cm3, the exact type and concentration in intrinsic region is not important. In this work, the intrinsic region was the lightly doped P－

region. The right-hand side of Eq. (1) represents the total

charge inside the Gaussian box and the first term on the left-hand side is equal to the net electric flux entering the Gaussian box in the y-direction. The second and third terms on the left-hand side of Eq. (1) represent the electric flux entering the top surface and bottom surface of the Gaussian box.

The potential at the bottom oxide–semiconductor interface φsb(y) can be expressed in terms of the φsf(y) by

solving the 1-D Poisson equation in the x-direction in Fig. 1 as

2

i sisb sf sf si g

si

( ) ( ) ( ) , 02

qN ty y E y t y L

(2)

and applying the electric displacement vector continuity conditions at the top oxide/semiconductor interface, we obtain

ox gs sfsf g

ox si

( ( ))( ) , 0

V yE y y L

t

(3)

Substituting Eqs. (2) and (3) in Eq. (1), we obtain

2

2sfsf2

( )( )

yy

y

(4)

with

2 ox ox2

si sisi

(2 )C C

C Ct

res ox ox ox1 gs 2

si si sisi si

(1 ) (2 )2

qN C C CV

C CC t

where Cox=εox/tox is the oxide capacitance and Csi=εsi/tsi is the silicon film capacitance.

The solution for Eq. (4), which is a simple second-order non-homogenous differential equation with constant coefficients, can be written as

sf 1 2( ) exp( ) exp( )y x x (5)

The electric field distribution can be written as

sf 1 2( ) exp( ) exp( )E y y y (6)

where 2

.

In order to determine the unknown functions ω1 and ω2, the following boundary conditions are used:

ssf (0) log( )

i

NKT

q n (7)

dsf g ds( ) log( )

i

NKTL V

q n (8)

Then, we can obtain the constants in Eqs. (5) and (6)

as

1

d sds g

g g

2

d sds g

g g

( log( ) ) ( log( ) )exp( )

exp( ) exp( )

( log( ) ) ( log( ) )exp( )

exp( ) exp( )

i i

i i

N NKT KTV L

q n q n

L L

N NKT KTV L

q n q n

L L

(9)

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The gate voltage, on which the tunneling barrier width at the tunnel junction has a weak dependence, is called the gate threshold voltage. When the channel potential in the inflection point wbs reaches the value

dds log( ),

i

NKTV

q n and the tunneling barrier width at the

tunnel junction has a transition between the strong and weak dependence on the gate voltage. By substituting wbs

and d

ds log( )i

NKTV

q n into Eq. (5), we can get the DG-

TFET gate threshold voltage model as

2 2si 1 2 2 3 1 1 si si

TG MSoxox

1 2 3 oxsi

( )

2 ( ) (2 )

iqN t C tV

CC CC

where

d1 dslog( )

i

NKTV

q n

s2 log( )

i

NKT

q n

1 g gexp( ) exp( )L L

2 bs bsexp( ) exp( )w w

3 g bs g bsexp( ) exp( ) exp( )exp( )L w L w

4 Results and discussion

The model was tested against the simulation results for different sets of parameters. The results show that the gate threshold voltage of DG-TFET is well predicted for different drain biasing conditions, Si layer thicknesses, gate dielectrics and gate lengths.

The model was firstly tested on a DG-TFET with Lg=100 nm, tox=3 nm and tsi=10 nm under a change in drain voltage. Figure 6 plots the variation of gate threshold voltage with drain voltage for different gate dielectrics. The line represents the model results, and scatter represents the simulation results which are extracted using TC method. It can be found that calculated results and simulation results agree very well with each other. VTG increases with the increase of Vds due to the reason that with a higher drain voltage applied to the device, the gate retains quasi-exponential control of the current over a larger voltage range.

Figure 7 shows the gate threshold voltage VTG versus the gate length Lg at given bias Vds=1 V and 0.5 V. VTG remains unchanged when the gate length increases. This is attributed to the limit effect of gate length Lg on the physical gate threshold voltage VTG as shown in Fig. 5. The presented analytical model can describe this effect well.

Figure 8 shows the gate threshold voltage VTG characteristic of DG-TFET as a function of gate

Fig. 6 VTG versus Vds

Fig. 7 VTG versus Lg

Fig. 8 VTG versus εox dielectric εox at Vds=1 V and 0.5 V. Gate dielectric εox here is scaled from 29 to 3.9 at constant gate oxide thickness tox=3 nm. The high-κ dielectric provides the gate with better capacitive control of the barrier width in tunnel junction, therefore, the corresponding VTG decreases for a given Vds. Figure 9 plots the variation of gate threshold voltage VTG with Si layer thickness. VTG decreases linearly when the Si film thickness decreases. Tunnel FETs are sensitive to body thickness, which influences the shape of its Ids−Vgs curve, as shown in

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Fig. 4. A thinner film modifies the electric field lines, increasing the gate control of the barrier width in tunnel junction. The model presented in this work can predict this phenomenon very well.

Fig. 9 VTG versus tsi

5 Conclusions

1) A numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET is reported. It is shown that the characteristics of DG-TFET can be optimized by setting its parameters.

2) A simple analytical gate threshold voltage model for the DG-TFET is derived based on its physical definition by solving quasi-two-dimensional Poisson equation in Si film. It is shown that the proposed model is consistent with the simulation results.

3) Also, the model can predict the improved performance on the physical threshold voltage when using high-κ dielectrics and thin Si layer and the limited effect on threshold voltage when changing the gate length.

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(Edited by DENG Lü-xiang)