MOSFETs -...

ECE 663

MOSFETs

ECE 663

A little bit of history..

Substrate

Channel Drain

Insulator

Gate

Operation of a transistor

VSG > 0n type operation

Positive gate bias attracts electrons into channelChannel now becomes more conductive

Moreelectrons

Source

VSD

VSG

Substrate

Channel Drain

Insulator

Gate

Operation of a transistor

Transistor turns on at high gate voltageTransistor current saturates at high drain bias

Source

VSD

VSG

Substrate

Channel Drain

Insulator

Gate

Source

VSD

VSG

Start with a MOS capacitor

ECE 663

MIS Diode (MOS capacitor) – Ideal

W

Questions

What is the MOS capacitance? QS(yS)

What are the local conditions during inversion? yS,cr

How does the potential vary with position? y(x)

How much inversion charge is generated at the surface? Qinv(x,yS)

Add in the oxide: how does the voltage divide? yS(VG), yox(VG)

How much gate voltage do you need to invert the channel? VTH

How much inversion charge is generated by the gate? Qinv(VG)

What’s the overall C-V of the MOSFET? QS(VG)

ECE 663

EC

EF

EV

Ei

Ideal MIS Diode n-type, Vappl=0

Assume Flat-band at equilibrium

qfS

ECE 663

02

yff B

g

mmsq

E

Ideal MIS Diode n-type, Vappl=0

ECE 663

Ideal MIS Diode p-type, Vappl=0

ECE 663

Ideal MIS Diode p-type, Vappl=0

02

yff B

g

mmsq

E

ECE 663

Accumulation

Pulling in majority carriers at surface

ECE 663

But this increases the barrier for current flow !!

n+ p n+

ECE 663

Depletion

ECE 663

Need CB to dip below EF. Once below by yB, minority carrier density trumps the intrinsic density. Once below by 2yB, it trumps the major carrier density (doping) !

Inversion

yB

ECE 663

Sometimes maths can help…

ECE 663

P-type semiconductor Vappl0

Convention for p-type: y positive if bands bend down

ECE 663

Ideal MIS diode – p-type

yyy enenenenn p

kTq

p

kTEqE

i

kTEE

ipFiFi

0

/

0

/)(/)( '

yy epepp p

kTq

pp 0

/

0

kT

q

CB moves towards EF if y > 0 n increases

VB moves away from EF if y > 0 p decreases

ECE 663

Ideal MIS diode – p-type

At the semiconductor surface, y = ys

senn ps

y 0

sepp ps

y 0

• ys < 0 - accumulation of holes

• ys =0 - flat band

• yB>ys >0 – depletion of holes

• ys =yB - intrinsic concentration ns=ps=ni

• ys > yB – Inversion (more electrons than holes)

ECE 663

Surface carrier concentration

senn ps

y 0

sepp ps

y 0

ECEF

ECE 663

Want to find y, E-field, Capacitance

• Solve Poisson’s equation to get E field, potential based on charge density distribution(one dimension)

s

s

dx

d

dx

d

Ddx

dk

y

y

/

1//

2

2

0

)()( ppAD npNNqx

EE

E

ECE 663

• Away from the surface, = 0

• and

00 ppAD pnNN

yy enepnp pppp 00

)1()1( 002

2

y

yy enepq

dx

dpp

s

ECE 663

Solve Poisson’s equation:

)1()1( 002

2

y

yy enepq

dx

dpp

s

E = -dy/dx

d2y/dx2 = -dE/dx

= (dE/dy).(-dy/dx)

= EdE/dy

)1()1( 002

2

y

yy enepq

dx

dpp

s

EdE/dy

ECE 663

• Do the integral:

• LHS:

• RHS:

• Get expression for E field (dy/dx):

dx

dx

xxdx

x y

0

2

2

x xx dxdxe

0 0

,

yy

yy 11

2 0

00

2

2 ep

ne

qp

q

kTE

p

p

s

p

field

Solve Poisson’s equation:

ECE 663

2

1

0

0

0

011,

yy

y yy e

p

ne

p

nF

p

p

p

p

Define:

0

2

0 p

s

p

sD

qpqp

kTL Debye Length

Then:

y

0

0,

2

p

p

D

fieldp

nF

qL

kTE

+ for y > 0 and – for y < 0

y > 0

E > 0

y < 0

E < 0

ECE 663

y

0

0,

2

p

p

s

D

Sssp

nF

qL

kTEQ

Use Gauss’ Law to find surface charge per unit area

2

1

0

011

2

yy

yy

s

p

p

s

D

ssS e

p

ne

qL

kTQ

ECE 663

Accumulation to depletion to strong Inversion

• For negative y, first term in F dominates – exponential

• For small positive y, second term in F dominates - y

• As y gets larger, second exponential gets big10

0

y

p

p

p

en

yB = (kT/q)ln(NA/ni) = (1/)ln(pp0/√pp0np0)

(np0/pp0) = e-2yB

yS > 2yB

Questions









ECE 663

Charges, fields, and potentials

• Charge on metal = induced surface charge in semiconductor

• No charge/current in insulator (ideal)

metal insul semiconductor

depletion

inversion

SAnM QWqNQQ

ECE 663

Electric Field Electrostatic Potential

Charges, fields, and potentials

ECE 663


Depletion Region

yy

yy 11

2 0

00

2

2 ep

ne

qp

q

kTE

p

p

s

p

field

ECE 663


y = ys(1-x/W)2

Wmax = 2s(2yB)/qNA

yB = (kT/q)ln(NA/ni)

Depletion Region

Questions









Couldn’t we just solvethis exactly?

U = y

US = yS

UB = yB

Exact Solution

dy/dx = -(2kT/qLD)F(yB,np0/pp0)

dU/F(U) = x/LD

U

US

F(U) = [eUB(e-U-1+U)-e-UB (eU-1-U)]1/2

Exact Solution

dU’/F(U’,UB) = x/LD

U

US

F(U,UB) = [eUB(e-U-1+U) + e-UB (eU-1-U)]1/2

= qni[eUB(e-U-1) – e-UB(eU-1)]

Exact Solution

NA = 1.67 x 1015

Qinv ~ 1/(x+x0)a

x0 ~ LD . factor

Questions









ECE 663

Threshold Voltage for Strong Inversion

• Total voltage across MOS structure= voltage across dielectric plus ys

B

i

SSiT

C

QVinversionstrongV yy 2)_(

)2(2)(2

)( max BAs

A

ssAAS qN

qN

invqNWqNSIQ y

y

B

i

BAsT

C

qNV y

y 2

)2(2

oxVi/tox = sys/(W/2) Before Inversion

After inversion there is a discontinuity in D due to surface Qinv

Vox (at threshold) = s(2yB)/(Wmax/2)Ci =

ECE 663

Notice Boundary Condition !!

B

i

BAsT

C

qNV y

y 2

)2(2

Local Potential vs Gate voltage

VG = Vfb + ys + (kstox/kox)√(2kTNA/0ks)[ys + eys-2yB)]1/2

Initially, all voltage drops across channel (blue curve). Above threshold, channel potential stays pinned to 2yB, varying only logarithmically, so that most of the gate voltage drops across the oxide (red curve).

yoxys

Look at Effective charge width

Initially, a fast increasing channel potential drops across increasing depletion width

Eventually, a constant potential drops across a decreasing inversion layer width, so field keeps increasing and thus matches increasing field in oxide

~Wdm/2

~tinv

Questions









Charge vs Local Potential

Qs ≈ √(20kskTNA)[ys + eys-2yB)]1/2

Beyond threshold, all charge goes to inversion layer

How do we get the curvatures?

EXACTAdd other terms and keepLeading term

Inversion Charge vs Gate voltage Q ~ eys-2yB), ys

- 2yB ~ log(VG-VT)Exponent of a logarithm gives a linear variation of Qinv with VG

Qinv = -Cox(VG-VT)

Why Cox?

Questions









ECE 663

Capacitance

y

y

yy

0

0

0

0

,

11

2

p

p

S

p

p

D

SSD

p

nF

ep

ne

L

QC

ss

For ys=0 (Flat Band):

D

SD

LbandflatC

)_(

Expand exponentials….. ........!3!2

132

xx

xex

ECE 663

Capacitance of whole structure

• Two capacitors in series:

Ci - insulator

CD - Depletion

Di CCC

111 OR

Di

Di

CC

CCC

dC i

i

ECE 663

Capacitance vs Voltage

ECE 663

Flat Band Capacitance

• Negative voltage = accumulation – C~Ci

• Zero voltage – Flat Band

i

D

s

i

si

Dis

D

siDiFB

LdLd

Ld

CCC

11111

FBCCV y 00

D

iFB

LdC

s

i

ECE 663

CV

• As voltage is increased, C goes through minimum (weak inversion) where dy/dQ is fairly flat

• C will increase with onset of strong inversion

• Capacitance is an AC measurement

• Only increases when AC period long wrt minority carrier lifetime

• At “high” frequency, carriers can’t keep up – don’t see increased capacitance with voltage

• For Si MOS, “high” frequency = 10-100 Hz

ECE 663

CV Curves – Ideal MOS Capacitor

max

'

minWd

C

s

i

i

ECE 663

MOScap vs MOSFET

ECE 663

Substrate

Drain

InsulatorGate

Source Channel

Substrate

InsulatorGate

Channel

Minority carriers generated byRG, over minority carrier lifetime~ 100ms

So Cinv can be << Cox if fast gateswitching (~ GHz)

Majority carriers pulled infrom contacts (fast !!)

Cinv = Cox

MOScap vs MOSFET

ECE 663

Example Metal-SiO2-Si

• NA = 1017/cm3

• At room temp kT/q = 0.026V

• ni = 9.65x109/cm3

• s = 11.9x1.85x10-14 F/cm

mcmW

Xx

xXxx

Nq

n

NkT

WA

i

As

m

1.010

10106.1

1065.910ln026.01085.89.11ln4

5

max

1719

91714

2max

ECE 663

Example Metal-SiO2-Si

• d=50 nm thick oxide=10-5 cm

• i=3.9x8.85x10-14 F/cm

Voltsinvx

xxx

C

WqNV

C

C

cmFxx

xx

WdC

Voltsx

xxn

N

q

kTinv

cmFxxx

dC

sB

i

ATH

i

i

i

ABs

ii

s

i

07.184.023.0)(109.6

1010106.12

13.0

/101.9109.119.3105

1085.89.3

84.01065.9

10ln026.02ln

22)(

/109.610

1085.89.3

7

51719

max

'

min

28

57

14

max

'

min

9

17

27

5

14

yy

yy

ECE 663

Real MIS Diode: Metal(poly)-Si-SiO2 MOS

• Work functions of gate and semiconductor are NOT the same

• Oxides are not perfect– Trapped, interface, mobile charges

– Tunneling

• All of these will effect the CV characteristic and threshold voltage

ECE 663

Band bending due to work function difference

msFBV f

ECE 663

Work Function Difference

• qfs=semiconductor work function = difference between vacuum and Fermi level

• qfm=metal work function

• qfms=(qfm- qfs)

• For Al, qfm=4.1 eV

• n+ polysilicon qfs=4.05 eV

• p+ polysilicon qfs=5.05 eV

• qfms varies over a wide range depending on doping

ECE 663

ECE 663

SiO2-Si Interface Charges

ECE 663

Standard nomenclature for Oxide charges:

QM=Mobile charges (Na+/K+) – can causeunstable threshold shifts – cleanlinesshas eliminated this issue

QOT=Oxide trapped charge – Can be anywherein the oxide layer. Caused by brokenSi-O bonds – caused by radiation damagee.g. alpha particles, plasma processes,hot carriers, EPROM

ECE 663

QF= Fixed oxide charge – positive charge layernear (~2mm) Caused by incompleteoxidation of Si atoms(dangling bonds)Does not change with applied voltage

QIT=Interface trapped charge. Similar in originto QF but at interface. Can be pos, neg,or neutral. Traps e- and h during deviceoperation. Density of QIT and QF usuallycorrelated-similar mechanisms. Cureis H anneal at the end of the process.

Oxide charges measured with C-V methods

ECE 663

Effect of Fixed Oxide Charges

ECE 663

ECE 663

Surface Recombination

Lattice periodicity broken at surface/interface – mid-gap E levelsCarriers generated-recombined per unit area

ECE 663

Interface Trapped Charge - QIT

• Surface states – R-G centers caused by disruption of lattice periodicity at surface

• Trap levels distributed in band gap, with Fermi-type distributed:

• Ionization and polarity will depend on applied voltage (above or below Fermi level

• Frequency dependent capacitance due to surface recombination lifetime compared with measurement frequency

• Effect is to distort CV curve depending on frequency

• Can be passivated w/H anneal – 1010/cm2 in Si/SiO2 system

kTEE

DD

D

DFegN

N/)(

1

1

ECE 663

Effect of Interface trapped charge on C-V curve

ECE 663

a – idealb – lateral shift – Q oxide, fms

c – distorted by QIT

ECE 663

Non-Ideal MOS capacitor C-V curves

• Work function difference and oxide charges shift CV curve in voltage from ideal case

• CV shift changes threshold voltage

• Mobile ionic charges can change threshold voltage as a function of time – reliability problems

• Interface Trapped Charge distorts CV curve – frequency dependent capacitance

• Interface state density can be reduced by H annealing in Si-Si02

• Other gate insulator materials tend to have much higher interface state densities

ECE 663

All of the above….

• For the three types of oxide charges the CV curve is shifted by the voltage on the capacitor Q/C

• When work function differences and oxide charges are present, the flat band voltage shift is:

d

i

echoxideFB dxxxdC

V0

arg_ )(11

i

otmfmsFB

C

QQQV

f

Some important equations in the inversion regime (Depth direction)

VT = fms + 2yB + yox

Wdm = [2S(2yB)/qNA]

Qinv = Cox(VG - VT)

yox = Qs/Cox

Qs = qNAWdm

VT = fms + 2yB + ([4SyBqNA] - Qf + Qm + Qot)/Cox

Substrate

Channel Drain

Insulator

Gate

Source

x

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