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VLSI

SEMINAR AND WORKSHOP

D.B.RAJESHApplication Engineer

SITEC ELECTRONICS

#33/B OPPOSITE TO FLORENCE

PUBLIC SCHOOL 2 ND BLOCK

R.T.NAGAR

BANGALORE-560032

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WELCOME

TO

THE WORLD OF VLSI

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EVOLUTION IN COMPUTERS

First Computer

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HISTORY OF IC DESIGN Date - 28th July.

Year - 1958.

Components1-Transistor, 3-Resistors,1-Capacitor.

Jack Kilby assembled those componentstogether on one semiconductor. The worlds

first integrated circuit.

He received the noble Prize for this inventionin October 2000.

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HISTORY OF IC DESIGN The first commercial monolithic IC came in the

market in 1961. It was a Flip-Flop, with 2 Transistors & resistor

Cost~$100

The metal-oxide-semiconductor (MOS) IC in 1962.

The complementary MOS (CMOS) IC in 1963.

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MOORES LAW

In 1969, Gorden Moore stated that, the

number of transistors per chip will double

every 18 months !!!

And it is happening !!!!!!!

Infact our world follows Moores Law.

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EVIDENCE OF MOORES LAW

ACCORDING TO GORDEN MOORE -

(in millions)

1996 MID 1997 1999YEAR

5 10 20 40

MID 2001

Pentium-I Came In 1996 Transistor Count5 Million

Pentium-IV Came In 2001 Transistor Count43 Million

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THE PROJECTED TREND OF IC DEVICES

IC technology 1987 1992 2000

TTL 12% 4% 1%

ECL 4% 2% Less than 1%PMOS Less than 1% 0% 0%

NMOS 24% 4% Less than 1%

CMOS 39% 73% 82%

BICMOS 0% 2% 6%

GaAs Less than 1% Less than 1% 1%

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DIGITAL PROGRAMMING METHODS

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TYPES OF LOGIC

LOGIC

Standard Logic

Programmable

Logic Devices

(PLDs)ASIC

SIMPLE PLDs CPLDs FPGAs

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STANDARD LOGIC

ADVANTAGES

-- Operating Speed is high

DISADVANTAGES

-- Defines only one function

-- Occupies large area in PCB

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PLDs

-- Prefabricated

-- Defines more functions

-- Reprogrammable

-- Occupies less area

-- Operating speed is low

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Simple PLDs (SPLD)

Programmable logic array

(PLA)

Programmable AND arrayand programmable OR

array

Programmable array logic(PAL)

Programmable AND array

with fixed OR array

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Simple PLDs (SPLD)

ADVANTAGES

-- It can define more functions in a single SPLD

-- Low cost

-- Delay is less compared to CPLD & FPGA

DISADVANTAGE

-- It is not useful for complex designs

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CPLD Architecture

Integration of several PLD blocks with a

programmable interconnect on a single chip

SPLD

BlockSPLD

Block

Interconnection Matrix

I/OBlock

I/OBlock

SPLD

BlockSPLD

Block

I/OBloc

k

I/OBloc

k

Interconnection Matrix

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CPLD

ADVANTAGE

-- Non-volatile memory

DISADVANTAGES

-- Less Operating speed

-- The gate density is up to 200k

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FPGA Architecture

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IOB

IOB = Input/Output Block (interface between the

package pins and the internal logic)

For spartan3 400k there are totally 144 IO pins.

In that 97 pins are user pins and 47pins arededicated pins

Totally 10 FRC ports are there in that

3---16pins2pins(1vcc,1gnd)

7---10pin----4pins(3vcc,1gnd)

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CLB

CLB (Configurable Logic Block) contains

4---LUT (4 variable)

Each LUT contains

1) Function Generators

2) MUX3) Flip Flop

4) Buffers

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BLOCK RAM

Used to store large amount of data.

Totally 16 block rams are there in Spartan-3

FPGA

Each block ram can store 18kbit data

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MULTIPLIER

Totally 16 Multipliers are there in Spartan-3

FPGA

Each Multiplier will multiply two 16 bits and

it will give 32bit result

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DCM

DCM = Digital Clock Manager

It is used on clock operations

1) Clock Division

2) Clock Multiplication3) Phase Shifting

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FPGA

ADVANTAGE

-- Gate density is up to 5-million

DISADVANTAGES

-- Volatile memory-- Operating Speed is less

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Why FPGA and CPLD ?

Reprogrammable Hardware

Low power

High speed

More I/O lines

Portable

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ASIC (Application specific integrated circuit)

ASIC

FULL CUSTOMSEMI CUSTOM

SEMI CUSTOM

Logic taken from librariesLayers are customized

FULL CUSTOMLogic and layers are customized

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ASIC

ADVANTAGES

-- Operating Speed is High

-- It defines more functions

-- High security

DISADVANTAGES

-- One time Programmable

-- Very high cost

-- It takes more time to come to market.

-- used for only one specific application

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BACKBONE OF VLSI DESIGN

Backbone of VLSI design are, Industrieslike.

EDA Companies

Mentor Graphics

Synplicity Synopsys

Cadence

Aldec

Device Vendors

Xilinx, Altera , Actel, Cypress, QuickLogicetc

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VLSI DESIGN FLOW

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DESIGN SPECIFICATIONS

Design specification is nothing but specifying therequirement of our design

There are various ways in which the design can be

specified.

Some of the specifications are :

Synchronous or Asynchronous design.

Positive or negative edge of the clock.

Number of blocks used for the design.

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DESIGN ENTRY

Design entry is the media through which ideas withdesigner are entered into the soft format.

There are various ways in which the design can beentered. Some of the popular ones are :

Designing with the help of schematics.

Designing using HDLS [ Hardware DescriptionLanguage ].

Designing using State Machines.

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DESIGN ENTRYSCHEMATIC HDL CODING FSM C Java

4 input AND gate

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DESIGN ENTRY

Hardware Description Languages : An effective wayto describe the functionality in a user friendly manner

VHDL [ Very High Speed Integrated Circuit Hardware

Description Language ].

Origin : 1981 (DOD America)

Standard : IEEE10761999

VERILOG HDL

Standard : IEEE1364

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DESIGN ENTRY

SCHEMATIC HDL CODING FSM C Java

Use library ieee;

use ieee.std_logic_1164.all;

entity AND4 isport (

A, B, C,D : in std_logic;

S : out std_logic;

);

end AND4 ;

architecture AND4 _ARCH of AND4 is

begin

S

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DESIGN ENTRY

SCHEMATIC HDL CODING FSM C Java

STATE MACHINE TO COUNT THE SEQUENCE

001 - 011 - 111

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Simulation Purpose

Analyze a Design / Testbench for Correct Syntax

Elaborate the Design for Integrity

Run the Testbench

Observe that the Design Behaves as Expected

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FUNCTIONAL SIMULATION

Functional Simulation is carried after entering the design.

Need for the simulation comes from the fact that the entered design isworking as per specifications

Advantage : Saves the time consuming need for physical prototyping

A

B

C = 1

D = 1

S

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SYNTHESIS

Synthesis is automatic process of converting HDL

code into equivalent logic gates.

Synthesis results are Target Technology Dependent.

Use library ieee;

use ieee.std_logic_1164.all;

entity AND4 is

port (

A, B, C,D : in std_logic;

S : out std_logic;

);

end AND4 ;

architecture AND4 _ARCH of AND4 is

begin

S

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SYNTHESIS

Synthesis

DesignConstraint

Libraries

NetlistReport

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POST-SYNTHESIS SIMULATION

Post Synthesis also called as GATE Level SimulationSimulation verifies functionality after Synthesis.

A

B

C=1

D=1

S

S1

GATE DELAY

Post synthesis simulation of 4-input and gate

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MAPPING & TRANSLATION

Mapping : Tool partitions thedesign into the logic blocks

available on the device. Goodpartitioning results in betterperformance

System Partitioning Dividing a large system into

smaller / standard modules

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PLACE & ROUTE

Is the process of, Placing the design into the

specified Device.

Optimizing the usage of

available resources, viz.logic cells andInterconnects.

Is Vendor and TargetTechnology Dependent

It Uses Vendor Libraries Vendor???

Algorithms

User Specified Constraints

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POST P & R SIMULATION

A

B

C = 1

D= 1

S

S1

S2

INTERCONNECT DELAYGATE DELAY

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BACK ANNOTATION

Technique of reducing the timing delay

Techniques:

Writing the code effectively

Change the pin assignments

Change the LUT positions near to the I/O pins

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PROGRAMMING

PROGRAM & SYSTEM TEST

Programming is the process of downloading

the design into the device.Applicable only for PLDs

After the device is programmed, you are

ready to test the actual system, with real lifeinputs and outputs.

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VLSI - APPLICATIONS

VLSI Finds applications in all aspects of Life,

Consumer Electronics, Defense, Computers, Communication,Space, Networking..

Some of applications could be listed as WIRELESS LAN

RE - CONFIGURABLE COMPUTING

WEARABLE COMPUTERS

HOME NETWORKING BLUETOOTH

SONET / SDH

Bus Interfaces, viz. PCI, Firewire, USB

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VLSI OPPORTUNITES

IBM

Intel

Motorola

TexasInstruments

STMicroElectronics

Cirrus Logic

Insight [ Xilinx]

Philips Sanyo

Lucent

Logic Eastern

Sasken

GE

HCL

SCL

Synopsys

PMC Sierra

NitAlIKOS

Alliance

Semiconductor

Wipro

L & T

DCM

Mos Chip

Chip Engines

U&I Scotty

Sage

AvantCirrus Logic

Cadence

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JOB AVENUES

More than 700 companies in India working inVLSI design

More then 200 Companies in Bangalore itself.

Major Hubs - Bangalore, Delhi, Hyderabad,Chennai, Pune, Mumbai.

Salaries in the range of 2 to 4 lacs/annum.

Jobs are for Design Engineer, Test Engineer,Field Application Engineers, Backend .

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THANK YOU

D.BASAVA RAJESH

SITEC ELECTRONICS

Email : rajesh@chipmaxindia.com

Mobile : 09986071743

mailto:rajesh@chipmaxindia.commailto:rajesh@chipmaxindia.com