8/16/2019 [Doi 10.1109_csci.2014.150] Kahraman, Nihan; Kiyan, Tuba -- [IEEE 2014 International Conference on Computatio…

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A Neural Network-Based Design Automation of

a Second Generation Current Conveyor

 Nihan KAHRAMAN

Electronics and Telecommunication Engineering

Yildiz Technical University

Istanbul, Turkey

nicoskun@yildiz.edu.tr

Tuba KIYAN

Electronics and Telecommunication Engineering

Yildiz Technical University

Istanbul, Turkey

tkiyan@yildiz.edu.tr

 Abstract  —  An artificial neural network approach for the

automated design of a positive type second generation current

conveyor is presented in this paper. A multi-layer perceptron

structure is successfully employed to estimate the

corresponding transistor dimensions for a given set of desired

performance criteria of the circuit. Data generated by a circuit

simulation program (SPICE) is used to train the artificial

neural network. The excellent agreement between the desired

specifications and the actual results from SPICE simulation

results approves that neural networks are powerful tools for

automated analog circuit sizing.

 Keywords- Computer aided design (CAD); neural networks;

 positive second generation current conveyor (CCII+); multilayer

 perceptron (MLP).

I. I NTRODUCTION

Analog circuits such as amplifiers, filters, oscillators

either can be designed in voltage mode or current mode [1-

3]. Since current mode circuits have the potentialadvantages such as wider bandwidth, simpler circuitry,

lower power consumption, and wider dynamic range, they

are preferred to their voltage mode counterparts.

Artificial neural networks (ANN) and evolutionary

algorithms are employed as aids in circuit design. In theliterature, there is some work that optimizes current

conveyor performance by using some optimization

algorithms. In [4], a steepest descent algorithm is used to

adjust the transistor sizes to obtain an optimum performance

for a filter that is designed using CCII+. In [5], bacterial

foraging optimization algorithm is used for finding thetransistor dimensions in order to increase the performance

of a CCII+. In [6], a heuristic methodology is used to

optimize an ultra low voltage rail to rail CCII.This paper aims to estimate the transistor dimensions for

a given set of specifications. An ANN is employed to attain

the sizes of all the transistors employed in the secondgeneration current conveyor.

II. SECOND GENERATION CURRENT CONVEYORS

CCII is a four-terminal active element. The terminal

equations are defined in Equation 1 for a non-ideal current

conveyor.

 z 

 x

 y

 z 

 x

 y

V 

 I 

V 

 I 

V 

 I 

00

00

000

  

    (1)

A positive type second generation current conveyor (Fig.1) is designed by using TSMC 0.25µm design parameters.

Positive and negative supply voltages are taken as +2.5V

and -2.5V, respectively. CMOS CCII+ is simulated by usingSPICE. Considering the circuit specifications, the transistor

dimensions are adjusted .

The linearity between  I  z  and  I  x is maintained, only when

 I  x  is larger than -100 µA and smaller than 100 µA.

Moreover, V  x follows V  y for -0.8 V < V  y < 0.8 V. According

to frequency domain simulation results, the bandwidth ofiz/ix current gain is 150 MHz and that of v x /v y voltage gain is

9 GHz.

III. DESIGN METHODOLOGY

The aim is to estimate the transistor sizes for the CCII+

for a given set of specifications by employing artificial

neural networks. In order to accomplish this, LevenbergMarquart algorithm and multilayer perceptron (MLP)

structure is used. MLP is a feed-forward artificial neural

network model that maps sets of input data onto a set of

appropriate outputs. It is trained with the error back-

 propagation learning algorithm. The system has two hidden

and one output layer. Logarithmic sigmoid in hidden layersand linear function in output layer is used as an activation

function. The first and second hidden layer has 20 and 10

neurons, respectively. The number of output neurons is 6.

The learning rate for Levenberg Marquardt is 0.6 and

momentum constant is 0.1.MLP maps sets of input data onto a set of appropriate

transistor dimension space. The desired performance criteriasuch as current and voltage ranges for a linear operation, bandwidth of the current and voltage follower and inputresistances of each terminals, are given to the artificialnetwork as inputs and corresponding transistor sizes areobtained as outputs of the system. The circuit is simulatedwith the obtained transistor dimensions and the results areevaluated and presented in Section IV.

2014 International Conference on Computational Science and Computational Intelligence

978-1-4799-3010-4/14 $31.00 © 2014 IEEE

DOI 10.1109/CSCI.2014.150

797

2014 International Conference on Computational Science and Computational Intelligence

978-1-4799-3010-4/14 $31.00 © 2014 IEEE

DOI 10.1109/CSCI.2014.150

313

2014 International Conference on Computational Science and Computational Intelligence

978-1-4799-3010-4/14 $31.00 © 2014 IEEE

DOI 10.1109/CSCI.2014.150

313

2014 International Conference on Computational Science and Computational Intelligence

978-1-4799-3010-4/14 $31.00 © 2014 IEEE

DOI 10.1109/CSCI.2014.150

313

8/16/2019 [Doi 10.1109_csci.2014.150] Kahraman, Nihan; Kiyan, Tuba -- [IEEE 2014 International Conference on Computatio…

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Figure 1. CMOS CCII+

IV. ANN BASED CIRCUIT SIZING R ESULTS

A pattern which has the iputs given in Table I is used totest the designed ANN. These inputs are the performancerequirements that the circuit is expected to meet. The trainedANN produces the transistor sizes as outputs as shown inTable II. To verify these results, we implemented SPICEsimulations using the W/L that are obtained by ANN. The

simulation results for this particular test pattern are shown inFigure 2 and Figure 3. It is observed that SPICE simulationresults are consistent with the desired specifications.

TABLE I. THE INPUTS FOR THE ANN

Specifications

Current range for a linear

current follower (Iz=Ix)-100 μA < Ix < 100 μA

Voltage range for a linear

voltage follower (Vy=Vx)-0.4 V < Vx < 0.6 V

Bandwidth of the Vx/Vy 10.07 GHz

Bandwidth of the Iz/Ix 167 MHz

Impedance of terminal X 5.33 K 

Impedance of terminal Y 3.8 T

Impedance of terminal Z 132 G

TABLE II. The Output of the ANN

TransistorW

[µm]L

[µm]Transistor

W

[µm]L

[µm]

T1 0.8965 0.2591 T5 2.0827 0.2473

T2 0.8965 0.2591 T6 2.0827 0.2473

T3 2.0827 0.2473 T7 1.3282 25.0474

T4 2.0827 0.2473 T8 1.3282 25.0474

V. CONCLUSION

In this work, we successfully demonstrated how CMOSCCII+ can be automatically designed for changing

 performance requirements which is achieved by employing

a MLP structure for this task. It has two hidden and one

output layer. First and second hidden layers have twenty and

ten neurons, respectively and output layer has six neurons.A set of training vector and test vector is produced using

SPICE simulations, which consists of design specifications

as inputs to the MLP and transistor sizes as outputs. MLP

maps sets of input data onto a set of appropriate transistordimension space

A test vector is applied in order to verify the system. It isshown that the system produces the accurate transistor sizesfor a given set of performance requirements which makes it

suitable for computer aided design (CAD) applications.

Figure 2. The frequency response of v x /v y voltage gain

Figure 3. The frequency response of i z  /i x current gain

R EFERENCES

[1] Laker, K. R., Sansen, W.M.C., (1994), “Design of Analog IntegratedCircuits and Systems”, Mcgraw-Hill.

[2] Deliyannis, T., Sun, Y., Fidler, J.K., (1999), “Continuous-TimeActive Fitler Design”, CRC Pres, London.

[3] Razavi, B., (2001), “Design of Analog CMOS Integrated Circuits”,McGraw-Hill.

[4] S. I. Liu, H.W. Tsao, J. Wu, T. C. Yu and T. K. Lin, “Design andoptimization of MOSFET-capacitor filters using CMOS currentconveyors”, Proceedings of the IEEE International Symposium onCircuits and Systems, vol. 3, 1990, pp. 2283-2286.

[5] A. Chatterjee, M. Fakhfakh, P. Siarry, “Design of second generationcurrent conveyors employing bacterial foraging optimization”,Microelectronics Journal, vol. 41, 2010, pp.616-626.

[6]  N. B. El Feki, S. Ben Salim, D.s. Masmoudi, “Optimization of a railto rail low voltage current conveyor and high frequency current modemode filter applications”, Journal of Applied Sciences Research, Vol.4, 2008, pp.1925-1934.

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