1/19/2005 1®

Diversified Technologies for System-on-Chip

Polytechnique, 9 March, 2004

Gerard Mas, Programme Management, Director Central R&D, Crolles

1/19/2005 2®

AgendaThe Market trendsCMOS roadmap and added-value optionsTechnology support for Low-power• Optimized MOS, multi-Vt• SOI• eDRAM

Design / Manufacturing linksSystem On Chip Design ChallengesCompetition.Conclusions

1/19/2005 3®

23%North America 5%

Japan

33%Asia

Pacific

36%Europe

3%Region

5*

2000 Sales: US$ 7.8B43,000 employees17 main production sites9 advanced R&D sites35 design and application centers62 direct sales offices in 24 countries3th* largest semiconductor supplier

(*source Dataquest)

2000 Sales: US$ 7.8B43,000 employees17 main production sites9 advanced R&D sites35 design and application centers62 direct sales offices in 24 countries3th* largest semiconductor supplier

(*source Dataquest)* Emerging markets

SMicroelectronics - A Global Semiconductor Company

1/19/2005 4®

Les prochains defis de l’industriede la microelectronique

Des defis d’ordre technique• Technologie Nanometre• Systeme sur siliciumDes defis d’ordre economique• Alliance• co-competition

1/19/2005 5®

The market trends

1/19/2005 6®

Living-Room Appliances

Audio Out

Video OutSatellite

DVD

Cable

Dig Terrestrial

MPEG A/VDecoder

BroadbandInterface

ONE PLATFORM

1/19/2005 7®

DVD – Variety of Applications

Basic DVD Player

DVD Recorder

Personal DVD

DVD TV Combos

DVD Receivers

DVD Audio

In Car Navigation

1/19/2005 8®

Migration of Digital TV

Analog Signals+

Digital ImageProcessing

Analog TV +

Free to AirDigital Decoder

Terrestrial Tuner

Fully Digital –Digital Signal,

Digital Tuner/DecoderImage Processing

Home Network

Home NetworkEthernet – 802.11 - HPNA

IP Telephony

TV BroadBandMedia Streaming

Cable/Satellite/DTT

PC BroadBandWWW Connection

CableModem/ADSL

WirelessInterconnect

Home NetworkRouters

Home Entertainment SystemsMedia Servers

1/19/2005 9®

Convergence of Technologies…

RFRF SecuritySecurityLow Power

Low Power

WEBWEB Flat PanelFlat

PanelCPUCPUHDDHDD NetworkNetwork

xDSLxDSL VoIPVoIPSecure NetworkSecure NetworkISDNISDN Cable

ModemCable

Modem

VideoVideo AudioAudioSecure AccessSecure Access

ImageSensors

ImageSensors GamesGames Video

Analog

Digital

CM

OS

DIG

ITA

LC

ON

VER

GEN

CERFWIRELESS

Analog/MixedSignal

CONSUMER

COMPUTER

TELECOM

1/19/2005 10®

1/19/2005 11®

……Divergence of Divergence of Applications

AUTOMOTIVE

Secure NetworkSecure Network

AudioAudio

Flat PanelFlat

Panel

HDDHDD

ImageSensors

ImageSensors

VideoVideoCPUCPUVideoVideo

MULTIMEDIAPHONE

RFRF

SecuritySecurityLow Power

Low Power

WEBWEB

NetworkNetwork

OFFICECOMPUTER

Secure NetworkSecure Network

Flat PanelFlat

Panel

HDDHDD

VideoVideo

CPUCPU

xDSLxDSL

HOMECONSUMER

VoIPVoIP

HDDHDD

Flat PanelFlat

PanelVideoVideo

ImageSensors

ImageSensors

CPUCPU

xDSLxDSL

CableModemCable

ModemCM

OS

DIG

ITA

LC

ON

VER

GEN

CE

Secure NetworkSecure Network

1/19/2005 12®

More Options in shorter timeN

b of

opt

ions

0.18µm

0.12µm 90 nm

AnalogRFBiCMOSe-SRAMe-DRAMPassivesetc…

Years

1/19/2005 13®

High Performance Technologies for …

Very Low power consumption in SoCand also…Ultra Low noise RF performanceHigh Speed digital and analogue (SiGe)Refined Analogue precisionEnergy Management (high voltage)High Density Memories (eDRAM, MRAM, Flash)

1/19/2005 14®

CMOS roadmap and added-value options

1/19/2005 15®

CMOS roadmap

70 -

100 -

130 -

180 -

Generation(nm)

0.18 Shrink110 kgates/ mm²

0.18 µm6 ML/ 1.8 V

85 kgates/ mm²

m0.12 µ6-8 ML/ 1.2 V

200 kgates/ mm²

90nm7-9 ML/ 1.0 V

360 kgates/ mm²

1998 1999 2000 2001 2002 2003 2004

65nm9-10 ML/ 0.9 V

650 kgates/ mm²

200mm

Right edge of boxes is PG acceptance

1/19/2005 16®

CMOS Roadmap: from R&D to production

2001 2002 2003 2004 2005 2006 2007

1st silicon

Protos acceptance

Production start

CMOS 45 nm

Advanced R&D

CMOS 32 nm

Advanced R&D

CMOS 90 nm

CMOS 65 nm

Advanced R&D

CMOS 120 nm

4 advanced CMOS platforms developed in parallel

1/19/2005 17®

Evolution in the last 10 yearsContact in 0.5µm = 0.64µm2

6-transistor SRAM cell in 65nm

From HCMOS5 (1992) to CMOS065 (2002)

1/19/2005 18®

CMOS090 300mm 6LM integration

Metal 6

Metal 1

Metal 2

Metal 3Metal 4

Metal 5

1/19/2005 19®

Extending Core CMOS for SOC

CMOS coreprocess

BICMOSRF (cellular phone)Fiber Optic IC

HFCMOSPower Management (cellular phone)

SRAM/DRAMPC peripherals

AnalogTuner (Set-Top Box)

RFCMOSBluetooth

ImagerWeb Cam

1/19/2005 20®

ABOVE IC INTEGRATIONSystem on Chip (SOC) approachOpen the door for innovative architecture & RF front-end

CoCo--integration of ICs, passives and RFMEMS integration of ICs, passives and RFMEMS New RF functions through strong coNew RF functions through strong co--development development

between technology & RF designbetween technology & RF design

High Q inductor

FBAR filter

RF Micro-switch

RFIC circuit

1/19/2005 21®

SoC’s with CMOS-Imager process

For mobile phone applications:ZS450: CIF format (~100000 pixels)

For webcam applications:ZS422: QVGA format (~75000 pixels)

=> audio/video/video processing (SOC)

Area24.0 mm²

Area39.6 mm²

ZS550: VGA format (~300000 pixels)

Area24.1 mm²

1/19/2005 22®

Production 0.18um SoC’s with eDRAM

Low-End Printer High-End Printer(20mm²) (34 mm²)

4 Mbits eDRAM

6 Mbits eDRAMCamera for cell phone

(15 mm²)Includes ARM microIncludes ARM micro

3 Mbits eDRAM

Disk Controller DVD recorder(26 mm²) (34 mm²)

4 Mbits

eDRAM

Includes ST10 microIncludes Super10 micro

1/19/2005 23®

Low-Power

Process / Design Trends

1/19/2005 24®

2 opposite requirements for the future

Increase processing power (GOPS):• Video, Audio, Graphics, Communications:

High performance dedicated processorsA lot of embedded memories

• Replace Analog by Digital (e.g. digital Radio)

Reduce power consumption (Watt/Op):• Dynamic power = CV2f

C: Need SOI-like junctions and LowK dielectricsV: decrease VDD to the minimum to achieve Frequency fF: keep Frequency pretty low, use parallelism

• Static power = as low as possible

1/19/2005 25®

Power Density in Microprocessors

i386 i486

Pentium

Pentium IIPentium Pro

Pentium III Pentium IV

Nuclear Reactor

1

10

100

1000

i386 i486 Pentium Pentium Pro Pentium II Pentium III Pentium IV NuclearReactor

W/c

m2

i386 i486

Pentium

Pentium IIPentium Pro

Pentium III Pentium IV

Nuclear Reactor

1

10

100

1000

i386 i486 Pentium Pentium Pro Pentium II Pentium III Pentium IV NuclearReactor

W/c

m2

1.51.5µµ 11µµ .7.7µµ .5.5µµ .35.35µµ .25.25µµ .18.18µµ .035.035µµ

Hot PlateHot Plate

Fred Pollack, IntelFred Pollack, Intel

Required Performance for Multi-Media Processing(source ITRS Design ITWG July 2003)

GOPS0.01 0.1 1 10

VideoVideo

AudioAudioVoiceVoice

CommunicationCommunicationRecognitionRecognition

GraphicsGraphics

FAXModem

2D Graphics

3D Graphics

MPEGDolby-AC3

JPEG

MPEG1Extraction

MPEG2 ExtractionMP/ML MP/HLCompression

VoIP Modem

Word Recognition

Sentence Translation

100

Voice Auto Translation

10Mpps 100Mpps

MPEG4

Face RecognitionVoice Print Recognition

SW Defined Radio

Moving Picture Recognition

1/19/2005 26®

GOPS: Giga Operations Per Second

SoC at the heart of conflicting trends

ST20ST20

MPEG2 MPEG2 VideoVideo

Dolby Dolby AC3AC3

FEIFEI

LinkLink

2 x 3 DAC2 x 3 DAC

Den

cD

enc

Time-to-market:Time-to-market:Process roadmap

accelerationConsumerization

of electronic devices

Process roadmap acceleration

Consumerizationof electronic devices

Complex systems:Complex systems:uCs, DSPs HW/SWSW protocol stacksRTOS’sDigital/Analog IPsOn-Chip bussesProcess options

explosion (analog, RF, imagers, …)

uCs, DSPs HW/SWSW protocol stacksRTOS’sDigital/Analog IPsOn-Chip bussesProcess options

explosion (analog, RF, imagers, …)

1/19/2005 27®

Deep sub micron effects:Deep sub micron effects:crosstalk

electro migrationwire delays, on-chip-variation

mask costs (OPC, PSM)copper wires

crosstalkelectro migration

wire delays, on-chip-variationmask costs (OPC, PSM)

copper wires

1/19/2005 28®

Static versus Dynamic Power

Dynamic Power per Chip is rather stable due to system limitation: mechanical / batteryDynamic Power is under control: P=CV2f• VDD is decreasing (slowly)• Power management is in practice (clock gating, power shut

down, …)Static Power is not under control: natural leakage of transistor multiplied by 10 every 2 years:• Power shut down is the only way to cut leakage• Very low voltage retention or zero leakage Non Volatile

memories are potential solutions (Flash, MRAM)Static Power is becoming as high as Dynamic Power at high temperature (wasted power, no solution)

1/19/2005 29®

Gate and Interconnect Delay vs technology node:

Good for Dynamic Power as well

05

1015202530354045

0.65 0.5 0.35 0.25 0.18 0.13 0.1

technology (µM)

dela

y (p

S)

Interconnect Delay, Cu & Low KInterconnect Delay, Al & SiO2Gate DelayTotal AlTotal Cu

Al 3.0µOhm-cm

Cu 1.7µOhm-cm

SiO2 K = 4.0

Low K K = 2.0

Al & Cu 0.8µ thick

Al & Cu line 43µ long

1/19/2005 30®

1

10

100

1000

10000

100000

300 400 500 600 700 800

Ion (µA/µm)

Ioff

(LO

G pA

/µm

)

C350C250

C180

C090GP

C120GP

C120LP

Ion/Ioff evolution is a BIG concern

1/19/2005 31®

SOI ?Advantages:• Reduced S/D junction capacitance• Full dielectric isolation => latch up immunity• BOX & STI cap are nearly null

Benefits:• power/performance improvement

C

GATE

TR.OX

SOURCE DRAIN

P -WellC2 C2

SiSUBSTRATE

N+ N+P+

TR.OX

BULK

TR.OX

C

D

GATE

BURIED OXIDE

Si SUBSTRATE

BURIED OXIDE400nm

TR.OX

SOURCE DRAIN

C1 C1

Si 150nm TR.OXN+ N+P+

SOI

1/19/2005 32®

Results in 120nm SOI

improved performances (on SRAM)

The gain achieved on 0.12um SOI technology corresponds to the next generation on Bulk = 90nm

Power Supply

Speed Gain

Dyn Power Gain

LeakageGain

1.08V 0 % 20% x 0.1

1.2 V 10% 17% X 0.15I

1.32 V 20% 14% x 0.5

1/19/2005 33®

Flash NOR Cell – ST vs. ITRS Roadmap

0.2480.186

0.34

0.125

0.061

0.81

0.16

1.2

0.32

0.46

0.080.05

0.01

0.1

1

10

0.0 0.1 1.0Technology [um]

cell

size

[um

2 ]

ITRS 2001

ST

10 F2

1/19/2005 34®

Low Power Design ActivitiesSystem Level

RTOSMemory size and bandwidth optimisationArchitecture Power/Performance trade-off

RTL to LayoutActivity control

Gated clockPower based synthesis

Leakage controlSupply controlVT control thru back-biasMix High-Speed and Low-Leakage

Smart Power/Low-voltage operationMulti-voltage supportOn-chip voltage regulator(s)

Disk Drive Controller0.13um

0.25um SiGe BiCMOS

GSM Power Management

Research activities Labs / Universities

90nm ST20 / ST40

1/19/2005 35®

Low-Power techniques for

wireless Power-up control

VddSleep

Vdd

Core power pads with switches

Vddfillercut

Io pad supply

Vdd Sleep pad zone

Two supply zones: Vdd and VddSleep.Specific rules at RTL for boundary between Vdd and VddSleep areasGnd is common for all cells.Pads are always powered.3 power pads with embedded switches

1/19/2005 36®

Single Package Triple Stacking

Multichip chip wire bonding

Triple stacked die

1/19/2005 37®

Design / Manufacturing links

1/19/2005 38®

Design For Manufacturability Gains

Reliabilityimprovement

Acceleration for ramp-up process (~months)

Yield gain for mature process (3 to 5%)

Standard approach

DFM approach

Process Maturity

Prod

ucts

Yiel

d

Robustnessincrease(versus design marginalities)

1/19/2005 39®

> Library and IP maturity, knownresults

> Chip contents

> Engineering data

LibYielddatabase

Impact of Test: From Design to Volume Manufacturing

Qty (Millions Parts)

TimePRE

PRODUCTIONPROTOTYPING MASS PRODUCTIONDESIGN

Production Ramping

Up Review

Productcharacterisation

TAG SCAN

PG ReviewMaturityCheckpoint

Yield Data Review

1/19/2005 40®

Predictive Chip Yieldbased on IP content

0%

20%

40%

60%

80%

100%

DP

R2H

D

RO

8L

SP

S2H

D

SP

S6

AR

M

CO

RE

LIB

8DH

S

CO

RE

LIB

8DLL

PLL

81

IOLI

B_8

0

LF10

othe

r

------

-

CH

IP

YieldYield W/ rep

Design / Manufacturing Yield Optimization

Design For Test

FailuresFault Isolation

L1

L2

Analog

Digital

1/19/2005 41®

Automatic Test Equipment

Wafer

Reticle

ManufacturingDesign

FIBDesign Intelligence:

CD SEM

Critical Regions and SitesFailed Nets

Wafer InspectionCourtesy of Cadence, Applied Materials

1/19/2005 42®

SOC design challenge

1/19/2005 43®

Today’s Reality

Complex SoC projects are draining the companies resources and developments are lagging behind the technology capacity.Today SoC project non-recurring expenses (NRE) are 10-50M$ should have 50-500M$ revenues to balance an acceptable ROI.Several $B already invested on IPs and integrated functions during last years.Design re-use must be exploited at all levels included sub-system re-use.

$-

$5.00

$10.00

$15.00

$20.00

$25.00

$30.00

1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005

ASIC Revenue/Design Start Design Costs

Revenue per ASIC is Not Increasing as Fast as Fixed Costs of Cutting Edge Design

0.35µm 0.25µm

0.18µm

0.13µm

90nm

$ Millions

Source: Gartner Dataquest 2002/2003; I.B.S. 2002…Custom EDAC Study

1/19/2005 44®

1/19/2005 45®

Photomask Costs Are Increasing…

$102$167

$310

$985

$62826 2830 32 34

$-

$100

$200

$300

$400

$500

$600

$700

$800

$900

$1,000

0.35m 0.25m 0.18m 0.13m 0.09m

Process

($Th

ousa

nds)

05101520253035404550

Tota

l Mas

k La

yers

Mask Set Cost Mask Layers

Source: IC Insights, 1/2003

1/19/2005 46®

S/W and H/W Complexity Factors1012

19701960 1980 20001990 2010 2020

Gates/chip: 2x / 18 monthseSW/chip: 2x / 10 monthseSW productivity: 2x / 5 years

Lines of code

H/W: +50% / year

eS/W

: +14

0% / y

ear

Gates

1010

108

106

104

102

1

1/19/2005 47®

Closing the Design Productivity Gap

1981 1995 2009

CAGR 58%

100000

0.01

Pro

duct

ivit

y(K

)Tra

ns.

/Sta

ff-M

o.P

rodu

ctiv

ity

(K)T

ran

s./S

taff

-Mo.

CAGR 21%

System LevelSpecification

HW-SWCo-verification

IP Reuse

1000

Logi

cTr

ansi

stor

s pe

rC

hip

(M

)Lo

gic

Tran

sist

ors

per

Ch

ip (

M)

0.001

1/19/2005 48®

Embedded Software Development Requires as Much/More Design Effort Than

Hardware

Concurrent Hardware/Software Design

Standard Flow

Spec Archi Design Fab Breadboard Softwaredevelopment

SystemIntegration

SystemValidation

Time

GAINSystem

ValidationSoftware

development

Methodology Extensions

SystemIntegration

1/19/2005 49®

1/19/2005 50®

HW/SW fast prototype platform

Faithful representation of the final designAvailable much sooner than the final siliconGuaranties the real-time behaviorValidation of the fundamentals of the SoCHW/SW architecture

HW Emulation

CELARO

RTL Design

MMCI/F

FLASHI/F µ8051

MUX

AnalogBlocks

To MMChost

ToFLASH

RTL Design

MMCI/FMMCI/F

FLASHI/F

FLASHI/F µ8051µ8051

MUXMUX

AnalogBlocksAnalogBlocks

To MMChost

ToFLASH

• 1w setup-time• ~0.5MHz

• Real M58LW128FLASH chip in-circuit

• SW host running @100KHz• Connection of HW host ongoing

1/19/2005 51®

1/19/2005 52®

First Prototype Platform: Aptix

ST120 Module

ARM7 Module

Interface to RF/Tester

Virtex FPGA (GSM/GPRS modem)

Memory boards

1/19/2005 53®

FPGA-based Prototyping Environment

RF GSM/GPRS Board

JTAG Connection to SW Debuggers

STEP1 BaseBandBoard

1/19/2005 54®

IP Reuse ProgramOrganization

company program “Design Methodology & IP Reuse”, CEO sponsoredcorporate driven CR&D + cross-divisional Committeedomain-specific Work Groups RTL2Layout, AMS, SLD, DFT, Functional Verif., Power, …intranet information site CAD On Line portal > K9 IP Reuse Pages

Reuse standardsadherence to industry approach VSIA; RMM; Qualitydeliverables / views BlueBook + Unicad ExtensionIP packaging bbview (mapping from BB logic views to IP physical files)HDL coding style Design Conventions + HAL associated checking toolOn Chip Bus VCI-close STBus; AMBA

MethodologyDevelopment flow Synopsys based QuartetOCB support STBus, AMBA Platform kitsSystem Level SL model deliverables (TLM, BCA…)Verification dynamic, formal, H/W-S/W, integration

InfrastructureDesign Data Managt., Bug tracking Products from Synchronicity, RationalIP Quality (IP=Product) IPScreen Certification; LibYield Maturity trackingIP Procurement IP On Line catalog; Procurement, Exchange procedures

IP certificationUSB2.0 example

If you pass OK, you have the logo

ST USB2 PHY

1/19/2005 55®

1/19/2005 56®

NortelNortelNokiaNokia

AlcatelAlcatelSynopsysSynopsys

VirageVirage

IP IP ExternalExternalProviderProvider

ARMARM

IP IP DeliverDeliver

yy

Corporate IP Catalog Project

IP IP InternalInternalProviderProvider

IP IP InternalInternalDeliveryDelivery

1/19/2005 57®

Multi-Site Collaborative Design(Synchronicity-based)

Memory RandomLogic

CPU PCI

Graphics

Multiple Designers Multiple Designers Multiple Locations Multiple Locations

One ChipOne Chip

1/19/2005 58®

Network on ChipIn 45 nm technologies, the intra-chip propagation delay is predicted between six and ten clock cycles Wire issues increase reaching up to 20% of the project design effortsLatency • the intra-chip propagation delay• Processor clock cycle times / memory access times• Processors / Co-processor• Within five years, the large majority of SoCs will run on heterogeneous

embedded processors. Today simple Set-Top Box SoC host 6 different processors

On-chip traffic management between integrated functions and the associated methodology will be the forthcoming challengesFocus and complexity are moving • FROM GATES TO WIRES

1/19/2005 59®

Flexible and Reconfigurable SoC

1/19/2005 60®

SOC flexibility and Configurable LogicSOC emerging problems• rising cost of masks• shorter market windows• need to quickly adapt to new customer requirementsneed of• level of programmability• flexibility on-chip

Set of solutions to be provided to our designers• Laser-fuses• Electrically programmable fuses or anti-fuses • Embedded OTP• Embedded ROM• Embedded SRAM with external ROM/Flash• Natural, low-density, embedded Flash in standard CMOS, up to Kbits• Embedded FPGAs• Embedded mask-programmable sea-of-gates.

1/19/2005 61®

Reconfigurable IC with eASIC

0.13um HCMOS9 technologyIncludes 12 eASICores (300kraw gates)Single-mask configuration

Customization: 110k gates + 28kb DP-RAM • Area penalty: 3 - 3.5 x• Speed penalty: 2 - 2.5 x

12eASICores(300k raw

gates)

ARM9468k/4k

SRAM

SRA

M200k gates SC

PLL

1/19/2005 62®

eFPGA Reconfigurable SoC’s

0.18um Working SiliconSpeed: 110 MHzAverage Power @50MHz: 160mWPaper at ISSCC 2003

0.18um Working SiliconSpeed: 180 MHzAverage Power @ 50MHz: 140mW-> in use in 0.13um

1/19/2005 63®

The competition

1/19/2005 64®

TAIWANUn pays exemplaire :

•Ampleur et variété des formes d’aides

•Ampleur des résultats

9 secteurs prioritaires (plan de 1991)

· Semi-conducteur· Communication· Aérospatial· Informatique· Précision machines et automatisation· Advanced Materials Industry· Chimie et Pharmaceutique· Médical · Contrôle et traitement de la pollution

R&D

Fiscalité

Industrialisation

1/19/2005 65®

TAIWAN

Luchu

52 fabs

10 fabs

TSMC, UMC, VANGUARD, VISHAY, …

300 mm

Fab universitaire/Labo public

Centre de R&D

Parcs technologiques

En 2002, Taïwanassure près de 10% de la production mondiale

100 000 emplois

21 millions d’habitants

ITRI/ERSO

Source : SEMI

1/19/2005 66®

Impact sur les entreprises taïwanaises

Dépenses de R&D des grandes entreprises du semi-conducteur de Taiwan en 2000 :

TSMC: 164 M$ (3% du CA) , UMC: 180 M$ (5% du CA), soit moins de la moitié de ce qu'elles devraient être pour être en mesure avec leur chiffre d'affaires et leur activité.

Mécanismes fiscaux pour déduire les investissements :

Double déduction des investissementsFiscalité réduite (exemption de 5 ans d’impôts sur les bénéfices)

Alliances pour développements de procédés < 0.1 µm

ST

IBM

SONY

AMD

AGERETexasInst.

INTEL

TOSHIBATSMC

MOTOROLAPHILIPS

MATSUSHITA

MITSUBISHI FUJITSU

NEC HITACHI

SHARP SANYO

ROHMOKI

NANYA

MOSEL

WINBOND

SAMSUNG

HYNIX

MICRON

Chartered

LSI Logic

Accord R&D

Crolles

East Fishkill

Hsinchu

Séoul

Tsukuba

Singapour

Portland

ELPIDA

UMCINFINEON

1/19/2005 67®

1/19/2005 68®

Monsieur le President Jacques Chiracinaugure l’alliance Crolles2

1/19/2005 69®

Monsieur le President Jacques Chiracinaugure l’alliance Crolles2

1/19/2005 70®

ConclusionsAlliance and co-competition.Large portofolio of Technologies adapted to different SoC market needs: low power, highspeed, RF, analog, imagers…Strong interactions between:• Wafer Manufacturing• Technology Development• IP design• CAD Development

Low-power:• Leakage is here to stay!!!• Design techniques / Process variants can help• More tools needed to predict/implement power solutions at all

abstraction levels

1/19/2005 71®

ConclusionsCo-competition

Low-power:• Leakage is here to stay!!!• Design techniques / Process variants can help• More tools needed to predict/implement power

solutions at all abstraction levels