A High-Speed Hardware A High-Speed Hardware Implementation of the LILI-II Implementation of the LILI-II Keystream GeneratorKeystream Generator

Paris Kitsos Paris Kitsos ...in cooperation with...in cooperation with Nicolas Sklavos and Odysseas Nicolas Sklavos and Odysseas

KoufopavlouKoufopavlou

Digital Systems and Media Computing Laboratory

School of Science & TechnologyHellenic Open University, Patras, Greece

e-mail: pkitsos@ieee.org

Presentation OverviewPresentation Overview

• LILI-II specifications overview• Proposed hardware architecture• VLSI implementation results• Comparisons in terms of FPGA area,

clock frequency and performance with existing works

LILI-II Specifications (I)LILI-II Specifications (I)• LILI-ΙΙ generator is a clock-controlled

nonlinear filter generator • LILI-II

– Use two binary LFSRs and – Two functions in order to generate a

pseudorandom binary keystream sequence

• The components of LILI-II grouped into two subsystems, based on the functions they perform– Clock control and Data generator

LILI-II Specifications (II)LILI-II Specifications (II)

• The LFSR for the clock-control subsystem is regularly clocked

• The output of the Clock-Control LFSR control the Data-Generation LFSR

LFSRC

x0 x126

fc

Clock-Control

LFSRd

x0 x122

fd

Data Generation

c(t)

x1 x96z(t)

LILI-II Specifications (III)LILI-II Specifications (III)• Clock-control LFSR (LFSRc)

– Use a primitive polynomial with length equal to 128

• The function fc defined as

• Data Generation LFSR (LFSRd)– Use a primitive polynomial with length equal to 127

• The Boolean function fd has 12 inputs for the LFSRd stages and defined by a truth table

12),( 12601260 xxxxf c

Proposed Architecture (I)Proposed Architecture (I)• The proposed architecture consists of the clock-

control subsystem and the data generation subsystem

• Operation– Initialization phase – Keystream generation phase

• Initialization Phase– Use the secret key and initialization vector and operates

twice and the output feeds the LFSRs as new values

• Keystream generator Phase– When the initialization phase finish the generator

produce the appropriate keystream bits.

Proposed Architecture (II)Proposed Architecture (II)

LFSRC

x0 x126

fc (3-bit adder)

Clock-Control

LFSRd (1)

fd (4096x1 ROM)Data Generation

c(t)

z(t)

MUX

3

ClockPulses

Clk

Clk

3 Pipeline Registers

Clk

2 Pipeline Registers

Clk

1 Pipeline Registers

Clk

4

2

2

MUX MUX

D_ff

LFSRd (2)

LFSRd (3)

LFSRd (4)

AND1

AND2

AND3

AND4

Proposed Architecture (III)Proposed Architecture (III)

• The Clock-Control subsystem is comprised by the LFSRc, the function fc and the Clock Pulses components.

• The fc is a simple 3-bit adder.• The Clock Pulses control the

LFSRds through the AND gates.

Proposed Architecture (IV)Proposed Architecture (IV)• The Data-Generation subsystem is

comprised by 4 LFSRds, 4 AND gates, the function fd, 6 Pipeline Registers and 12 4x1 Multiplexers.

• Pipeline registers are located in the LFSRd(i) outputs in order to equalise the data delays between of them

• The multiplexers (MUXs) are used in order to combine the appropriate LFSRds positions

• The fd function is implemented by ROM with 4096 per 1-bit elements

A Different ApproachA Different Approach• Many applications, in the same device, demand

different security levels. This could be achieved with the usage of reconfigurable LFSRs, if different feedback polynomials selected any time.

D D D DD

p(0) p(1) p(n-1)p(n-2)

clock

input

LFSR

P(i) registeri

VLSI Implementation ResultsVLSI Implementation ResultsDevice VIRTEX 2V1000FF896

Resources Used Avail. Utilization

I/Os 391 432 90 %

Function Generations

938 10240 9.1 %

CLB Slices 469 5120 9.1 %

Dffs or Latches

693 11536 6 %

Block RAM 1 40 2.5 %

ComparisonsComparisonsStream Cipher

FPGA Device F(MHz)

Bit rate (Mbps)

LILI-II (previous)

2V6000FF1152

243 243

A5/1 2V250FG25 188.3 188.3

E0 2V250FG25 189 189

Edon80 2V250FG25 220.75 220.75

WG ASIC 1000 125

Proposed V400BG560 158.5 158.5

Proposed V400EBG560 230 230

Proposed 2V1000FF896 366 366

Conclusions Conclusions

• An efficient hardware implementations of the LILI-II keystream generator was presented

• Achieves a throughput equal to 366 Mbps

• The proposed architecture is more hardware efficient than previous works

Questions ?Questions ?