Digital synchronisation of switching transistors

D.W. AucklandR. ShuttleworthT.W. Wong

Indexing terms: Digital control, Integrated circuits, Transistors

Abstract: A digital technique is described for con-trolling the application and removal of base driveto parallel connected power transistors so thatthey switch on and off in synchronism, and withminimum power dissiptation. The control cir-cuitry was designed specifically for integration onan uncommitted logic array to produce a dedi-cated integrated circuit. This circuit, together withits power transistor, associated base drive andemitter current sensing circuitry forms a powermodule which can be operated in parallel withother similar modules to form a switch modepower regulator of any required current rating.

1 Introduction

Transistors operating in switched mode are being usedincreasingly in fast acting power regulators. Inevitably,there are instances where, to meet load requirements,transistors have to be operated in parallel to achieve thenecessary current ratings. But devices of nominally thesame type can differ considerably, particularly withrespect to storage and delay times. Because of this, paral-lel connected transistors, when driven from a commonsource, tend to share load unequally during switchingtransitions [1]. Consider for example two parallel con-nected transistors regulating current to an inductive loadfitted with a free wheeling diode. During turn-on, thefaster transistor takes an undue share of the load currentwhilst switching full collector voltage. It therefore suffersexcessive power dissipation. During turn-off the slowertransistor suffers, taking an undue share of load currentagain under the influence of full collector voltage thisbeing rapidly reinstated due to load inductance as thefirst transistor begins to turn-off.

Various techniques using passive circuits have beendevised to counteract the excessive dissipation experi-enced during switching transitions [2]. In every case,operational sacrifices such as regulator bandwidth areattendant upon their use. An alternative, with lessadverse effects on performance, has been devised [3, 4].In this, an even distribution of current between tran-sistors is achieved using feedback control to advance andretard base drive to the transistors independently, tocompensate for intrinsic differences in turn-on and turn-off times.

Paper 5861B (P6), first received 2nd December 1986 and in revised form8th October 1987The authors are with the Electrical Engineering Laboratories, The Uni-versity, Manchester M13 9PL, United Kingdom

The system worked, and an arrangement was envis-aged whereby each power transistor together with itsbase drive controller would comprise an independentunit. This could be connected in parallel with anynumber of similar units according to load demands,without incurring transitional load sharing problems. Butpractical considerations prevented this, for the controllersemployed extensive analogue circuitry involving prob-lems of cost, reliability, long term stability and setting updifficulties.

Many of the control functions could have been imple-mented digitally using standard integrated circuits, butwith no saving in component count. However, recentyears have seen the development of microcircuit uncom-mitted logic arrays (ULAs) which provide a cost effectivemethod for the production of small batches of purposedesigned integrated circuits. The concept underlyingULA technology is that of the standard chip consisting ofa matrix of identical logic cells complete except for thefinal metallisation pattern used for interconnection. Thispattern can be specified and applied to suit particularcircuit requirements. Standard chips contain hundreds oflogic cells capable of switching at frequencies of order10 MHz so that a comprehensive range of functions canbe accommodated.

This paper describes a digital controller designed spe-cifically for integration on an uncommitted logic array toproduce a single integrated circuit controller. This in con-junction with a power transistor and associated drive andcurrent sensing circuitry forms a power switching modulefor operation in parallel with other similar units as orig-inally envisaged for the analogue system described byAuckland et al. [3] and Foo [4],

2 Principle of operation

Synchronous switching of parallel connected transistorsmay be said to be achieved when the energy dissipated byeach one, during switching transitions is the same. Thisciriterion is very nearly satisfied when the emitter cur-rents through the transistors all reach half their steadyvalues at the same time [3]. The system to be describedwas designed to achieve this.

Fig. 1 is a block diagram illustrating the principle ofoperation. For simplicity, only two transistors are shown.The current through each one is sensed using a low-valued noninductive shunt resistor R, the voltage acrosswhich is applied to one input of an operational amplifierin a comparator unit. The other input is driven from asample and hold circuit whose output is proportional tohalf the value of the emitter current flowing in the pre-vious switching cycle. The comparator output is thereforea square wave the transitions of which occur as the risingand falling edges of its transistor's emitter current reach

IEE PROCEEDINGS, Vol. 135, Ft. B, No. 2, MARCH 1988 97

half steady state value. This output is applied to the con-troller where it is compared in phase with the outputfrom the master oscillator. The controller advances or

Vcc

Phase differences between Wc, Wc and their respectivereference waveforms are resolved into clock periods. Thecontrol loops turn the transistor on and off via the base

inputsignal load

masteroscillator

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controller

—

basedriveunit

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controllerbasedriveunit

edgecomparator

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Fig. 1 Block diagram of two-transistor control system

retards base drive to its transistor, in proportion todetected phase differences, so reducing them to negligibleproportions. Thus, the emitter currents of both tran-sistors are synchronised to the master oscillator outputand therefore to each other.

The waveforms associated with the digital synchro-nisation of a transistor to the master oscillator are shownin Fig. 2. The master oscillator generates a high fre-

Si

So

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Fig. 2 Switching waveformstt-t6 — times of events during turn-onta-tf — times of events during turn-off

quency clock waveform, and two unity-mark to spacesquare waves S7 and So at the specified transistor switch-ing frequency. S7 and So act as references for two inde-pendent phase sensitive digital feedback loops within thecontroller. That associated with S7 synchronises tran-sistor current, i.e. at turn on in accordance with the com-parator output Wc, whilst that associated with Sosynchronises turn off, in accordance with the signal Wc.

drive unit (Fig. 1) which is a fast acting bistable element.A pulse (BN) from the turn-on loop, sets the bistable tosupply base-current which is removed following a reset-ting pulse (BF) from the turn off loop.

Both loops operate in the same way, which will bedescribed for turn-on. Referring to Fig. 2, with the feed-back path between the comparator unit and controlleropen, the rising edge of Sj at tx would trigger the basedrive unit to deliver a turn on pulse, nd clock pulses laterat time t2. Following this, the emitter current wouldbegin to rise, reaching half its steady state value after nrclock periods, at time t3. This process would continue forevery cycle of the master oscillator, with the emittercurrent rising to half its steady value nd + nT clock pulsesfollowing the rising edges of S7 at time tv

Closing the feedback path instigates synchronisation.Referring again to Fig. 2, assume that the feedback pathis closed immediately prior to tv The output from theedge comparator, Wc, which is now applied to the con-troller, again rises at t3, marking the instant of halfemitter current. The controller registers the phase differ-ence between t3 and the application of base drive, at t2,by counting the clock periods nr. The controller subtractsnr from nd and advances the next turn on pulse from thebase drive unit accordingly, so that it occurs at t5, nd— nr clock pulses after the rise of S7 at t4. Thus, the base

drive and therefore the rise in emitter current areadvanced relative to S7 by an amount equal to the tran-sistor's rise time. This process is repeated during eachswitching cycle, so that rising edges of the emitter currentand Sj remain synchronised with a permanent phase dis-placement of nd clock periods. The turn-off loop synchro-nises the fall of emitter current in the same way so that itreaches half its steady value nd clock periods followingthe rising edges of So.

Pulse width modulation is imposed upon the tran-sistor's operation by varying the phase of S7 with respectto So, in proportion to the master oscillator inputvoltage (Fig. 1). Since the turn on loop maintains syn-chronism between St, and rising edges of emitter current,

98 IEE PROCEEDINGS, Vol. 135, Pt. B, No. 2, MARCH 1988

and the turn off loop maintains synchronism betweenfalling edges of emitter current and the invariant So,transistor ON time is directly proportional to the masteroscillator input. The response to changes in phasebetween Sj and So occur within 1 cycle of the clock wave-form used in the turn-on loop. Since the frequency of thiswaveform is of order 10 MHz, the response is less than0.1 fis, and so may be regarded as instantaneous.

3 The control and master oscillator circuits

The control and master oscillator circuit design wasinfluenced by the choice of ULA for the control circuitry.This has to be fast if transistor delays, particularly duringturn on, are to be resolved satisfactorily. The type chosenwas the Ferranti 90c, which has a capacity of 990 logiccells per array. These cells are comprised of single bipolartransistor NOR gates capable of operating up to20 MHz. This determined the master oscillator fre-quency, enabling the controller to achieve a temporalresolution in its phase measurements, of 50 ns.

The logic system used to implement the control func-tions was based on 8 bits, being determined by thenumber of gates available for active logic. This was lessthan the 990 contained in the logic array since somegates are lost to accommodate signal highways. As ageneral rule, at least 30% of the gate capacity must beleft available for highway use. In the present case 580 ofthe 990 gates were consumed by active logic, so leavingadequate space for signal highways [5].

Fig. 3 is a block diagram of the controller. Clockwaveforms C7 for the turn on loop, and Co for the turnoff loop, together with S7 and So are derived within themaster oscillator from a 20 MHz square wave generator.So and Sj are obtained by frequency dividing the gener-ator output according to the transistor switching fre-

quency required. For example, division by 4096 gives aswitching frequency of 4.9 kHz. The phase shift betweenSj and 50 is implemented by a retriggerable monostableconfigured so that the displacement imparted is directlyproportional to the master oscillator input voltage.

The clock waveform Ct comes directly from the20 MHz generator, whereas Co is obtained after dividingthe generator output by two. This reflects differences inthe turn-on and turn-off delays of the power transistor,and the need to resolve these delays in terms of clockperiods, using 8-bit counters in the control unit.

Fig. 3 shows the flow of data as it passes through theintegrated circuit controller from the master oscillatorand edge comparator. The way in which this data is usedto effect synchronous switching between St and transistorturn on, is the same as for So, and turn-off. The turn-oncase will be used to illustrate the operations involved.Thus, referring to Fig. 3, the number nd — nr indicated inFig. 2 is derived in the subtractor, and used to preset thedown counter. This counter is initiated by rising edges ofSj, when its contents are decremented by clock pulsesCj. When zero is reached, the counter output undergoesa positive transition, triggering the base drive bistable sothat it delivers current to the base of the power transistorwhich starts to turn on. Thus base drive is advanced nrclock pulses relative to the master oscillator waveform,where nr is the perceived turn on time of the power tran-sistor.

As the output of the base drive bistable goes positive,it opens the clock gate allowing clock pulses C7 to entercounter CA or CB, depending upon the state of thecounter selector. The clock gate is closed by the risingedge of Wc from the edge comparator so that the selectedcounter registers a figure equal to the rise time of thepower transistor in terms of clock pulses C7. This figureis nominally equal to nr but CA and CB are selected on

turn on loop

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downcounter

downcounter

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turn off loop

Fig. 3 Block diagram of controller

IEE PROCEEDINGS, Vol. 135, Pt. B, No. 2, MARCH 1988

close to load

open

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99

alternate half cycles of the master oscillator waveform.Their contents are added, and divided by two so that thevalue nr applied to the subtractor is an average takenover two switching cycles.

Averaging the delay time avoids instability caused byinteractions between controllers as they attempt to syn-chronise the switching of their respective transistorsagainst variations in delay times, induced by controlaction. The effect occurs during turn-on where it is accen-tuated by the fact that turn-on delays are typically100 ns, which represents only two master oscillator clockcycles. Consider the synchronisation, using non-averaging controllers, of two transistors A and B, whereA is the faster device. When the transistors first turn on,A takes all the load current and saturates first. TransistorB turns on with low collector emitter voltage, so that itsrise time, which is indirectly proportional to Vce, is con-siderably extended. The controller of B advances its basedrive accordingly to the extent that B turns on before A.Current and voltage conditions at A now cause its risetime to extend, so that the turn-on sequence reversesduring the next switching cycle. The process repeatsindefinitely with the transistors turning on before andafter each other alternately. Using an average value of nr,taken over an even number of switching cycles, filters outvariations in delay time so imparting stability to thesystem.

Instability does not occur during turn-off becauseboth transistors' collector currents undergo turn-offunder the influence of full collector voltage. The cross-coupling phenomena induced during turn-on is thus notpresent and stability is assured without the need toaverage delay time measurements. Nevertheless, averageddelays were used for turn off since this eased the processof integration by making the circuitry symmetrical.

4 Performance

The effectiveness of the technique described was tested inthe control of two parallel connected 2SD646A, 50 amp,450 V power transistors used to regulate the armaturecurrent of a 12 hp DC motor. Pulse width modulationwas used at a switching frequency of 4.9 kHz. The tran-sistors exhibited a difference in turn-on times of 100 nsand in turn-off times of 1.3 /is. That the controllers suc-cessfully compensated for these discrepancies is apparentfrom the oscillograms of Figs. 4 and 5. Emitter currentsof the two transistors during turn-on and turn-off whendriven from a common base drive circuit are shown inFig. 4 and follow the familiar pattern. The emitter currentwaveforms with separate digitally controlled base drivesare shown in Fig. 5. Current distribution during turn-offshows a marked improvement. The turn-on transition,although synchronised at half steady state current,exhibits current overshoot in both transistors. This is dueto the flow of freewheeling diode reverse-recovery currentover which the controllers have no influence.

To ensure the safety of the transistors whilst operatingwith common base drive, the comparative results of Figs.4 and 5 were obtained at appropriately restricted cur-rents. The effectiveness of digitally controlled base drivewas demonstrated for higher currents when it enabled thetransistors to switch a steady current of approximately100 amps without failure, sharing it evenly in a formidentical to that shown in Fig. 5. Thus is was that thetransistors were able to operate in parallel without derat-ing to accommodate current overshoot due to device mis-match. With this no longer a factor, safe operation is

determined by the magnitude of the free wheeling diodereverse recovery current pulse at turn-on. In the presentcase, this was well below the 100 A surge limit for thetransistors used.

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Fig. 5 Emitter currents of two transistors with separate digitally con-trolled base drivesa During turn-onb During turn-off

Before using the controller, the delay times of thedevices to be controlled have to be known approx-imately, to ensure that for the chosen clock frequency thenumbers nr and nf will always be less than the presetnumber nd. If, for example nr is greater than nd, the downcounter in the controller's turn-on section will reach zeroprematurely. The associated transistor will turn on

100 1EE PROCEEDINGS, Vol. 135, Pt. B, No. 2, MARCH 1988

equally early and fail, owing to overcurrent. Overflowduring turn-off could also result in the failure of one ormore parallel devices.

In the integrated circuit controllers, the value of nd wasfixed for both the turn-on and turn-off loops at themaximum of 255. With fixed values of nd the overflowproblem is avoided by correct choice of clock frequency.In the present case, 10 MHz was used for turn-off and20 MHz for turn-on. The former was determinedknowing that for the 2SD646A transistor, the maximumquoted turn-off time is 10.5 /is. With a turn-off clock fre-quency of 10 MHz, nf is 105. This is well within theallowed value. The maximum quoted turn-on time for the2SD646A transistor is 1 /is, representing 20 clock pulsesat 20 MHz so that even at this higher frequency, over-flow is not a problem. Whilst the use of two differentclock frequencies provides a means of avoiding overflowit does restrict the minimum on time of the transistors. Inthe present case, this amounted to 12.75 /is being equalto the difference between the time to fill the two control-ler down counters at their respective clock frequencies.

The time taken for the controllers to impose synchro-nous operation on their respective transistors followingthe application of supply voltage is determined by thetime to obtain nf and nr. It follows from the use ofaveraging to achieve stability that nf and nr are built upin two stages. In effect, the averaging process introduces adominant time lag which determines synchronisationtime. Thus the controllers take a total of 3 switchingcycles to achieve synchronous operation. This has notproved a problem in the operation of the two-transistorregulator used to obtain the results of Fig. 5, since theinitial flow of current was limited to safe values by theload and supply impedance. Once synchronised, theloops advance and retard base drive to their respectivetransistors following variations in the switching time ofeach transistor as the load current changes. Using tran-sistors of the same type ensures that these variations areapproximately the same, so little or no corrective actionis necessary to maintain synchronisation. Hence the effectof the averaging delay is reduced to insignificant propor-tions. This was confirmed in the present case by observ-ing the phase differences between the rising, and betweenthe falling, edges of the square wave output to the basedrive units of both transistors following a step change ofmotor armature current, created by short circuiting aseries connected resistor. The change was of 40 A andtook place over a 5 ms period in accordance with thearmature time constant.

By imposing synchronous operation on the tran-sistors, the power dissipation which they suffer duringswitching transitions is much reduced to an extent thatsnubbers become less essential for reliable operation.They were not used in the present regulator but had theybeen, their implementation would have been eased by thepresence of the control loops. Synchronously controlledtransistors behave as one so that the snubber circuitsrequired absorb and dissiptate minimal quantities ofenergy during switching transitions arid therefore havethe least effect on modulation depth. Had a snubber beenused in the present arrangement, the turn-on controlloops would have required slight modification to accom-modate the surge of current at turn-on associated withthe discharge of snubber capacitance. This surge domi-nates the switch on transition, load current flow being

restricted by snubber inductance. The turn-on loops mustrecognise this dominance, controlling their respectivetransistors so that they share the surge equally. The mag-nitude of this surge is determined by the value of thecurrent limiting resistance present in the discharge pathand by the voltage on the snubber capacitor at theinstant of turn-on. It follows therefore, that the compara-tor reference signals used to determine current conditionsat turn-on should be obtained from the voltage acrossthe snubber capacitor rather than from across emittershunts as indicated in Fig. 3.

5 Conclusions

A digital control system has been developed which syn-chronises the switching of parallel connected transistorsso that they share load evenly during switching tran-sitions. The loops are fast acting, and do not restrict thefrequency response of the parallel group in terms of itsability to supply current or to modulate a carrier.

When synchronised, the transistors behave as a singledevice having a current rating equal to the sum of theindividual ratings. Since the transistors share currentevenly without overshoot during switching transitionsthey dissipate less energy than when uncontrolled. Thisallows the group to be operated at higher frequencies andalleviates the need for snubbers under some circum-stances. Should snubbers be required the circuitryinvolved is minimal leading to the least possiblereduction in switching frequency and bandwidth. Theeconomic advantages so realised far outweigh the cost ofthe controllers which, unlike snubbers, dissipate insignifi-cant quantities of energy and occupy very little space.

The control system was designed for integration on anuncommitted logic array and this has been done. A tran-sistor, together with its integrated controller, base-drivecircuit, and edge comparator circuitry forms a compactswitching module which can be operated in parallel withany number of similar modules. Recent developments inULA technology will shortly allow the edge comparatorcircuits to be configured adjacent to the digital circuitry,so reducing module size and complexity even further.

The techniques described have been applied to thesynchronisation of transistor switching. They could havebeen equally well demonstrated using thyristors as theswitching element.

6 Acknowledgments

The authors acknowledge the help of Mr A.T. Vahderand Mr E. Powner of UMIST who configured the ULA.This work was carried out with the financial assistance ofthe SERC, for which the authors are grateful.

7 References

1 REDOUTEY, J.: 'Parallel operation of switching transistors, thepower transistors in its environment' (Thomson, CSF, 1979), pp.207-229

2 CALKIN, E.T., and HAMILTON, B.H.: 'Circuit techniques forimproving the switching logic of transistors switches in switchingregulators', IEEE Trans., 1976, IA(12), pp. 364-369

3 AUCKLAND, D.W., FOO, C.F., and SHUTTLEWORTH, R.: 'Con-trol method for compensation of switching delays in transistors'. IEEProc. B, 1982,129

4 FOO, C.F.: PhD thesis — University of Manchester 19815 VAHDER, A.T.: MSc thesis dissertation — University of Manchester

1983

IEE PROCEEDINGS, Vol. 135, Pt. B, No. 2, MARCH 1988 101