Digital Electronics 4

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    Circui t Analys is Procedure

    by

    Dr.M.ManikandanAssociate Professor

    Dep t. o f Elec tron ics Engg .Anna Un iversi ty.

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    Overview

    Important concept analyze digital

    circuits

    Given a circuit

    Create a truth table

    Create a minimized circuit

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    Overview

    Approaches Boolean expression approach

    Truth table approach Leads to minimized hardware

    Provides insights on how to design

    hardware

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    The Problem

    How can we convert from a circuitdrawing to an equation or truth

    table?

    Two approaches

    Create intermediate equations

    Create intermediate truth tables

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    The Problem

    A

    BC

    A

    B

    C

    Out

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    Label Gate Outputs

    Label all gate outputs that are afunction of input variables.

    Label gates that are a function ofinput variables and previously

    labeled gates.

    Repeat process until all outputs are

    labelled.

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    Label Gate Outputs

    C

    A

    B

    C

    A

    B

    Out

    R

    S

    T

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    Approach 1: Create

    Intermediate EquationsStep 1: Create an equation for each

    gate output based on its input.

    R = ABC

    S = A + B

    T = CS

    Out = R + T

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    Approach 1: Create

    Intermediate Equations

    A

    B

    C

    A

    B

    C

    Out

    R

    S

    T

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    Approach 1: Substitute in

    subexpressions Step 2: Form a relationship based on input

    variables (A, B, C)

    R = ABC

    S = A + B

    T = CS = C(A + B)

    Out = R+T = ABC + C(A+B)

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    Approach 1: Substitute

    in subexpressionsAB

    C

    A

    B

    C

    Out

    R

    S

    T

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    Approach 1: Substitute in

    subexpressions Step 3: Expand equation to SOP

    final result

    Out = ABC + C(A+B) = ABC +

    AC + BC

    Out

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    Approach 1: Substitute

    in subexpressions

    A

    C

    Out

    B

    C

    AB

    C

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    Approach 2: Truth Table

    Step 1: Determine outputs forfunctions of input variables.

    A0000

    1111

    B0011

    0011

    C0101

    0101

    R0000

    0001

    S0011

    1111

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    Approach 2: Truth Table

    AB

    C

    A

    B

    C

    Out

    R

    S

    T

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    Approach 2: Truth Table

    Step 2: Determine outputs for

    functions of intermediate variables.

    T = S * C

    A000

    0111

    1

    B001

    1001

    1

    C010

    1010

    1

    R000

    0000

    1

    S001

    1111

    1

    T001

    0101

    0

    C101

    0101

    0

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    Approach 2: Truth Table

    A

    BC

    A

    B

    C

    Out

    R

    S

    T

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    Approach 2: Truth Table

    Step 3: Determine outputs for function.

    A

    0000

    1111

    B

    0011

    0011

    C

    0101

    0101

    R

    0000

    0001

    S

    0011

    1111

    T

    0010

    1010

    Out

    0010

    1011

    R + T = Out

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    Approach 2: Truth Table

    ABC

    A

    B

    C

    Out

    R

    S

    T

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    More Difficult Example

    Step 3: Note labels on interior nodes

    Logic Diagram for Analysis Example

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    More Difficult Example: Truth

    Table Remember to determine

    intermediate variables starting from

    the inputs.

    When all inputs determined for a

    gate, determine output.

    The truth table can be reduced

    using K-maps.

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    More Difficult Example: Truth

    Table

    A00001111

    B00110011

    C01010101

    F200010111

    F21

    1101000

    T10

    1111111

    T20

    0000001

    T30

    1101000

    F10

    1101001

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    Summary

    Important to be able to convertcircuits into truth table and

    equation formWHY? ---- leads to minimized

    sum of productrepresentation

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    Summary

    Two approaches illustrated Approach 1: Create an

    equation with circuit output

    dependent on circuit inputs

    Approach 2: Create a truth

    table which showsrelationship between circuit

    inputs and circuit outputs

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    Summary

    Both results can then be

    minimized using K-maps. Next time: develop a minimized

    SOP representation from a highlevel description