Digital Circuits Design Chin-Sung Lin Eleanor Roosevelt High School.

Digital Circuits Design

Chin-Sung Lin

Eleanor Roosevelt High School

Digital Circuits Design

• From Logic Gates to Boolean Functions

• From Boolean Functions to Truth Tables

• From Truth Tables to Logic Gates (Sum-of-Products)

• Logic Circuits Simulation

• Properties of AND and OR Gates

• Properties of NAND and NOR Gates

• Digital Logic Circuits Implementation

• Digital Building Blocks

From Logic Gates to Boolean Functions


A + BOR


Y = C (A + B)

A + B

AND

OR


A BAND


Y = C + A B

A B

OR

AND


A BAND


A BAND

AND

C D


Y = A B + C D

A B

OR

AND

AND

C D


Y = A B + C D

A B

OR

AND

AND

C D

B

C


Y = A B C + A B C + B C D

A B C

ORAND

AND

B

C

AND

A B C

B C D

From Boolean Functions to Truth Tables


Y = C + A B

A B

OR

AND


Y = C + A B

A B

OR

AND

A B C Y


Y = C + A B

A B

OR

AND

A B C Y

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1


Y = C + A B

A B

OR

AND

A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1


Y = A B + C D


Y = A B + C DA B C D Y

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

A B

OR

AND

AND

C D



0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

A B

OR

AND

AND

C D


Y = A B + A B A B Y

0 0

0 1

1 0

1 1


Y = A B + A B A B Y

0 0 0

0 1 1

1 0 1

1 1 0


Y = A B C + A B C A B C Y

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1



0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 0



0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1


A B C Y

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

Y = A B C + A B C

From Truth Tables to Logic Gates

From Truth Tables to Logic Gates(Sum of Products)

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

Y = A B + A B

Product Product

Sum of Products (SOP)


A B C D Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1



0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

A B

OR

AND

AND

C D


A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Y = A B C + A B C + A B C + A B C + A B C


A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Y = C + A B


Y = A B C + A B C + A B C + A B C + A B C + A B C

Y = (A B C + A B C) + (A B C + A B C) + (A B C + A B C)

Y = A C (B + B) + A B (C + C) + A C (B + B)

Y = A C + A B + A C

Y = A C + A C + A B

Y = (A + A) C + A B

A B

OR

AND


A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1


A B

OR

AND

Y = C + A B

Logic SimplificationIs there a better way?

From Truth Tables to Logic Gates(Karnaugh Map, K-Map)

A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

0 1

00

01

11

10

AB C

K-Map

• Karnaugh Map (K-Map) is a graphical tool for simplifying Boolean functions

• Coordinates of each cell are the input variables, which are ordered in Gray code to ensure that only one variable changes between adjacent cells

• Each cell represents a row in the truth table• The number of cells is always a power of 2


A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

0 1

00

01

11

10

AB C

K-Map

• Load the cell values from the truth table


A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

0 1

00 0 1

01 0 1

11 1 1

10 0 1

AB C

K-Map

• Load the cell values from the truth table


A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

0 1

00 0 1

01 0 1

11 1 1

10 0 1

AB C

K-Map

• Load the cell values from the truth table• Group adjacent cells with 1’s into pairs, quad,

and octet (powers of 2)


A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

0 1

00 0 1

01 0 1

11 1 1

10 0 1

AB C

K-Map

• Load the cell values from the truth table• Group adjacent cells with 1’s into pairs, quad,

and octet (powers of 2)• A cell can be grouped more than once• All cells need to be grouped if possible• Group cells around the outer edge of the map• Find the sum of these groups


A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

0 1

00 0 1

01 0 1

11 1 1

10 0 1

AB C

K-Map


A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

0 1

00 0 1

01 0 1

11 1 1

10 0 1

AB C

Y = A B + C

A B

OR

AND

K-Map


A B C D Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

00 01 11 10

00

01

11

10

AB CD

K-Map


A B C D Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

00 01 11 10

00 0 0 1 0

01 0 0 1 0

11 1 1 1 1

10 0 0 1 0

AB CD

K-Map

Y = A B + C D

A B

OR

AND

ANDC D


A B C D Y

0 0 0 0 1

0 0 0 1 0

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 0

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1

00 01 11 10

00

01

11

10

AB CD

K-Map


A B C D Y

0 0 0 0 1

0 0 0 1 0

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 0

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1

00 01 11 10

00 1 0 0 1

01 0 1 1 0

11 0 1 1 0

10 0 0 0 0

AB CD

K-Map

Y = A B D + B D


A B C D Y

0 0 0 0 0

0 0 0 1 1

0 0 1 0 0

0 0 1 1 1

0 1 0 0 1

0 1 0 1 0

0 1 1 0 1

0 1 1 1 0

1 0 0 0 0

1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 0

1 1 1 0 1

1 1 1 1 1

AB CD

K-Map


A B C D Y

0 0 0 0 0

0 0 0 1 1

0 0 1 0 0

0 0 1 1 1

0 1 0 0 1

0 1 0 1 0

0 1 1 0 1

0 1 1 1 0

1 0 0 0 0

1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 0

1 1 1 0 1

1 1 1 1 1

00 01 11 10

00

01

11

10

AB CD

K-Map


A B C D Y

0 0 0 0 0

0 0 0 1 1

0 0 1 0 0

0 0 1 1 1

0 1 0 0 1

0 1 0 1 0

0 1 1 0 1

0 1 1 1 0

1 0 0 0 0

1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 0

1 1 1 0 1

1 1 1 1 1

00 01 11 10

00 0 1 1 0

01 1 0 0 1

11 1 0 1 1

10 0 1 1 1

AB CD

K-Map


A B C D Y

0 0 0 0 0

0 0 0 1 1

0 0 1 0 0

0 0 1 1 1

0 1 0 0 1

0 1 0 1 0

0 1 1 0 1

0 1 1 1 0

1 0 0 0 0

1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 0

1 1 1 0 1

1 1 1 1 1

00 01 11 10

00 0 1 1 0

01 1 0 0 1

11 1 0 1 1

10 0 1 1 1

AB CD

K-Map

Y = B D + B D + AC= (B ⊕ D) + AC

Properties of AND and OR Gates

Properties of AND Gates

Enable

X Y

0 X 0

1 X X

• Any zero input of AND gate will zero the output

• One of the inputs of AND gate can be used as Enable pin

• When Enable is ‘1’, Y = X• When Enable is ‘0’, Y = 0

Enable

X Y

0 0 0

0 1 0

1 0 0

1 1 1

Properties of AND Gates

Select A B Y

0 A B B

1 A B A

• 2-to-1 Multiplexer• Select pin used to enable one of

the AND gates• When Select is ‘1’, Y = A• When Select is ‘0’, Y = B

Select A B Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

Properties of OR Gates

Disable X Y

0 X X

1 X 1

• Any ‘1’ input of OR gate will make the output equal to ‘1”

• One of the inputs of OR gate can be used as Disable pin

• When Disable is ‘1’, Y = 1• When Disable is ‘0’, Y = X

Disable X Y

0 0 0

0 1 1

1 0 1

1 1 1

Properties of NAND and NOR Gates

Properties of NAND and NOR Gates

• Any Boolean function can be implemented by a

combination of AND, OR, or NOT functions.

• Any Boolean function can be implemented using only

NAND gates.


NOR gates.

Universal Property of NAND Gates


NAND gates.

OR

NOT

AND

De Morgan’s laws

NAND: x · y = x + y

Universal Property of NOR Gates


NOR gates.

OR

NOT

AND De Morgan’s laws

NOR: x + y = x · y

Digital Logic Circuits Implementation

Half-Adder Example• Select• A• B• Y• 0• 0• 0• 0• 0• 0• 1• 1• 0• 1• 0• 0• 0• 1• 1• 1• 1• 0• 0• 0• 1• 0• 1• 0• 1• 1• 0• 1• 1• 1• 1• 1

A B C S

0 0

0 1

1 0

1 1


A B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0


A B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

S = ~AB + A~B = A ⊕ B

C = AB

Logic Circuits Simulation

Digital Building Blocks

Digital Building Blocks• Select• A• B• Y• 0• 0• 0• 0• 0• 0• 1• 1• 0• 1• 0• 0• 0• 1• 1• 1• 1• 0• 0• 0• 1• 0• 1• 0• 1• 1• 0• 1• 1• 1• 1• 1

Arithmetic Logic Unit (ALU)• Select• A• B• Y• 0• 0• 0• 0• 0• 0• 1• 1• 0• 1• 0• 0• 0• 1• 1• 1• 1• 0• 0• 0• 1• 0• 1• 0• 1• 1• 0• 1• 1• 1• 1• 1

OPCODE

Operands

Instruction Format• Select• A• B• Y• 0• 0• 0• 0• 0• 0• 1• 1• 0• 1• 0• 0• 0• 1• 1• 1• 1• 0• 0• 0• 1• 0• 1• 0• 1• 1• 0• 1• 1• 1• 1• 1

Central Processing Unit (CPU)• Select• A• B• Y• 0• 0• 0• 0• 0• 0• 1• 1• 0• 1• 0• 0• 0• 1• 1• 1• 1• 0• 0• 0• 1• 0• 1• 0• 1• 1• 0• 1• 1• 1• 1• 1

Central Processing Unit (CPU)• Select• A• B• Y• 0• 0• 0• 0• 0• 0• 1• 1• 0• 1• 0• 0• 0• 1• 1• 1• 1• 0• 0• 0• 1• 0• 1• 0• 1• 1• 0• 1• 1• 1• 1• 1

OPCODE

Operands

Program

Computational Thinking

through Digital Hardware

Reflections on Lessons

Reflections on Lessons

• Binary number system has been adopted as the machine

language (it can do everything the decimal system did).

• Digitization & quantization methods can convert all the real-

world information into binary data.

• Digital computer hardware are made of millions/billions of

switches (which have only two states: 1 & 0).

• Logic gates (which are made of switches) form the basic

building blocks of digital logic circuits.

• Logic circuits can perform arithmetic, logic, and data flow

control functions on binary data.

• Building a “thinking machine” purely in hardware.

Digital Circuits Design Chin-Sung Lin Eleanor Roosevelt High School.

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