DIGITAL 2 : EKT 221 RTL : Microoperations on a Single Register.
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Transcript of DIGITAL 2 : EKT 221 RTL : Microoperations on a Single Register.
DIGITAL 2 : EKT 221DIGITAL 2 : EKT 221RTL : Microoperations on RTL : Microoperations on
a Single Registera Single Register
Today’s OutlineToday’s OutlineMultiplexer-based transfersTransforming Block Diagram to
Detailed LogicShift Registers
◦Shift Registers with Parallel Loads◦Shift Registers with Parallel Loads and
Hold
MULTIPLEXER-BASED MULTIPLEXER-BASED TRANSFERTRANSFER
Microoperations on a Single Microoperations on a Single RegisterRegisterImplement one or more microoperations
with a single register as the destination of all primary results.
The single register may also serve as a source of an operand for binary and unary operations.
A simple technique using multiplexers for selection is introduced to allow multiple microoperations on a single register
Multiplexer-Based TransfersMultiplexer-Based Transfers
A register receives data transfers from more than 1 sources.
A dedicated multiplexer is used to select the wanted input
Example shows:◦If K1=1, R0 receives
data from R1.◦If K1=0, R0 receives
data from R2.
R2
R1
R0
K2
K1
01
S
2:1 MUX
n=4
n=4
n=4
Multiplexer-Based Multiplexer-Based TransfersTransfers
How do we represent this in RTL form?Written in if-then-else:
If (K1=1) then (R0 R1), else if (K2=1) then (R0 R2).
Written in RTL:R2
R1
R0
K2
K1
01
S
2:1 MUX
n=4
n=4
n=4
1. Hardware connections from two source registers, R1 and R2, to one common destination register, R0.
2. Selection between R1 and R2 must be based on the control variables K1 and K2.
Multiplexer-Based Multiplexer-Based TransfersTransfers
K1 K2 LoadR0
content
0 0 0 n.c
0 1 1 R2
1 0 1 R1
1 1 1 R1
Analyse the diagram for input:
*n.c : no change
R2
R1
R0
K2
K1
01
S
2:1 MUX
n=4
n=4
n=4
1OR2
R2
R1
R0
K2
K1
01
S
2:1 MUX
n=4
n=4
n=4
1
O R 2
Load
Block Diagram
1
O R 2
Q0Q1Q2Q3
D0D1D2D3
Load
Q0Q1Q2Q3
D0D1D2D3
Load2 to 1 MUX
Y0Y1Y2Y3
A0A1A2A3
B0B1B2B3
Q0Q1Q2Q3
D0D1D2D3
Load
S
CLK
K2K1
R1
R0
R2
Detailed Logic
Transforming a Transforming a Block Diagram into Block Diagram into Detailed LogicDetailed Logic
SHIFT REGISTERSSHIFT REGISTERS
Shift RegistersShift Registers
Shift Registers move data laterally within the register toward its MSB or LSB position
In the simplest case, the shift register is simply a set of D flip-flops connected in a row like this:
*CP: a common clock pulse input that activates the shift
Shift RegistersShift Registers
Data input, In, is called a serial input or the shift right input.
Data output, Out, is often called the serial output.The vector (A, B, C, Out) is called the parallel
output.
Serial Input Serial Output
Parallel Output
Shift RegistersShift Registers
CP In A B C Out
T0 0 ? ? ? ?
T1 1 0 ? ? ?
T2 1 1 0 ? ?
T3 0 1 1 0 ?
T4 1
T5 1
T6 1
T0 is the register state just before the first clock pulse occurs
T1 is after the first pulse and before the second.
Initially unknown states are denoted by “?”
Complete the last three rows of the table
Shift Registers with Shift Registers with Parallel LoadParallel LoadThe shift register shown earlier
has no control input, thus data is always shifted on clock pulse.
How to make the shift registers more controllable?E.g. shifts only on select positive
clock edges.Shift operation can be controlled
through D inputs of the FFs, rather than through the clock inputs CP.
Shift Registers with Shift Registers with Parallel LoadParallel Load
By adding a mux between each shift register stage, data can be shifted or loaded
If SHIFT is LOW, A and B are replaced by the data on DA and DB lines, else data shifts right on each clock.
SHIFT
IN
Dn A0
A1
Selector
2 to 1 MUXSerial Input
Shift Registers with Parallel Shift Registers with Parallel Loads and HoldLoads and Hold
But what if we want to hold to the current data, meaning no shift or no loading of new data?
The design must have 2 controls:
1.For the SHIFT2.For the LOAD
SHIFT LOAD OPERATION
0 0 No Change
0 1 Load Parallel Data
1 X Shift down from Q0 to Q3
We use an AND gate to disabled the Load input, so we mark with don’t care condition
Function Table for the Register of Fig 7-10
4-bit SHIFT REGISTER WITH PARALLEL LOAD AND HOLD OPERATIONIn Register Transfer Language:
Shift : Q sl Q, Shift Load : Q D
Figure 7-10M. Morris ManoLOGIC AND COMPUTER DESIGN FUNDAMENTALS
Control inputs AND gates:
1. Enables the Shift operation2. Enables the input data3. Restores the contents of
reg. when no operation
1
2
3
1
2
3
1
2
3
1
2
3
Shift Registers Shift Registers with with Parallel Loads Parallel Loads and and HoldHold S = 0, L = 0 :
◦ AND3 in each stage is enabled
◦ The output of each FF is applied to its own D input.
◦ A +ve transition of CLK restores the contents of reg.
◦ Output Qi is unchanged
1
2
3
Shift Registers Shift Registers with with Parallel Loads Parallel Loads and and HoldHold
S = 0, L = 1 : ◦ AND2 in each stage is
enabled◦ The input Di is applied
to D input of corresponding FF.
◦ Next +ve transition of CLK transfers the parallel input data into reg.
◦ Output Qi = Di
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2
3
Shift Registers Shift Registers with with Parallel Loads Parallel Loads and and HoldHold
S = 1 : ◦ AND1 in each stage is
enabled
When +ve edge occurs on CLK:
◦ Data from serial input SI to be transferred to FF Q0,
◦ Output Q0 to be transferred to FF Q1,
…and so on down the line.
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2
3
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