DEVELOPMENT OF FRONT-END ELECTRONICS FOR ONLINE … · 2019-05-08 · • Cylindrical Drift Chamber...

DEVELOPMENT OF FRONT-END ELECTRONICS FOR ONLINE TRIGGER

SYSTEM OF COMET PHASE-I Master defense presentation

CHAU THANH TAI12-02-2019

Master Defense Presentation 2019 @ Osaka Univ. Chau Thanh Tai1

Ø Introduction§ COMET Phase-I

§ CyDet Trigger system of COMET Phase-I

Ø Development§ Firmware of front-end electronics

§ Communication

Ø Results and conclusion

OUTLINE

Master Defense Presentation 2019 @ Osaka Univ Chau Thanh Tai2

COMET PHASE-I EXPERIMENTCOMET (COherent Muon to Electron Transition) Phase-I

• Measuring the neutrinoless, coherent transition of a muon to an electron. ( )

Standard Model : O(10-54) • Branching ratio

New model : O(10-15) (can be achieved by COMET Phase-I)

AleAlμ �o� ��

3

CYLINDRICAL DETECTOR SYSTEM (CyDet) • Cylindrical Drift Chamber (CDC)→ Reconstructing tracks of electrons from conversion.• CyDet Trigger Hodoscope (CTH)→ First level trigger signal for CyDet trigger system.

CDC

CTHMaster Defense Presentation 2019 @ Osaka Univ Chau Thanh Tai3

MeV/c105E e

• CyDet trigger system→ Trigger rate from CTH is too high , about 1 MHz order.→ Developed to reduce trigger rate to manageable level for stable data acquisition.

CYDET TRIGGER SYSTEM


CentralTriggerSystem

Other trigger systems

COTTRI MB

COMET TRIgger systems(COTTRI system)

COTTRI FE CDC

COTTRI FE CTH

RECBE(Frontend) CDC

FE CTH

1st level trigger

final trigger

DAQ

2nd leveltrigger

COTTRI MB

• The communication plays an important role in CyDet trigger system.• To evaluate the error rate of communication, ECC is developed in RECBE's firmware.• It can detect errors and correct single bit error during data transmision.(ECC : Error Correction Code)

• Evaluating items to confirm the reliability of communication.→ Confirming the performance of ECC in detecting and correcting errors.→ Latency of communication protocol and modified RECBE's firmware→ Stability of communication→ Error rate and data loss during data transmission.

REQUIREMENTS FOR COMMUNICATION


FRONT-END ELECTRONICS• Readout: RECBEs - Developed by Bella-II CDC group.


CDC

ASD

ADC

• Digitizing analog signals• Sending digital sigals to FPGA

FPGA

Connecting to PC• Taking data for DAQ• Changing parameters in FPGA

SFP

• Generating trigger data• Sending this data to COTTRI FE

48 channels

FIRMWARE DEVELOPMENT• Diagram of modified RECBE's firmware


Arranging data receiving fromADC chips

Generating trigger data

Create data format and send to COTTRI FE

ADC data - 48 channels(Charge information) RING

BUFFER

PROTOCOL COMMUNICATION

ADC data

TDCMODULE

ADCI/F

Digital signals from ASD

(Time information)

DATAGENERATION

COTTRI FEBOAD

RECBE's FPGA

TDC data

TDC hit

...

• TDC hit → RECBE records electric signal from charged particles.

GENERATING TRIGGER DATA • Data generation module• Basic idea of this modules illustrated by this figure

• How to distinguish sum of charged information and sum of baseline in FPGA ?→ TDC hit signal is used to in this case.Master Defense Presentation 2019 @ Osaka Univ Chau Thanh Tai8

• Data generation module• Upper and lower thresholds are used to suppress data size of sum 3 ADC samples.→ Their values can be adjusted through SFP

• Obtain 2 bits/channel so total data size is 96 bits/board.• The time range between two 2-bit data is 100 ns.

Master Defense Presentation 2019 @ Osaka Univ Chau Thanh Tai

Upper Threshold

Lower Threshold

3

2

1.... 0 0 .....

9

GENERATING TRIGGER DATA

• Communication protocol moduleCOMMUNICATION PROTCOL & ECC


• Diagram of communication protocol module:

10

96-bit data

1 2 3

Communication protocol module

Data format

Communication protocol

ECC (encoder)

DataGeneration

Module

RECBE

• ECC module is developed for COMET Phase-I to detect errors during data transmission.• ECC (based on Hamming Code) includes ECC encoder and ECC decoder→ ECC encoder generates 6 parity bits based on every 24-bit data. ( at transceiver) → ECC decoder uses 6 parity bits to detect errors and correcting single bit errors ( at receiver)

COTTRIFE

• Error Correction Code (ECC)

24-bit data

• Data formatDATA FORMAT AND AURORA PROTOCOL


• Format of trigger data

• Aurora 8b/10b is chosen as communication protocol.• Packaging one header and four data into one frame.• Sending this frame from RECBE to COTTRI

Maximum data rate of protocol is 3.84 Gbps

• Communication protocol

→ Sent Number - a number of new data is sent from RECBE to COTTRI FE→ Board ID - which RECBE board sent new data to COTTRI FE

11

• COMET TRIgger (COTTRI) system → COTTRI front-end (FE) and COTTRI motherboard (MB)

COTTRI PROTOTYPE

FPGA

Si5326

Display port

Year-end Workshop Presentation 2018 @ Osaka Univ. Chau Thanh Tai12

Receiving dataTransmitting data

MMCX portReceive 40 MHz clock

Si5326 chipGenerating 120 MHz

SET UP OF TESTING COMMUNICATION• Diagram of setup for testing


Si5326 Si5326

Aurora

FCTInterface FCT

FPGA

Aurora

FPGA

FunctionGenerator

RJ45Aurora

40 MHz

40 MHz

RECBE

120 MHz

120 MHz

120 MHz

Clock source

40 MHz

• Fast control and Timing (FCT) is used to generate and send clock signals to other boards.• Parameters of Aurora 8b/10b protocol of COTTRI FE and MB is same as that of RECBE• Pseudo data is sent RECBE → COTTRI FE → COTTRI MB.• 5 m DisplayPort cable is used in COMET Phase-I

5.0 m5.0 m

COTTRI FE COTTRI MB

• Performance of ECC decoder at COTTRI• Injecting errors to pseudo data generated at RECBE before sending it to COTTRI FE

• Receiving data before and after being checked by ECC decoder

• ECC decoder can detect single and double bits error.

• Single bit error is corrected after going out ECC decoder.

RESULT FOR LATENCYRESULTS


Errors injected

ScreenshotDebugging Software

• Latency from each contribution

• Stability of connection, error rates and lost data• The test is run during 2 days with pseudo data generated in RECBE.

RESULT FOR LATENCYRESULTS


Contribution Value (ns)Generating trigger data from CDC hit information 100Formatting data to send RECBE → COTTRI FE 125

ECC decoder for checking and repairing in COTTRI FE 50ECC decoder for checking and repairing in COTTRI MB 50

Data transmission RECBE → COTTRI MB 692.5Latency from new firmware and communication 1018

COTTRI FE COTTRI MB

Cable Length 5 m 5 mConnection Loss 0 0Errors of Aurora 0 0Errors of ECC 0 0

Data Loss 0 0

• Total receiving bits - 2.77×1014 bits• Error ~ 1 error

3.16×10-15 errors/bit

CONCLUSION• ECC decoder can detect errors in receiving data.• ECC decoder can correct single bits errors as expected.

ECC module can detect and correct errors successfully.

• The latency for transmitting data RECBE → COTTRI MB is ~ 1.018 µs. → The allowed latency for Ring Buffer of RECBE to wait for trigger signal is ~ 5 µs. → The latency RECBE → COTTRI MB takes 20.4% of allowed latency (small enough).

The latency of new firmware and communication is small for CyDet trigger system.

• The stability of communication among boards is confirmed during 2 days.

• Because of data rate being 1.6×109 bits/s, the number of errors of communication is about 0.497 error/day (less than 1 error).

The number of error per day of communication is also small for CyDet trigger system.

New firmware and communication can be applied to CyDet trigger system.16

RESULT FOR LATENCYCONCLUSION


DEVELOPMENT OF FRONT-END ELECTRONICS FOR ONLINE … · 2019-05-08 · • Cylindrical Drift Chamber...

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