Design Tradeoffs For Hard and Soft FPGA-based Networks-on-Chip

Design Tradeoffs For Hard and Soft FPGA-based Networks-on-Chip

Mohamed ABDELFATTAHVaughn BETZ

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Outline

Why NoCs on FPGAs?

Hard/soft efficiency gap

Integrating hard NoCs with FPGA

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OutlineWhy NoCs on FPGAs?



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Motivation Previous Work

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Interconnect

Motivation1. Why NoCs on FPGAs?

Logic Blocks

Switch Blocks

Wires

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Logic Blocks

Switch Blocks

Wires

Hard Blocks:• Memory• Multiplier• Processor

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Logic Blocks

Switch Blocks

Wires

Hard InterfacesDDR/PCIe ..

Interconnect still the same

Hard Blocks:• Memory• Multiplier• Processor

1600 MHz

200 MHz

800 MHz

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MotivationDDR3 PHY and Controller1. Bandwidth requirements for

hard logic/interfaces2. Timing closure

1. Why NoCs on FPGAs?PCIe Controller

Gigabit Ethernet

1600 MHz

200 MHz

800 MHz

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hard logic/interfaces2. Timing closure3. High interconnect utilization:

– Huge CAD Problem– Slow compilation– Power/area utilization


Gigabit Ethernet

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4. Wire speed not scaling:– Delay is interconnect-dominated


Gigabit Ethernet

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5. Low-level interconnect hinders modularity:– Parallel compilation– Partial reconfiguration– Multi-chip interconnect


Gigabit Ethernet

Barcelona Los Angeles

Keep the “roads”, but add “freeways”.

Hard Blocks

Logic Cluster

Source: Google Earth

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DDR3 PHY and Controller


Gigabit Ethernet

1. Bandwidth requirements for hard logic/interfaces

2. Timing closure3. High interconnect utilization:




FPGA with NoCNoC

Routers

Links Router forwards data packet

Router moves data to local interconnect

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Gigabit Ethernet






FPGA with NoC

Pre-design NoC to requirements NoC links are “re-usable” Latency-tolerant communication NoC abstraction favors modularity

High bandwidth endpoints known

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Gigabit Ethernet






FPGA with NoC

Latency-tolerant communication NoC abstraction favors modularity

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Gigabit Ethernet

Implementation options: Soft Logic (LUTs, .. ) Hard Logic (unchangeable)

Mixed Soft/Hard

Hard vs. Soft

Soft NoC Hard NoC• Build as needed out of LUTs • Must build the whole thing

• Tailor to application • Must be general enough for any aiapplication

• Slower, bigger • Faster, smaller

Investigate the hard vs. soft tradeoff for NoCs (area/delay)

Configurability Efficiency

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Previous Work FPGA-tuned Soft NoCs:

– LiPar (2005), NoCeM (2008), Connect (2012) Hard NoCs:

– Francis and Moore (2008): Exploring Hard and Soft Networks-on-Chip for FPGAs

Applications that leverage NoCs:– Chung et al. (2011): CoRAM: An In-Fabric Memory Architecture

for FPGA-based ComputingOur Contributions:

1. Quantify area/performance gap of hard and soft NoCs2. Investigate how this impacts NoC design (hard/soft)3. Integrate hard NoC with FPGA fabric

1. Why NoCs on FPGAs?

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NoC Architecture

Methodology Soft NoC design

Results

Area/Speed Efficiency Gap

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Router Microarchitecture NoC = Routers + Links

2. Hard/Soft Efficiency

State-of-the-art router architecture from Stanford:1. Acknowledge that the NoC community have excelled at

building a router: We just use it2. To meet FPGA bandwidth requirements:

High-performance router3. A complex router includes a superset of NoC

components that may be used: More complete analysis

Split router into 5 Components

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Router – 5 Components2. Hard/Soft Efficiency

Input Modules Output Modules

Virtual Channel (VC) Allocator

Switch Allocator

Crossbar Switch

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5

1

5

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Switch Allocator

Crossbar Switch

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5

1

5

Multi-Queue Buffer

• Port Width• Buffer depth• Number of VCs

= Memory + CIControl Logic

Input Modules

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Switch Allocator

Crossbar Switch

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5

1

5

Multiplexers

Logic + crowded interconnect

• Port Width• Number of Ports

Crossbar

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Switch Allocator

Crossbar Switch

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1

5

Retiming Register

Registers + little control logic

• Port Width• Number of VCs

Output Modules

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Switch Allocator

Crossbar Switch

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Arbiters

= Logic + Registers

• Number of Ports• Number of VCs

Allocators

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Design Space2. Hard/Soft Efficiency

5 Components



Switch Allocator

Crossbar Switch

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1

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Input Module

Crossbar

VC Allocator

SW Allocator

Output Module

Port Width

Number of Ports

Number of VCs

Buffer Depth

4 Parameters

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Methodology Post-routing FPGA (soft) area and delay Post-synthesis ASIC (hard) area and delay Both TSMC 65 nm technology (Stratix III) Verify results against previous FPGA:ASIC

comparison by Kuon and Rose


Per Router Component

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3 Options for Buffer on FPGA Relatively small memories Critical component in router design 3 options for FPGA:

Registers

LUTRAM

Block RAM

One per LUT

640 bits

9 Kbits


Area of each implementation option

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Width = 32 Bits


Another logic cluster used

3 Options for Buffer on FPGA

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3 Options for Buffer on FPGA Relatively small memories 3 options for implementation on FPGA

Registers

LUTRAM

Block RAM

One per LUT

640 bits

9 Kbits

0.77 Kbit/mm2

23 Kbit/mm2

142 Kbit/mm2

16% utilized BRAM more area efficient than fully used LUTRAM (Valid for Stratix III)

LUTRAM could win for some points in other FPGAs

Use BRAM for FPGA (soft) implementationSoft


29 High port count inefficient in softSoft

24X – 94X

60X – 170X


Results – High Port Count

30 High port count inefficient in soft Width scales betterSoft


Results – Width

26X – 17X

72X

31 Buffer depth is free on FPGAs when using BRAMSoft

Filling up the BRAM

Results – Deep Buffers2. Hard/Soft Efficiency

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Soft Router Design Design recommendations based on FPGA silicon area Supported by delay measurements

Buffer depth is free on FPGAs when using BRAMSoft

High port count inefficient in soft Width scales betterSoft

Use BRAM for FPGA (soft) implementationSoft


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Results – Area

Memory

= Logic + Registers


Router Component Mean Area Ratio LUT:REGInput Module 17 --Crossbar 85 --VC Allocator 48 8:1Switch Allocator 56 20:1Output Module 39 0.6:1Router 30

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Results – Delay


Router Component Mean Delay RatioInput Module 2.9Crossbar 4.4VC Allocator 3.9Switch Allocator 3.3Output Module 3.4Router 3.6

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Hard NoC + FPGA Wiring

Conclusion Future Work

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What to harden?Router Component Area Ratio Delay RatioInput Module 17 2.9Crossbar 85 4.4VC Allocator 48 3.9Switch Allocator 56 3.3Output Module 39 3.4Router 30 3.6

Router Component Area Ratio Delay RatioInput Module 17 2.9Crossbar 85 4.4VC Allocator 48 3.9SW Allocator 56 3.3Output Module 39 3.4Router 30 3.6

50% Total Area Critical

Path

Results suggest hardening Crossbar and Allocators Mixed hard/soft implementation

40%

10%

3. Hard NoC with FPGA

37Input Modules Output Modules


Switch Allocator

Crossbar Switch

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5

1

5

Mixed Implementation



Switch Allocator

Crossbar Switch

1

5

1

5



Switch Allocator

Crossbar Switch

1

5

1

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Soft Hard MixedArea 4.1 mm2 (1X) 0.14 mm2 (30X) 2.3 mm2 (1.8X)

Speed 150 MHz (1X) 810 MHz (5X) 390 MHz (2.5X)

? ?

How to connect hard and soft?

How efficient is mixed/hard after doing that?

Soft

Hard

Mixed not worth hardening

For a typical router ..• 5 ports• 32 bits wide• 2 VCs• 10 buffer words


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Integrating a Hard Router3. Hard NoC with FPGA

Router Logic

Programmable Interconnect

Router

• Same I/O mux structure as a logic block – 9X the area• Conventional FPGA interconnect between routers

Logic clusters

RouterLogic

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Router Logic


FPGA

Router


• Same I/O mux structure as a logic block – 9X the area• Conventional FPGA interconnect between routers

730 MHz

19th of FPGA vertically ( 2.5mm)

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Router Logic


Router


Assumed a mesh Can form any topology

FPGA

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Soft Hard Hard (+ interconnect)Area 4.1 mm2 (1X) 0.14 mm2 (30X) 0.18 mm2 = 9 LABs (22X)

Speed 150 MHz (1X) 810 MHz (5X) 730 MHz (4.7X)

64-node NoC on Stratix V

Integrating a Hard Router

Router Logic


Router

Soft Hard (+ interconnect)

Area~12,500

LABs576 LABs

%LABs 33 % 1.6 %

%FPGA 12 % 0.6 %


Hard NoC + Soft Interconnect is very compelling

Provides 47 GB/s peak bisection bandwidth

Very Cheap! Less than cost of 3 soft nodes

Why NoCs on FPGAs?



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• Big city needs freeways to handle traffic• Solve communication problems for a large/heterogeneous FPGA:

• Timing Closure – Interconnect Scaling – Modular Design

• A hard NoC is on average 30X smaller and 3.6X faster than soft• Crossbars and allocators worst – Input buffer best

• An efficient soft NoC:• Uses BRAMs – Large width, low Port Count – Deep buffers

• Mixed implementation does not make sense• Integrated fully hard NoC with FPGA fabric (for NoC Links)

• 22X area improvement over soft• Reaches max. FPGA frequency (4.7X faster than soft)• 64-node NoC = 0.6% of total FPGA area (Stratix V)

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Future Work Power analysis More hardening:

– Dedicated inter-router links (hard wires)– Clock domain crossing hardware

How do traffic hotspots (DDR/PCIe) influence NoC design?

Latency insensitive design methodology that uses NoC CAD tool changes for a NoC-based FPGA


Thank You!

[email protected]

Design Tradeoffs For Hard and Soft FPGA-based Networks-on-Chip

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