Design of an Integrated FractionalFrequency Divider Circuit

Tze Hin Cheung

School of Electrical Engineering

Thesis submitted for examination for the degree of Master ofScience in Technology.Espoo 25.7.2019

Supervisor

Prof. Jussi Ryynänen

Advisors

M.Sc. (Tech.) Mikko Martelius

D.Sc. (Tech.) Kari Stadius

Copyright © 2019 Tze Hin Cheung

Aalto University, P.O. BOX 11000, 00076 AALTOwww.aalto.fi

Abstract of the master’s thesis

Author Tze Hin CheungTitle Design of an Integrated Fractional Frequency Divider CircuitDegree programme Electronics and NanotechnologyMajor Micro- and Nanoelectronic Circuit Design Code of major ELEC3036Supervisor Prof. Jussi RyynänenAdvisors M.Sc. (Tech.) Mikko Martelius, D.Sc. (Tech.) Kari StadiusDate 25.7.2019 Number of pages 72 Language EnglishAbstractModern mobile devices employ an increasing number of radio standards which resultsin the devices having to be capable of supporting multiple frequency bands. Themulti-band support introduces design challenges to frequency synthesizers as therange of frequencies increases.

The performance and range of frequencies that an existing frequency synthesizersupports can be improved by introducing frequency dividers. The flexibility providedby frequency dividers comes from the programmability of division ratios and especiallyfrom fractional division ratios. With the use of fractional division ratios, a widerfrequency range and an improved frequency resolution can be achieved for an existingfrequency synthesizer.

In this thesis, the task was to design a standalone fractional frequency divider(FFD) operating between input frequencies of 6–16 GHz down to output frequencies of3–4 GHz. The FFD has a division ratio range of 2–3 with an 8-bit fractional divisionratio resolution. The design is based on the generation of a time-average fractionalfrequency signal using a multi-modulus counter-based integer divider (MMD) anda Sigma-Delta modulator based digital control circuit. The time-average signal isafterwards processed by a phase interpolator (PI) which generates a proper fractionalfrequency signal that has good instantaneous phase. The FFD is designed in 28 nmCMOS and occupies an area of 0.17 mm2. The power consumption is 103.5 mW,when producing an output signal with a frequency of 4 GHz. The resulting outputhas a peak-to-peak period jitter of less than 6 ps. The designed FFD has a frequencyraster of less than 7.8 MHz within the 3–4 GHz output range.Keywords Frequency synthesis, Open-loop Fractional Frequency Divider, Frequency

Divider, Phase Interpolator, Multi-Modulus Integer Divider,Instantaneous Phase, Sigma-Delta Modulator

Aalto-yliopisto, PL 11000, 00076 AALTOwww.aalto.fi

Diplomityön tiivistelmä

Tekijä Tze Hin CheungTyön nimi Integroidun murtolukutaajuusjakajapiirin suunnitteluKoulutusohjelma Elektroniikka ja nanotekniikkaPääaine Mikro- ja nanoelektroniikkasuunnittelu Pääaineen koodi ELEC3036Työn valvoja Prof. Jussi RyynänenTyön ohjaaja DI Mikko Martelius, TkT Kari StadiusPäivämäärä 25.7.2019 Sivumäärä 72 Kieli EnglantiTiivistelmäNykyaikaiset mobiililaitteet käyttävät hyväkseen yhä useampia radiostandardeja,mikä on johtanut yhä useamman taajuuskaistan tukemiseen yksittäisissä laitteis-sa. Usean taajuuskaistan tukeminen on luonnollisesti johtanut tilanteeseen, jossataajuussyntetisaattorien kehittäminen on tullut haastavammaksi.

Yksi tapa laajentaa taajuussyntetisaattorien ulostulon taajuusaluetta on käyt-tää taajuusjakajia. Taajuusjakajien tehtävänä on käytännössä tuottaa signaaleita,joiden taajuudet ovat johdannaisia taajuussyntetisaatorin tuottamista taajuuksista.Taajuussyntetisaattorin tuottaman signaalin taajuus suhteessa jakajan tuottamaantaajuuteen kutsutaan jakajan jakosuhteeksi. Useimmissa tapauksissa jakosuhde onkokonaisluku, mutta jakajan tuomaa joustavuutta voidaan lisätä käyttämällä murto-lukujakosuhteita.

Tajuusjakajia voidaan suunnitella eri tavoilla, joista integroiduissa piireissä suosi-tuimpiin kuuluu laskureihin pohjautuvat jakajat. Laskureihin pohjautuvat taajuusja-kajat kykenevät jakamaan ainoastaan kokonaisluvuilla, mikä johtaa siihen, että niitäei voida suoraan käyttää murtolukutaajuusjakajina. Käytännössä murtolukujakosuh-de voidaan kuitenkin saavuttaa likiarvoistamalla murtolukua kokonaisluvuilla.

Likiarvoistaminen voidaan toteuttaa piiritasolla sigma-delta modulaattorien avul-la. Likiarvoistaminen tuottaa aina signaalin, joka sisältää virheitä. Käytännössänämä virheet näkyvät aika-tasossa vaihe-eroina. Vaihe-erojen poistaminen voidaantoteuttaa vaiheinterpolaattorilla.

Tässä työssä on suunniteltu murtolukujakaja, joka toimii 6–16 GHz taajuusalu-eella ja tuottaa ulostulossa 3–4 GHz signaalia. Suunniteltu murtolukujakaja kyneneejakamaan kahdesta kolmeen 8 bitin tarkkuudella. Jakajan toimintaperiaate perustuulikiarvoistamiseen sekä jälkeenpäin signaalin korjaamiseen vaiheinterpolaattorilla.Murtolukujakaja muodostuu laskuripohjaisesta kokonaislukujakajasta, sigma-deltamodulaattorista sekä vaiheinterpolaattorista. Piiri toteutettiin 28 nm CMOS teknolo-gialla ja sen pinta-ala on 0.17 mm2. Tehonkulutus on 103.5 mW, kun jakaja tuottaa4 GHz signaalia. Tuotetun signaalin aika-tason ajanjakson huojunta on alle 6 ps.Avainsanat Taajuussyntetisointi, murtolukutaajuusjakaja, taajuusjakaja,

vaiheinterpolaattori, sigma-delta modulaattori

v

PrefaceI would like to thank my supervisor Prof. Jussi Ryynänen for giving me the opportu-nity to work in the ECD group and encouraging me to work towards a goal. I wouldalso like to thank my advisors M.Sc. Mikko Martelius and D.Sc. Kari Stadius forguiding me in the writing process of this thesis. I want to especially thank Mikko forteaching me the basics of IC design tools and the simulation of complicated circuits.I would also like to thank my co-workers who have given me insightful views in tothe world of IC design and to the discussions regarding everyday life. Finally andmost importantly, I would like to sincerely express my gratitude towards my parentsfor supporting me and giving me the opportunity to strive for the goals that I haveset for myself.

Otaniemi, 25.7.2019

Tze Hin Cheung

vi

ContentsAbstract iii

Abstract (in Finnish) iv

Preface v

Contents vi

Symbols and Abbreviations viii

1 Introduction 1

2 Background 22.1 Frequency Up- and Down-Conversion . . . . . . . . . . . . . . . . . . 22.2 Frequency Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2.1 Direct Analog Frequency Synthesis . . . . . . . . . . . . . . . 42.2.2 Indirect Frequency Synthesis . . . . . . . . . . . . . . . . . . . 5

2.3 Frequency Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.3.1 Regenerative Frequency Dividers . . . . . . . . . . . . . . . . 82.3.2 Injection-Locked Frequency Dividers . . . . . . . . . . . . . . 92.3.3 Counter-Based Frequency Dividers . . . . . . . . . . . . . . . 10

3 Fractional Frequency Dividers 133.1 Defining Frequency for Fractional Dividers . . . . . . . . . . . . . . . 133.2 Direct Fractional Frequency Dividers . . . . . . . . . . . . . . . . . . 143.3 Multi-Modulus Based Fractional Frequency Divider . . . . . . . . . . 16

3.3.1 Multi-Modulus Frequency Divider . . . . . . . . . . . . . . . . 163.3.2 Fractional Division Ratios with the Use of Multi-Modulus

Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . 193.3.3 Phase-Offset Compensation . . . . . . . . . . . . . . . . . . . 21

4 Open-Loop Fractional Frequency Divider Design 244.1 Design Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.2 System Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.3 Design of Multi-modulus Integer Divider . . . . . . . . . . . . . . . . 26

4.3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274.3.2 Current-Mode Logic Latch . . . . . . . . . . . . . . . . . . . . 304.3.3 Current-Mode Logic XNOR . . . . . . . . . . . . . . . . . . . 334.3.4 Current-Mode Logic AND . . . . . . . . . . . . . . . . . . . . 34

4.4 Design of Sigma-Delta -modulator Based Control Circuitry . . . . . . 354.5 Design of Phase Interpolator . . . . . . . . . . . . . . . . . . . . . . . 37

4.5.1 Three Phase Generation . . . . . . . . . . . . . . . . . . . . . 384.5.2 Phase Interpolation Stage . . . . . . . . . . . . . . . . . . . . 394.5.3 Phase Interpolator Unit . . . . . . . . . . . . . . . . . . . . . 42

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5 Layout and Simulation of the Fractional Frequency Divider 475.1 Layout of the Designed Fractional Frequency Divider . . . . . . . . . 475.2 Simulation of Multi-Modulus Integer Divider . . . . . . . . . . . . . 525.3 Simulation of the Sigma-Delta Digital Control Circuit . . . . . . . . . 535.4 Simulation of Phase Interpolator . . . . . . . . . . . . . . . . . . . . . 555.5 Combined Fractional Frequency Divider System Simulation . . . . . . 625.6 Performance Summary of the Fractional Frequency Divider . . . . . . 66

6 Conclusion 69

References 70

viii

Symbols and AbbreviationsAbbreviations

5G Fifth Generation Wireless Telecommunications

BB Baseband

BW Bandwidth

DAC Digital-to-Analog Converter

DAFS Direct Analog Frequency Synthesis

DDFS Direct Digital Frequency Synthesis

DJ Deterministic Jitter

DNL Differential Nonlinearity

DTC Divide-by-Two Circuit

EM Electromagnetic

FFD Fractional Frequency Divider

FFT Fast-Fourier Transform

IC Integrated Circuit

IF Intermediate Frequency

ILFD Injection-locked Frequency Divider

INL Integral Nonlinearity

LO Local Oscillator

LPF Loop Filter

LPF Low-Pass Filter

MMD Multi-Modulus Divider

MSB Most Significant Bit

PI Phase Interpolator

RF Radio Frequency

SNR Signal-to-Noise Ratio

VCO Voltage Controlled Oscillator

1 IntroductionWireless communication systems have become ever more important for the modernsociety with variety of radio standards from Bluetooth, IEEE 802.11 Wi-Fi to LTEand 5G. With the ever increasing number of radio standards, modern mobile deviceshave to be designed to support multiple frequency bands.

With the growing number of radio standards, the design of multiband transceiversbecomes progressively more essential. For example in the new fifth generationwireless telecommunication (5G) radio standard includes within itself two frequencyranges that cover at least the ranges below 7.125 GHz and above 24.25 GHz [1, 2].With these two widely different scales of frequencies, the idea is to cover bothsmall and large physical distances with varying data rates. Such large difference infrequency introduces challenges in the frequency synthesizers for generating signalsthat cover the desired frequency range in a single device. In order to cover the range,improvements to the frequency synthesizers can be implemented with two differentapproaches. The approaches are to use more complex frequency synthesizer schemesor by employing frequency dividers as part of the frequency synthesizer chain. Thefrequency dividers would produce the desired frequencies from the existing signalsprovided by the frequency synthesizer.

Frequency dividers are circuits that are capable of producing frequencies that arefractions of the original frequency. Most frequency divider topologies can achieveinteger division ratios whereas more complex designs have to be used for achievingfractional division ratios. Roughly speaking the trade-off between an integer orfractional division ratio is the complexity of the design process versus achievablefrequency resolution.

In this thesis, the main objective is the design of a standalone fractional frequencydivider with proper instantaneous phase and good frequency resolution. A standalonedivider can be used with an existing frequency synthesizer design in order to improvethe frequency range and resolution. A layout of the divider is drawn and theperformance will be evaluated based on simulations.

The structure of the thesis consists of five sections besides this introduction.Section 2 is the background section which introduces the popular frequency synthesizertopologies and general information regarding different frequency dividers and howthey are currently used in frequency synthesizers. Section 3 is dedicated to fractionalfrequency dividers and the definition of fractional frequency. Section 4 consists of thedesign of a fractional frequency divider and covering of the main functionalities ofdifferent blocks forming it. Section 5 is the confirmation of performance and behaviorof the designed fractional frequency divider by using various circuit simulators.Section 6 is a summary regarding fractional frequency dividers and especially theone designed.

2

2 BackgroundFrequency synthesis is the generation of specific frequencies from a single or a group offrequency references. With the help of a reference frequency, a frequency synthesizercan flexibly and precisely generate desired frequencies for use in RF applications suchas mixing. The flexibility and precision of frequency synthesizers can be attributedto extensive theory behind different designs and to the use of frequency dividers.[3, 4]

Frequency dividers provide the possibility for additional output frequencies whenthey are used as parts of a frequency synthesizer. In other words, the number ofoutput frequencies can be increased by dividing one of the existing outputs of thesynthesizer with a specific division ratio. The output before and after the divider canbe used and thus the divider increases the number of feasible outputs and improvesthe flexibility of a frequency synthesis circuit. [4]

This section of the thesis consist of three distinct parts: frequency translationusing mixers, frequency synthesizers and dividers. Section 2.1 provides a briefintroduction to mixers and how they are used for frequency shifting. In Section 2.2,frequency synthesizers will be introduced with the help of two different techniques.In Section 2.3, a more detailed look at frequency dividers is provided with threedifferent architectures.

2.1 Frequency Up- and Down-ConversionIn a wireless system, information is usually encoded in relatively low frequency whichin itself is not suitable for transmission over air medium using feasibly sized antennas.In order to be able to use a smaller antenna for transmitting this low frequencyinformation, higher frequencies have to be used for carrying the information. Highfrequencies are used in wireless transmission because the size of the antenna isinversely proportional to the frequency that is used for carrying the information. [5]

A high frequency carrier signal can be provided for the low frequency informationin a process known as frequency translation. Frequency translation is used in twodifferent ways in RF transceivers. First, frequency translation can be used to shift theinformation containing signal to a higher frequency for wireless transmission. Second,extracting the low frequency information from the received high frequency signalis possible by removing the carrier with another frequency translation step. Thesespecific use cases of frequency translation are known as up- and down-conversiondepending on whether the desired output frequency is higher or lower than the signalthat is translated.

Frequency translation can be performed in a single or multiple stages and this isdependent on the used transceiver architecture. A transceiver using only a singletranslation stage is called a direct-conversion trasceiver whereas the alternative thatuses two or more translation stages are named superheterodyne-based architectures.A two-stage superheterodyne receiver is shown in Figure 1, and besides the antennathe receiver consists of amplifiers, filters and mixers. [5]

Mixers are nonlinear circuits that can perform up- and down-conversion in RF

3

RFLNA G

LO1 LO2

IF Stage

BasebandChain

Figure 1: Typical block diagram of heterodyne receiver, which includes amplifiers,bandpass filters, mixers and baseband processing. [6]

transceivers. Nonlinearity of mixers is the main reason why they are capable ofgenerating new frequencies from two existing sources. These new frequencies areformed by the multiplication of two or more sinusoidals signals that result in thesum and difference components. These sum and difference frequencies are theoutcomes that are responsible for the frequency translation process. The result of amultiplication of two cosinusoids is shown with the help of the following equations:

v1 = A1 · cos (ω1t + ϕ1) (1)v2 = A2 · cos (ω2t + ϕ2) (2)

vout = v1v2 = 12A1A2[cos ((ω1 − ω2)t + ϕ1 − ϕ2)

+ cos ((ω1 + ω2)t + ϕ1 + ϕ2)](3)

Equation (3) further clarifies the generation of the compound components. Addi-tionally, the compound components are shown in Figure 2 (b), which depicts therelationship between the input and output frequencies of the mixer. [4, 5]

|ω1-ω2| |ω1+ω2|ω1 ω2

v1

v2

vout

(a) (b)

Mixer

ω

Figure 2: (a) Frequency translation using a mixer and (b) a spectrum showing thefrequencies that are present at different ports of the mixer.

Mixers require two signals for enabling the up- and down-conversion process. Oneof the two signals contain the information that is to be sent or received (RF/IF/BB)

4

and the other signal is the LO signal that has the desired carrier or IF frequency.The features of the LO signal are critical for proper up- and down-conversion. [4, 5]

Two of the most important features of the LO signal regarding frequency transla-tion are spectral purity and phase noise which are determined by the LO generationcircuitry. Spectral purity denotes the cleanliness of the output frequency spectrumfrom undesired components while phase noise is the spreading of energy aroundthe desired frequency stemming from device noise or external interference. Thesetwo parameters are affected by the implementation of the LO generation circuitry.LO signals in ICs can be generated using different frequency synthesizer topologiesthat will be introduced in Section 2.2. When the LO signal has been properlygenerated, frequency translation can be performed successfully without corruptingany information beyond recognition. [4, 7]

2.2 Frequency SynthesisFrequency synthesis is the generation of specific frequencies from a stable reference orfrom a group of stable references. Usually the generation of frequencies includes sometype of mixing, multiplication or division of frequency in relation to the reference [3].The synthesized frequencies can be used for example as LO signals for performingfrequency translation in RF transceivers.

Frequency synthesis can be performed with different techniques, which can beseparated into two different approaches. These approaches are the direct and indirectfrequency synthesis. In direct frequency synthesis, the output frequency is constructedwithout a feedback mechanism whereas in the indirect method a feedback loop ispresent. In the indirect method, the reference frequency is compared with the outputwith some arithmetic operation applied to it, for example division or multiplication.[3, 8]

2.2.1 Direct Analog Frequency Synthesis

In a conventional direct analog frequency synthesis (DAFS), the desired outputfrequency is generated without the help of a feedback. The basic principle employedin the DAFS is the successive use of frequency translation using mixers and filtersuntil the generation of one final desired output frequency.

Mixers are the main components in DAFS responsible for generating new frequen-cies from known sources. Mixers generate sum and difference frequency componentsfrom the two inputs that are applied at the ports. The generation of two componentsis problematic from the perspective of fine accurate frequency generation. Eachsuccessive use of a mixer increases the number of frequencies by two. This problemcan be solved by using filters to limit the output to only one component. [3, 9]

Filters are used in DAFS to reduce the number of mixing components which inturn will limit the frequencies seen at the final output of the frequency synthesizer.The use of mixers and filters together lead to a structure which consist of numerousfrequency sources, mixers and bandpass filters as in Figure 3, which shows threestages of mixing and filtering. [3, 9]

5

The output frequency of the DAFS is determined by the frequency sources thatare used for frequency translation in the mixers. The sources used in the DAFS areprovided by crystal oscillators because of their sufficiently low level of phase noise.Using multiple crystal oscilators as frequency sources could possibly limit the interestin the DAFS. As an alternative to using multiple crystal oscillators, the frequencysources can also be derived from a single reference source by using multipliers anddividers which translate the reference to different frequencies for the mixing. [3, 9]

foutf1

f2 f3 f4

Stage 1

÷N

Figure 3: A conventional direct analog frequency synthesis circuit consisting of anumber of frequency sources, mixers and bandpass filters. [3]

DAFS based frequency synthesizers are rarely seen in IC implementations becauseof mainly two reasons. The most significant factor for the rarity is the excessiverequirement for hardware and the second reason is the leaking of spurious tones tothe output without proper shielding. Excessive numbers of mixers and filter arerequired in the pursuit for fine frequency resolution and small frequency step sizes. Inan integrated circuit, the hardware requirement directly translates to requirement fora large silicon area and thus also leads to increase in cost, which is a major downsideof this frequency synthesizer topology. [3]

2.2.2 Indirect Frequency Synthesis

The main principle behind indirect frequency synthesis is the generation of specificfrequencies with the help of a feedback loop. The purpose of the feedback is tominimize the error of the output by comparison with a known entity, the reference.For on-chip implementations of an indirect frequency synthesizer, the most commonone would be a phase-locked loop (PLL). [10, 11]

Phase-locked loops can be constructed with four distinct components assembledin a feedback loop. The core components of an analog PLL are a phase-frequencydetector (PFD), a loop filter (LPF), a voltage controlled oscillator (VCO) andfrequency dividers. These components are connected in a feedback loop in conjunctionwith a stable reference frequency consisting of a crystal oscillator. The placement ofeach individual block can be seen in Figure 4 which denotes a common PLL structure.[10]

These four blocks in a feedback loop can be shown to be able to generatefrequencies by analyzing the operation of the PLL in four steps. In the first step

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the PFD compares the reference frequency, fref , with the divided output, fdiv, andproduces an error pulse wave, verr corresponding to this difference. In the second step,the LPF averages out this error pulse wave with the intention of producing a suitablecontrol signal, vctrl, for the VCO. Third, the VCO produces an output frequencythat corresponds to this control signal. The last step employs the frequency dividerthat divides the output to a suitable frequency for comparison with the reference inthe PFD. [4, 10]

PFD LPF

VCO

÷N

fref

fdiv

verr vctrl fout÷M

fout/M

Figure 4: Block diagram of a generic Phase-Locked Loop with an additional frequencydivider at the output. [10]

A PLL can provide a specific output frequency when two conditions for the loopare achieved. The conditions are termed frequency and phase locking. A PLL canbe considered locked when the reference and divided output frequencies are matchedand the phase difference settles to a constant [4]. When the PLL has achieved alocked state, the following relations would apply for signals in the loop:

fref − fdiv = 0 (4)

fdiv = fout

N(5)

fout = N · fref (6)

From these equations, the critical information to observe is the relationship betweenthe output and the reference under locked conditions. Under locked conditions,Equation 6 indicates that the output of the PLL is N times the reference frequency.The output frequency can be multiple times the reference frequency because of thefrequency divider and the VCO. More specifically, the VCO can generate frequenciesthat are orders of magnitude larger than the reference because the frequency dividerwill divide the output to a suitable level for comparison in the PFD. This in turnguarantees that the PFD controls the VCO properly. Alternatively it could bethought that the capabilities of the frequency divider will determine the outputfrequencies of the PLL according to the Equation 6. [10, 12]

The most important feature of the divider in terms of the frequencies that canbe synthesized are the division ratio and the programmability of said division ratio.In a typical PLL frequency synthesizer, the frequency divider has a programmable

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division ratio N that can achieve integer or fractional values. The PLL will be namedeither integer-N or fractional-N PLL depending on the type of frequency divider inthe feedback loop. [4, 10]

The main difference between integer-N and fractional-N PLLs is the achievablefrequency resolution given a fixed frequency reference. For an integer-N PLL, theachievable frequency resolution is limited by the reference frequency whereas for thefractional-N PLL the defining factor is the resolution of the fractional division ratio.[3, 10]

2.3 Frequency DividersFrequency dividers are circuits that are capable of shifting the input signals to lowerfrequencies according to the division ratio. Different ratios are easier to achievewith different divider architectures with division by two being the most commonlyattainable division ratio. Dividers are commonly found in frequency synthesizers andright before up- and down-conversion mixers. [4, 8, 6]

Frequency divider designs can be categorized into three different architectureswith minor similarities amongst them. These architectures are regenerative, injection-locked and counter-based frequency dividers. Even though there are three differentarchitectures, all of them are based on feedback loop structures. The decision ofchoosing a suitable architecture is dependent on the desired input frequency range,division ratio(s) and programmability of the division ratio. [4, 10]

The most common division ratio is two and the resulting dividers are calleddivide-by-two circuits (DTC). DTCs find their use in numerous RF applicationsbecause of their added flexibility for system design. DTCs are common in transceiverswhere the frequency synthesizer generates an intermediate carrier frequency that istwice the desired down-conversion carrier frequency. The DTC is used to step downthis frequency to half to be suitable for down-conversion in the mixer. DTCs areused in such occasions in order to avoid distortion to the frequency synthesizer byinjection pulling effects from the other mixer input signal. The other benefit of usinga DTC is the ease of IQ signal generation. DTCs are also employed in high frequencyapplications because of strict phase noise requirements. [4, 8, 6, 10].

Frequency dividers can be more flexible if their division ratio can be altered usinga control signal. The presence of the control signal usually indicates that additionallogic circuitry is used to enable the toggling of the division ratio. The flexibilityintroduced by the programmable division ratio is the enabling of a wide range ofoutput frequencies using a single divider. [10, 11]

The upcoming subsections consist of introductions to the three main architecturesthat are used in the design of frequency dividers. Sections 2.3.1 and 2.3.2 consist ofintroduction to the regenerative and injection-locked frequency dividers by illustratingthe common implementations of DTC using said architectures. Section 2.3.3 consistsof the counter-based frequency divider and the ease of programmability of the divisionratio in this architecture. More focus is placed on the counter-based because of itspopularity in IC implementations.

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2.3.1 Regenerative Frequency Dividers

Regenerative frequency dividers, also known as Miller dividers, are a class of dividersthat consist of a mixer and a low-pass filter (LPF) in a feedback loop configuration[13, 14]. The feedback loop and the input frequency can be seen in Figure 5. Theterm regenerate is associated with this divider type because of the use of the outputfor generating the intermediate frequencies denoted by x in Figure 5.

The operating principle of the divider can be understood by considering thetask of each of the components in the loop. The mixer is used to generate theintermediate sum and difference components resulting from the input and outputfrequencies. Then, the LPF filters out the higher frequency component which is thesum component. Finally only the difference component is left at the output of thedivider. When the divider is operating as designed, the following equations holdtrue:

x = fin ± fout (7)fout = LPF (x) = fin − fout (8)

fout = 12fin (9)

From Equation (9), the circuit can be confirmed to operate as a divide-by-two circuit.In order for the circuit to produce a divided output, the mixer and the LPF have tooperate accordingly.

LPF Gfin foutx

Figure 5: A simple regenerative dividers consisting of a mixer, lowpass filter and anamplifier. [10]

The most important task for the LPF is to attenuate the sum component producedby the mixer. This undesired component is the third harmonic of the output whichis generated because of the loop dynamics. The third harmonic can be calculatedfrom Equation 7 and it equals fin + fout = 3

2fin. In case the LPF does not providesufficient attenuation, inductors can be considered in the design of the mixer toprovide additional suppression of the third harmonic. [4]

Regenerative dividers are not popular in high frequency applications becauseof two issues. The first issue is the phase noise generated by the mixer and LPFwhich limits the use cases of this architecture [10]. The second downside in this

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architecture is switching speed of the output frequency. The speed is limited by theloop dynamics and results in it taking multiple input cycles to reach a steady output.The limited switching speed rules out applications that require fast switching speedsfor the output frequency. [4]

2.3.2 Injection-Locked Frequency Dividers

Injection-locked frequency dividers (ILFD) are a class of dividers that employ afree-running oscillator as a part of the feedback loop. The basic structure of an ILFDconsists of an injection-locked oscillator and a mixer as can be seen from Figure 6.The basic structure of the ILFD is quite similar to the regenerative divider introducedearlier. [4, 15]

ILFDs and regenerative frequency dividers have similar block diagrams as can beseen by comparing figures 5 and 6. Both of the block diagrams consist of a feedbackloop that has a mixer for producing compound frequencies. The main differencebetween the two architectures is the existence of an injection-locked oscillator andthe lack of a dedicated LPF in the ILFD.

fin foutx

Injection-lockedOscillator

Figure 6: A simple block diagram of an Injection-locked frequency divider. [4]

The operating principle of the ILFD will show the similarities and differencesbetween it and the regenerative frequency dividers. The operating principle of ILFDsis based on the injection-locking of a free-running oscillator. The injection-lockingis possible with the help of a harmonic frequency of the oscillator that is generatedby the mixer. When the loop has achieved a steady state, the same signals fromthe regenerative frequency divider will be seen at the node x from figures 5 and 6,which are x = fin ± fout. Even though the x nodes of the two architectures displaythe same intermediate signals, there is a fundamental difference between the twoarchitectures which are the LPF and the injection-locked oscillator. [4, 16]

The injection-locked oscillator in the ILFD serves two purposes. The first task ofthe oscillator is the attenuation of the undesired mixing components. This is madepossible by the selectivity of the oscillator which essentially acts as a LPF. Thesecond task of the oscillator is the generation of a harmonic locked output frequency.

10

This generation is sensitive to the undesired frequency components, which makes theselectivity of the oscillator important.[4, 8, 17]

ILFDs have similar advantages and disadvantages to the regenerative frequencydividers, which make them rare in IC implementations. However, ILFDs have oneselling point that could potentially overcome the clear disadvantages in this architec-ture. This selling point is the low power consumption. A low power consumptionis achieved by using inductors in the design of the oscillator. The consequence forachieving lower power consumption is the narrowband operation range because offrequency dependency of the inductor. Furthermore, the use of inductors requiresadditional area in an IC implementation which directly leads to increase in the cost.Besides this, the ILFD also suffers from limited output frequency switching speedsimilarly to the regenerative divider. In case a low power frequency divider is desiredand the downsides are tolerable, ILFD could be a potential architecture for designinga frequency divider.[18, 19]

2.3.3 Counter-Based Frequency Dividers

Counter-based frequency dividers perform division by operating similarly to digitalcounters. A digital counter operates by changing the output when a rising or fallingedge of a clock signal is detected. This division operation based on counting is bestdemonstrated using a single-bit counter.[4, 10]

A single-bit digital counter can toggle its output between two values and can beshown to act as a divide-by-two frequency divider. A single-bit counter changes itsoutput in the presence of either a rising or falling edge. The sensitivity to eitheredge is determined by the type of counter. The reaction of the counter to only oneedge-type of the clock means that the other edge-type is essentially skipped. In otherwords, only a rising or falling edge will make the counter toggle its output. Becausethe counter only counts half of the edges, the resulting output waveform has onlyhalf the frequency of the clock signal used for toggling the counter. An illustration ofthe clock and output signals can be seen in Figure 7 along with a single-bit counter.[4, 10]

D Q

CLK

Out

(a)

CLK

Out

TCLK

TOut=2 TCLK

(b)

Counter

Q'

Figure 7: (a) A simple counter circuit consisting of a d-type flip-flop and (b) therespective clock and output signals in time domain.

11

The most common division ratio for a counter-based frequency divider is two. Acounter-based DTC is called the Johnson counter and is shown in Figure 8. Thepopularity of counter-based DTCs stem from the fact that they can operate at highfrequencies, can achieve good phase noise performance and that they can be chainedto achieve varying division ratios.

For a counter type frequency divider, the division ratio can be changed byincreasing the number of successive counter stages. The purpose of chaining dividerstages is the alleviation of the requirements for the successive dividers. Each successivestage has to operate at lower frequency than the preceeding stage which makes thedesign more straightforward. The design of the divider chain can be mainly focusedon the first divider which operates at the highest frequency. [4, 10]

Consequently, the chained structure of a divider makes the design of a pro-grammable division ratio obvious. The division ratio of a chained divider can bedesigned to be programmable with the addition of logic circuit(s). The logic circuitswould enable sections of the divider chain which essentially produce different divisionratios based on the enabled parts. [4, 10]

D

D'

Q

Q'

LatchD

D'

Q

Q'

Latch

CLK

CLK'

Master Slave

Figure 8: Block diagram of a Johnson Counter used as a divide-by-two frequencydivider consisting of two latches. [10]

The design of counter-based frequency dividers is highly parallel to the design offlip-flops. The operation of a counter circuit is based on them and in order to designa proper counter-based frequency divider an understanding for the core operation offlip-flops is essential. A flip-flop in a frequency divider is an edge-triggered devicethat passes the input to the output in the presence of an edge of a clock signal.Otherwise, the output retains the previous input value. A counter can be made byconnecting the flip-flops output back into the input with negative feedback as isshown in Figure 7 (a). Flip-flops can achieve these functionalities because of the use

12

of latches. [4]A latch is a level-sensitive circuit that can be used to form a flip-flop. A latch is

a circuit that either passes the input to the output or stores the previously sampledinput value. Either of these two modes will prevail depending on the state/level ofthe clock signal. A flip-flop can be designed by connecting the output of one latch tothe input of another one. Additionally the clock signal for one of the two latches hasto be inverted to enable the functionalities of a flip-flop. [4]

The basic idea behind the operation of two latches as a flip-flop is that one ofthe two latches is in sampling mode whereas the other is in store mode. The latchesoperate in opposing modes because of the inversion of the clock signal in the flip-flopstructure. When the clock signal changes levels, the two latches exchange theirmodes. During the change of modes, information is passed from one latch to theother. Externally this intricate operation is seen as an edge triggered circuit whicheither forwards information or stores the previously sampled one. [4]

For a counter to operate properly, the latches forming the flip-flops have to switchtheir states in a single clock cycle. Otherwise, a condition known as metastability hasto be considered. Metastability is a condition where there is no sufficient amount oftime to ensure that the input has been properly regenerated in the storing mode. Inother words, there is no guarantee that the information at the output of the flip-flopis the same as the sampled input. The chance for a corrupted output to occur canbe minimized by using the latches at their intended design frequency range. [4]

A counter circuit can operate either synchronously or asynchronously dependingon the way that the trigger signal is delivered to the flip-flops. In the synchronouscase, the flip-flops are triggered using a common clock signal whereas in asynchronouscounter the triggering signal is usually the output of a preceding flip-flop stage.Synchronous divider have better phase noise performance whereas asynchronousdivider can achieve more dynamic division ratios. [4]

The flexibility and options in designing a counter-based frequency divider makethem popular in IC implementations. This can be attributed to the modular designof divider stages for achieving a high division ratio and to the ease of designing aprogrammable division ratio. Additionally, the design of the frequency divider canbe attributed to latches which are relatively easy to analyze and design and do notemploy inductors. [4, 10]

13

3 Fractional Frequency DividersIn frequency synthesizers, a fine frequency resolution can be mainly achieved in twodifferent ways. The first way is to use a tunable frequency source that is then divideddown into a desired value. In this case, the frequency resolution is determined bythe accuracy of the tuning of the frequency source. The alternative approach isto have a generic precise fixed frequency source which is divided with the help ofa programmable fractional frequency divider (FFD). In this case, the frequencyresolution is mostly determined by the accuracy of the fractional frequency divider.[11, 8]

This section of the thesis consists of three different parts. The first part isdedicated to the definition of fractional frequency that is generated by differentfractional frequency dividers. The second and third parts are introductions tofeasible fractional frequency divider topologies.

3.1 Defining Frequency for Fractional DividersFrequency can be defined in two different ways. The first definition is the ideal formof frequency and the second is the time-averaged frequency. An ideal signal wouldbe a waveform that has the proper frequency/period with a constant duty-cycle. Onthe other hand, the time-average signal is an approximation of this ideal form withthe use of two or more frequencies in succession. Time-average frequency could bethought of as a combination of different periods that over a time frame will achievethe desired frequency. [3]

Frequencies generated by fractional dividers are produced with the use of fractionaldivision ratios Nfrac in the dividers. In other words, fractional frequency is definedas ffrac = fref

Nfrac, where the Nfrac is of form N + α where N is an integer and α is non-

integer valued. Fractional frequency can also be either of the ideal or time-averagetype. By definition, the ideal fractional frequency has a period of T = 1

ffracwhereas

the time-average frequency has an instantaneous period of Tinst = Nfref

dependingon the current integer N used in the division for approximating Nfrac. Figure 9illustrates a clock signal that is divided into two different waveforms that correspondto time-average and ideal fractional division. [3]

Time-average frequencies are generated when integer divisions are performed insuccession with different division ratios. Time-average frequency is a concept that isbest demonstrated with the help of a counter-based divider. Counter based frequencydividers are limited to perform divisions that are of one reference period in resolution.In other words, the counter-based dividers are limited to integer division. This hasbeen illustrated in the waveform in the middle of Figure 9 showing successive divisionwith varying division ratio. [3, 20]

Time-average fractional frequency signal occasionally has phase offsets whencompared to the ideal divided frequency as can be seen by comparing the waveformsin Figure 9. The phase offsets are a result of using integers to approximate a fractionalvalue. The presence of phase-offsets means that time-average frequencies cannot be

14

CLKin

Time-Average

Ideal

Nfrac=2.5

2Tin 3Tin

2.5Tin

Figure 9: Time-domain signals of time-average and ideal frequencies of a fractionalfrequency divider.

directly used in instantaneous phase sensitive applications, such as down-conversionmixers. [4, 20]

Time-average and ideal fractional frequencies can be generated with differentfractional frequency divider topologies. Ideal fractional frequencies can be generatedby using regenerative dividers. In contrast, time-average frequencies can be generatedby using multi-modulus counter-based frequency dividers. [4]

3.2 Direct Fractional Frequency DividersDirect fractional frequency dividers are frequency dividers that can directly achievean ideal fractional frequency. Ideal fractional frequencies can be achieved withregenerative and injection-locked based frequency dividers. [8, 14, 21].

Currently there are some limitations for direct FFDs that are related to theachievable division range and ratio. The earlier regenerative and injection-lockedoscillator based frequency divider architectures can be modified to have a fractionaldivision ratios with the help of integer dividers. [21]

Regenerative frequency dividers can be modified to achieve fractional divi-sion ratios with the use of integer dividers. Fractional ratios can be achieved byplacing an integer divider into the feedback path of a regenerative divider. Thefractional frequency divider using this topology is shown in Figure 10 which consistsof a mixer, loop-filter and integer divider. Similar approaches can be used on theinjection-locked frequency divider to achieve fractional division ratios.

The achievement of a fractional division ratio is attributed to the effect theinteger divider has on the signals in the loop. Most notably, the integer divider in thefeedback path feeds a divided waveform of the output signal. Following equations

15

hold true when the circuit operates as desired:

x = fin ± 1N

fout (10)

fout = LPF (x) = fin − 1N

fout (11)

fout = N

N + 1fin (12)

The fractional division ratio can be evaluated from Equation 12. The division ratiois defined as N+1

N= 1 + 1

Nwhere 1

Nis the fractional part. In conclusion, the addition

of an integer divider in the feedback path of a regenerative divider has produceda fractional division ratio that is defined by the division ratio of the used integerdivider.

In this design, the resolution of the fractional part can be evaluated by calculatingthe difference between two integer dividers separated by a unity step. The followingequations show this calculation for the resolution:

∆α = 1N

− 1N + 1 (13)

∆α = 1N(N + 1) (14)

The resolution of the fractional part is defined by reciprocal of the multiplication ofthe two integer division ratios. In other words, the larger the two division ratios are,the finer the fractional frequency resolution in theory.

LPF Gfin foutx

÷N

Figure 10: Block diagram of a regenerative fractional frequency divider. [4]

Despite being able to generate fractional division ratios, regenerative fractionalfrequency dividers have several limitation that reduce their usage as the go totopology. One of the issues is the stricter requirements for the low-pass filter inthe loop resulting from the mixer. This deduction is based on Equation 10, whichtogether with Equation 12 shows that the difference between the two frequencycomponents at node x is only 2

N+1fin. The larger the division ratio is the closer

16

the two frequencies are at the output of the mixer and a steeper low-pass filter isrequired. In other words, the resolution and range of achievable fractional divisionratios is limited by the capabilities of the low-pass filter.

Another downside in this topology is the time that is required to achieve thecorrect output. Regenerative frequency dividers are known to require multiple inputclock cycles before reaching a steady output. Occasionally this might be an issue inapplications that require instantaneous correct frequency. [4]

3.3 Multi-Modulus Based Fractional Frequency DividerFractional frequencies can be achieved from a reference frequency with the help ofmulti-modulus programmable frequency dividers. Multi-modulus frequency dividers(MMD) are usually designed using counter-based approaches that can toggle thedivision ratio with the help of a control signal. The use of counter-based frequencydivider indicates that the output frequency of the divider is of the time-average type.[3]

Time-average fractional frequency requires post-processing before it can be usedin instantaneous phase sensitive applications. A time-average signal can be processedto become closer to the ideal waveform by compensating deterministic errors in thegenerated time-average frequency.

3.3.1 Multi-Modulus Frequency Divider

Multi-modulus frequency dividers (MMD) are a class of dividers that can vary theirdivision ratios in a controlled manner. MMDs are commonly designed by chainingcounter-based frequency dividers and using logic gates to enable sections of thischain. The chaining introduces a flexible way of designing different division ratios.[3, 22, 23, 24, 25].

Three of the core design aspects for the MMD are operating frequency range,number of achievable division ratios and sufficiently fast switching speed betweenthese division ratios. Clearly, the achievable division ratios are determined by thechained dividers whereas the switching speed is determined by the logic circuits andthe circuit responsible for producing the control signal for the logic. [22]

MMDs can be designed with the help of chained counter structures and logiccircuitry. A simple dual-modulus frequency divider is shown in Figure 11. Thedual-modulus frequency divider consists of two flip-flops (FF), two logic gates and adigital circuit for generating the control signal which is not explicitly shown in Figure11. The logic gates enable the use of such a circuit for division with two integerdivision ratios. This can be confirmed by analyzing the effect of the CTRL signal.

Different division ratios can be achieved by changing between the two states ofthe CTRL signal. The first obvious division ratio can be achieved by having CTRLsignal be at logic HIGH. When CTRL is set to HIGH, the output of the OR gatewill be HIGH regardless of the second input coming from the output of the leftmostflip-flop. This fixed value of the OR gate makes the following AND gate only sensitiveto its other input. This input is produced by the output of the rightmost flip-flop in

17

D Q

Q'FF

D Q

Q'FF

CLK

CTRL

Out

D Q

Q'FF

D Q

Q'FF

CLK

Out

(a)

(b)

Q2'Q1 D2

Figure 11: (a) 2/3-modulus divider consisting of flip-flops and logic gates and (b)divide-by-3 mode of the same circuit when CTRL is set to LOW. [4]

Figure 11 (a). In other words, the dual-modulus divider is logically reduced into atypical divide-by-two circuit such as in Figure 7 (a). [4]

The second division ratio can be achieved by setting CTRL to logic LOW. Bysetting the CTRL to low, the OR gate is essentially bypassed and the output fromthe leftmost flip-flop will be connected to the AND gate. The circuit is logicallyequivalent to the circuit shown in Figure 11 (b). The division ratio of such a circuitmay not be immediately recognizable and thus a brief analysis might be in place todeduce the ratio. [4]

One way to help the deduction of the division ratio of the circuit in Figure 11 (b)is to find out the feasible signal states in different nodes of the circuit. These signalstates are collected in Table 1 and are illustrated in Figure 12. The table shows thecyclic nature of the signals which in essence show a division by 3 with the outputhaving a duty cycle of 33.3%. The Table 1 should be considered as cycling betweenstates from from the top row towards the bottom row and then back to the top.

Table 1: Feasible signal states in the divide-by-3 circuit

D2 Q′2 Q1 Q′

2 = Out1 1 1 00 0 1 10 1 0 0

18

CLK

D2

Q1

Q2'

Figure 12: Waveforms in the divide-by-3 circuit including propagation delays.

The analysis of feasible signal states in the divider starts by evaluating whichsignals are sensitive to the clock signal and which are not. D2 is a signal correspondingto the output of the combinational AND logic gate which is not sensitive to the clockwhereas Q1 and Q2’ are the outputs of flip-flops that are clock edge sensitive. D2 isthe result of an AND operation between Q1 and Q2’, Q1 is a sampled version of Q2’and finally Q2’ is an inverted sample of D2.

First, assume that D2 is 1. This means that both Q1 and Q2’ have to be 1because of the AND gate. When a clock edge arrives to the divider, the Q2’ willoutput an inverted version of D2 while Q1 will maintain its value of 1 because itsamples Q2’ when it is still 1. Now that Q1 and Q2’ are different, the D2 will changeto 0 because of the AND gate. This is the first transition and can be seen in Figure12 on the left side with black dashed lines. The same transition can be seen betweenthe first and second row of the Table 1.

When the second clock edge arrives, both Q1 and Q2’ will switch their statesas their respective inputs of Q2’ and D2 changed states during the time intervalbetween the first and second clock edge. This simultaneous switching can be seen inthe middle of Figure 12 with red dashed lines and the state is represented by thelast row in Table 1.

When the third clock edge arrives, Q1 will first change to 1 because Q2’ is 1. Nowthat both Q1 and Q2’ are 1, the D2 will change to 1 because of the AND gate. Everysignal is now 1 and it is the same state as what the analysis started with. Essentiallythere are three different states that are cycled in steps and together represent adivision-by-3. The last transition back to the "original" state is illustrated with theblue dashed lines in Figure 12.

Based on the analysis of the feasible signal states in the circuit presented inFigure 11 (b), there are only 3 feasible states which indicates that the circuit acts asa divide-by-3 circuit. The circuit is capable of dividing by 3 because a single loop of

19

feasible signal states takes three clock cycles.To conclude, it has been shown that a dual-modulus dividers can be designed by

enabling different division ratios of a chained counter circuit with the help of logicgates. In other words, more counter circuits can be chained and more logic gates canbe used to acquire a wide variety of division ratios.

The next question in line is how to design the circuitry that controls the logicgates in order to achieve the functionalities of a fractional frequency divider.

3.3.2 Fractional Division Ratios with the Use of Multi-Modulus Fre-quency Divider

The use of a MMD as a fractional frequency divider is based on the toggling of thedivision ratio in a controlled manner. The toggling of the integer division ratios willproduce an output that is a fractional frequency over a time-period. In other words,a time-average fractional frequency can be achieved by switching between two integerdivision ratios in a specific manner.

The achievable fractional division ratios are dependent on the division ratios thatare present in the MMD. The achievable fractional division ratio can be shown to beof following form:

Nfrac = A

A + B· N + B

A + B· (N + ∆s) (15)

Nfrac = N + B

A + B∆s = N + α, (16)

where N is an integer value, ∆s is the step size between the two integer divisionratios, A and B correspond to the ratio when each of the two division ratios areenabled, and α which denotes fractional part of the division ratio.

The most important information from these equations is that the fractional partα is dependent on the toggling ratio and the step size ∆s between the two integerdivision ratios. α can be strictly defined by the toggling ratio by choosing the stepsize between the two integers to be a unity step. With this setup, the resolution of αis the responsibility of the circuit that controls the toggling of the division ratio.

A unity-step dual-modulus frequency divider can be used to demonstrate theachievement of fractional division ratios of the form shown in Equation 16. As ademonstration of a fractional division ratio of 2.4, following relations have to besatisfied:

Nfrac = 2.4 (17)N = 2 (18)

N + ∆s = 3 (19)

α = 25 = 0.4 (20)

These equations show the requirements for the integer division ratios and the togglingratio α for the larger integer.

20

For achieving the desired toggling ratio and fractional part α, a control circuitryfor the division ratio of the MMD is required. Most of the classical implementationsof the division control are based on the use of an accumulator. An accumulator isessentially a memory device that can be incremented by a specified value until thememory overflows. A simple accumulator is also known as a first-order Σ∆-modulator.In a fractional frequency divider, this specific value has a role in controlling thefractional part of the division ratio in MMD. [3, 26]

A simple accumulator can used to produce specific control patterns for use in aMMD for generating fractional frequencies. The purpose of the accumulator is toproduce a control bit when sufficient amount of pulses have occurred to warrant thechange in division ratio.

In order to achieve the desired control pattern for a specific fractional divisionratio, the accumulator has to be incremented by the desired fractional part α ofthe division ratio. As an example, the overflow and residue/current values of anaccumulator for achieving α = 0.4 are shown in Table 2. An overflow bit is generatedwhen the current value in the accumulator surpasses 1.

The control pattern for the MMD is shown as the column with the overflow valuesin Table 2. The pattern shows that there are three divisions by the smaller value, thenumber of 0s, and two divisions by the larger value. In other words, two out of fivetimes a division by the larger value is performed. This is the same as α in Equation20 and thus demonstrates the use of an accumulator as a circuit for generating theproper control pattern for achieving fractional division ratios in a MMD.

Table 2: Accumulator overflow and residue for fractional division by α = 0.4

Overflow Residue0 0.40 0.81 0.20 0.61 0.0

A waveform with the division pattern from Table 2 for achieving fractional divisionratio of 2.4 is illustrated in Figure 13. The figure shows the output of a MMD andan ideal frequency corresponding to the same division ratio. The use of a MMDmeans that the fractional frequency cannot be achieved directly, but will instead beaveraged over a time-period which is 12 input cycles in this example. The number ofinput cycles required for the averaging is dependent on the desired fractional divisionratio.

In order ro have proper timing in the control pattern, the accumulator has toincrement in respect to the MMD output signal and not the clock signal fed to theMMD. The MMD output signal has to be used, because the accumulator generatesthe overflow pattern in accordance to the number of total division that are required

21

CLKin

MMDout,A

MMDout,ideal

-0.4Tin -0.8Tin -0.2Tin -0.6Tin 0Tin0Tin -0.4Tin

Nfrac=12/5=2.4

Figure 13: Fractional division with a multi-modulus integer divider and the resultingdeterministic jitter in respect to the input clock. The division pattern is |2 2 3 2 3|.

for achieving a specific fractional division ratio. This is to guarantee the propernumber of N and N+1 divisions. [27]

Figure 13 also shows the phase-offset between the MMD output and the idealfrequency. The phase-offsets result from the truncation error presented by theaccumulator. Truncation error occurs because of the approximation of a fractionalvalue with the use of integer values. Incidentally, the phase-offset can also be seenas the residue value present in Table 2. In order to use time-average frequencies ininstantaneous phase sensitive applications, the phase-offsets have to be compensated.

3.3.3 Phase-Offset Compensation

Fractional frequency dividers that produce time-average fractional frequencies requirephase offset correcting techniques to transform the frequency to be closer to an idealsignal with consistent duty-cycle. Phase offset correction will attempt to transformthe time-average fractional frequency signals to have proper instantaneous phasesthat correspond to the desired fractional frequency. The phase offset correctingtechniques are commonly based on the use of delay elements. [20, 28, 29]

Phase-offsets/deterministic jitter (DJ) in time-average fractional frequency di-viders are a result of truncation error that are born from the approximation offractional values with integer ones. Deterministic jitter can be defined in respect tothe input clock because of the counter-based operation of the MMD. In Figure 13,the ideal output signal and the DJ between the actual output and the ideal output isshown. The DJ present in the MMD output limits the usage of this particular signalto applications where instantaneous phase is not important. Alternatively, if a signalfrom a MMD-based fractional frequency divider was to be used in an instantaneousphase sensitive application, the DJ would have to be compensated. The compensationof deterministic jitter starts from the analysis of how it is generated.

Positive and negative deterministic jitter is produced when a value different fromthe desired one is used in the division process. Negative DJ is produced when asmaller value is used whereas positive DJ is produced when a larger than the desiredvalues is used. For example in Figure 13, the DJ produced by division by 2 and 3 for a

22

fractional division ratio of 2.4 are 2Tin − 2.4Tin = −0.4Tin and 3Tin − 2.4Tin = 0.6Tin

respectively. The deterministic jitter can accumulate as a result of series of divisions.This accumulation of DJ can be though of as a residual phase-offset/DJ.

In Figure 13 the residual DJ is most of the time negative which indicates that intime domain the output arrives earlier than desired. The amount the residual DJchanges depends on the current integer division ratio as was introduced earlier. Theresidual error will be zero when a complete cycle for achieving a specific division ratiois reached. This is the same number of input cycles that are required for achievingthe desired fractional ratio using the MMD. Alternatively, this could be though ofas the accumulator having 0 residue. This deduction can be confirmed by looking atthe residual DJ in Figure 13 and the residue values of the accumulator in Table 2.

Negative residual DJ can be compensated with equal amount of positive delay. Theamount of delay that is required for compensating the residual DJ is determined bythe residual error that is present in the accumulator. In other words, the accumulatorcan also serve as a control circuit for the delay compensating circuit.

There are two main approaches for compensating the deterministic jitter: a delayline or phase interpolation based approaches. A delay line based approach removes thedeterministic jitter with the use of finely controlled delay elements whereas a phaseinterpolator produces the compensation with the use of interpolation between twosignals. Figure 14 illustrates the desired output waveform of a phase compensatingcircuit, which is to be capable of generating different phases with a predeterminedoffset between them. Both of the delay line and phase interpolator approaches arefeasible for generating the waveforms of Figure 14.The difference between a chosenapproach are their respective challenges and capabilities. [20, 30]

Tin

Tin/8

Figure 14: Performing phase compensation by choosing correct phase between equallyspaced phases.

Delay line based DJ compensation is mainly concerned with the proper calibrationof the delay line. The delay line has to be precisely calibrated to be capable ofproducing a delay of one pre-division input clock period Tin. The requirement forthis is because the accumulator used to produce the control pattern will only produceresidual errors that are in the range of 0 to 1 Tin. Delay line based approaches are

23

generally quite linear but the difficulty is indeed in the proper calibration. [20]

A

B

AB

Figure 15: Phase interpolation of two signals.

Phase interpolation based approach removes the DJ with the help of interpolationof two signals. The main idea behind the interpolation is the generation of anintermediate signal that is between the two phases that are used for interpolationsuch as in Figure 15. In Figure 15, signals A and B are interpolated with each otherto generate the AB signal that has an equal phase-offset with A and B. With carefulselection of this purposely generated phase offset, the deterministic jitter can becancelled.

For compensating the DJ using phase interpolation, one of the signals would bethe direct output of the MMD and the second one would be a delayed version of thesame signal. The delay between the two signals is equal to one input cycle of thepre-division clock signal. The one input period long delay is sufficient because theaccumulator will in theory never produce an output that has a residual DJ over oneinput clock period.

Ideally a phase interpolator is capable of interpolating into any phase valuebetween the two input signals. By selecting the phase that corresponds to therequired delay for compensating the residual DJ, a spectrally pure output signal canbe generated. The selection of the correct phase is possible with the use of successiveinterpolation steps which increase the achievable phase resolution.

24

4 Open-Loop Fractional Frequency Divider De-sign

Fractional frequency dividers (FFD) can be used to extend the range of frequenciesand resolution produced by a frequency synthesizer. In this thesis, an open-loopinstantaneous phase FFD is designed that is based on a multi-modulus counter-basedinteger divider and phase compensation.

This section of the thesis consists of details and specifications regarding thedesigned FFD. Section 4.1 consists of specifications that are fulfilled by the designedFFD. Section 4.2 is dedicated to system level presentation of the designed FFD. Sec-tion 4.3 presents the designed counter-based multi-modulus integer divider. Section4.4 shows the designed Σ∆-modulator based digital control circuit and Section 4.5shows the design of the phase interpolator responsible for compensating phase offsetsproduced by the integer divider and Σ∆-digital control circuit.

4.1 Design SpecificationsFractional frequency dividers can be used to shift an input clock frequency intoanother frequency range according to the achievable fractional division ratios of thedivider. In this thesis, the designed fractional frequency divider is designed to operatewith an input signal with frequencies from 6 to 16 GHz. This range is desired tobe shifted into 3–4 GHz range with a fine frequency resolution. With this in minda fractional frequency divider with a division range from 2 up to 4 is sufficient tofulfill these requirements. Furthermore the results from the frequency divider shouldhave correct instantaneous phase for further processing of the output signal of thefrequency divider.

Table 3: Specifications for fractional frequency divider

Parameter ValueInput frequency range 6 GHz to 16 GHzOutput frequency range 3 GHz to 4 GHzResolution Σ∆ 13 bits and PI 8 bits

The fractional divider is designed using Cadence Virtuoso environment with28 nm CMOS and the resulting design is simulated with ELDO circuit simulator.Comparisons to the specifications will be performed during pre- and post-layoutversions of the circuit.

4.2 System Level DesignThe main goal is to design a stand-alone fractional frequency divider (FFD) thatsupports the operation of a frequency synthesizer. This setup of frequency synthesizerand fractional divider is shown in Figure 16. Essentially the FFD acts as an external

25

part of a frequency synthesizer for enabling fine frequency resolution and wider rangeof output frequencies.

fref ÷Nfrac

fout/NfracSX

fout

This work

FCW

Figure 16: Frequency synthesizer (SX) and an open-loop fractional frequency divider.

The goal in designing the fractional frequency divider is to achieve a good fractionalfrequency resolution. For achieving a good fractional frequency resolution, a counterbased multi-modulus frequency divider (MMD) is a highly feasible topology. Themost attractive points of the counter based MMD are the relative ease in designingprogrammability, wide input frequency range and inductorless design. These threepoints together will result in relatively straightforward design flow and layouting.

In order to generate fractional frequencies in a counter based divider, a divisionratio control circuitry is necessary. This control can be performed with a digitalΣ∆-modulator based design in order to achieve control of the division ratios of theMMD and fine fractional frequency resolution. Be reminded that the fractionalfrequency resolution α can be solely defined by the Σ∆-modulator that controlsthe division ratio when the division ratios of the MMD are designed with unitystep separation. With this setup the desired fractional frequency resolution can beoutsourced to designing a suitable Σ∆-modulator.

The decision to use a MMD and a Σ∆-modulator results in an output signalwaveform that can achieve the desired fractional division ratios in a specific timeframe only which is to say that it is a time-average signal. The time-average fractionalfrequency signal has some deterministic jitter (DJ) resulting from the truncation errorproduced by the Σ∆-modulator. This DJ has to be compensated in order to achieveproper instantaneous phase performance from the fractional frequency divider. DJhas to be compensated in time-domain when the designed FFD operates as stand-alone divider [20]. A phase interpolation based method is chosen for achieving therequired phase offset cancellation. The block diagram of the open-loop instantaneousphase Σ∆ fractional frequency divider is shown in Figure 17

The fractional frequency divider is completely designed using differential circuitsbut in the following sections describing the details of the FFD, mostly single endedversions are shown for clarity.

26

MMD PI

ΣΔ

fin

FCW

fin/Nfrac

2Tin 3Tin 2.5Tin 2.5TinTin

Figure 17: Block diagram of the designed open-loop fractional frequency dividerconsisting of a multi-modulus frequency divider, phase interpolator and a Σ∆-modulator based digital control circuit.

4.3 Design of Multi-modulus Integer DividerA fundamental part of a fractional frequency divider is the multi-modulus integerdivider (MMD). The MMD generates the time-average fractional frequency signalsby properly toggling the integer division ratios. Precise toggling of the division ratiois critical for the MMD to act as a fractional frequency divider.

As a starting point of designing the MMD, one of the core questions is whatdivision ratios are needed to achieve the desired output frequency range. Divisionfrom 6–16 GHz down to 3–4 GHz requires integer division ratios of two, three andfour. These division ratios are closely spaced and should be used only in unity steppairs as is discussed in Section 3.3.2. The divider should operate in unity step divisionmode pairs of 2/3 and 3/4 depending on the input frequency and the desired outputfrequency.

For the actual implementation of the division ratios, the largest integer ratiois the defining factor for the design. The design requires at least two flip-flops(FF) for a counter based division-by-4 frequency divider circuit. With two FFs theremaining integer division ratios of 2 and 3 do not required more FFs and can insteadbe designed with the help of logic circuits and other control circuitry for enablingdifferent parts. The challenge in enabling multiple division ratios is in designingsuitable logic that enables different integer division ratios sufficiently fast.

Now that the rough design aspects of the MMD are clarified, the next design

27

question is the speed requirements for FFs and latches forming them. The inputfrequency range of 6-16 GHz means that the latches in the MMD design have tobe fast. At this frequency range the fastest latch topology employs some form ofcurrent-steering. The circuit designs that use current steering are referred to asCurrent-Mode-Logic (CML) circuits. [4]

4.3.1 Architecture

The MMD design starts by considering the largest division ratio that the divider issupposed to work at. In this case, the largest division ratio is 4 which requires twoflip-flops (FF) to form the counter. In order to have better understanding of what isrequired of the MMD, a quick consideration for different division ratios is presented.

Division by 4 requires two FFs and an inversion of the latter FF output that isfed to the input of the first FF. Similarly, a division by 2 requires one FF and aninversion of the output of the first FF. Division by 3 requires two FFs and a suitablelogic gate which enables the proper division. These requirements together couldbe summed as the MMD requiring at least two FFs, inversion capability of the FFoutputs and some logic circuit for enabling different division modes.

The designed divide-by-2/3/4 multi-modulus frequency divider is shown in Figure18 and it consists of two flip-flops, a division control circuit made out of AND gatesand a XNOR logic gate. The operating principle of this divider can be evaluated byanalyzing the effect of the division control circuits and the XNOR gate.

D Q

Latch

D Q

Latch

D Q

Latch

D Q

Latch

fout

clk

D1

XNOR

ctrl<1>

ctrl<0>

DivCtrl

clkΣΔ

Q1

Q2

Figure 18: Block diagram of a multi-modulus integer divider with division controllogic consisting of AND gates and a XNOR-gate.

In this design, the logic circuit is based on the XNOR gate which provides therequired separation of division modes. The features of XNOR gate in this dividerdesign can be analyzed by considering the truth table for a two input XNOR gate.First consideration is how can a XNOR gate provide division by 3 capability.

28

One can notice similarities with the logic in division-by-3 and a XNOR gateby comparing the truth table of a XNOR gate in Table 4 to the Table 1, whichrepserents division by 3. The similarities between the tables are in the last threerows of the tables. In essence XNOR gate can be used to introduce the required logicfor division by 3. The circuit utilizing the division-by-3 mode with a XNOR gatecan be seen in Figure 19 (b) and the respective feasible signal states are in Table 5.

Table 4: XNOR truth table.

X Y X ⊕ Y0 0 10 1 01 0 01 1 1

Table 5: Feasible signal states in the divide-by-3 circuit using a XNOR-gate. Eachstate is cycled from top to bottom.

D1 Q1 Q2 Q1,i = Out1 0 0 00 1 0 10 0 1 0

The other benefit of the XNOR gate is that it can also provide the requiredinversion of output for division by 2 and 4. The XNOR gate can act as an inverterwhen one of its inputs are fixed to 0 as can be seen from Table 4 where the twotopmost rows have a fixed X to 0 and the resulting output is an inversion of theother input Y.

This can be accomplished with a circuit that provides a fixed 0 when a controlsignal is set to a desired value. In this MMD design, this functionality is implementedwith the DivCtrl circuit consisting of AND gates shown in Figure 18.

The DivCtrl circuit serves two purposes that define the division ratios. The firsttask is enabling the division by 3 by passing the output values of the two FFs throughto the XNOR gate. The second task of the DivCtrl circuit is to provide a fixed value0 to one of the XNOR gate inputs when division ratio of 2 or 4 are desired. Thesedivision ratios of two, three and four are illustrated in Figure 19.

Changing between division ratios is possible with the control of the DivCtrlcircuit. The desired unity step division ratio pairs for the MMD are 2/3 and 3/4which are enabled by setting either ctrl<1> or ctlr<0> to 1 in Figure 18. By settingctrl<0> to 1, the divider acts in the 2/3 mode as the AND gate that has a 1 as acontrol signal will directly pass its input into the output which in this case is theleftmost FF corresponding to division by 2. In this case, toggling ctrl<1> will enable

29

D Q

Latch

D Q

Latch

D Q

Latch

D Q

Latch

fout

clk

D1Q1

D Q

Latch

D Q

Latch

D Q

Latch

D Q

Latch

fout

clk

D1Q1

Q2

D Q

Latch

D Q

Latch

D Q

Latch

D Q

Latch

fout

clk

D1Q2

(a)

(b)

(c)

XNOR

clkΣΔ

clkΣΔ

clkΣΔ

Figure 19: (a) Divide-by-2, (b) divide-by-3 and (c) divide-by-4 modes of the multi-modulus divider.

either division by 2 or 3 by either directly forwarding the rightmost FF output tothe XNOR gate or providing a fixed value 0 for the XNOR to act as an inversionfor the division by 2. The division ratios corresponding to the states of the controlsignal are collected into Table 6. The most important information in the Table isthat the division ratio of the pairs can be toggled using a single control bit.

Another important point from the Table is that there is a forbidden state whereboth of the control signals are set to 0. In this situation both of the XNOR inputsare set to 0 because of the AND gates, and the XNOR gate will output a fixed1 regardless of the other inputs to the DivCtrl circuit. This eventually stops thedivision process as every signal stays at 1 after the XNOR. This scenario where bothof the control signals are set to 0 will not happen due to the designed Σ∆ digitalcontrol circuit. As a result, the only problematic situation is a case where a divisionratio transitions into division-by-3 when and if the XNOR inputs, Q1 and Q2, are 1.

30

Table 6: Control signal states and the corresponding division ratios of the multi-modulus integer divider.

CTRL<1> CTRL<0> Mode0 0 no output0 1 div-by-21 1 div-by-31 0 div-by-4

However, this state is not reachable because of the Σ∆ digital control circuit whichensures that switching of the division ratios only occur during the falling edge of theclock signal which is derived from Q1 as can be seen from Figure 19. This aloneensures that both Q1 an Q2 are not simultaneously 1 during the switch to divisionby 3.

The forbidden state could in theory be reached during the startup of the integerdivider as Q1 and Q2 would be in a unknown state and the Σ∆ digital control circuitwould not react to anything. To ensure proper initiation of the circuit at the start,the initial division ratio should not be chosen to be 3 but instead 2 or 4, which dueto inversion will necer get stuck in any states.

Now that the logic related aspects of the design are clear, the next question iswhat kind of logic family should be used to fulfill the speed requirements for thelatches, XNOR gate and AND gates in DivCtrl circuit. One of the fastest integratedcircuit logic families is the Current-Mode Logic (CML). Their speed advantages areattributed to their capability to be enabled and disabled fast. [4]

4.3.2 Current-Mode Logic Latch

Current-Mode Logic (CML) latches are frequently used for counter-based frequencydividers. They are suitable for multi-gigahertz division operations with non-rail-to-rail clock signal. CML latches are considered one of the fastest types of latchesavailable. [4, 10]

The speed of a CML latch can be attributed to its structure which can be seenin Figure 20. The speed advantage of a CML latch is achieved because of thecurrent-steering capabilities enabled by the M5 and M6 transistors. Current-steeringin this case means that upon activating either M5 or M6, their respective stackedtransistors will also start functioning. In other words, when either one of these twotransistors is enabled by the clock or control signal, the latch will operate either inthe sampling or storing/regeneration mode.

The sampling mode is based on the differential pair made up of M1 and M2 andthe store/regeneration mode is based on the cross coupled pair M3 and M4. Onlyone of these two transistor pairs will be active and it depends on the clock signalthat turns on transistor M5 or M6.

During the sampling mode, the CML latch will amplify the differential signal

31

DP

DN

CKP

CKN

QN

QP

M1 M2

M5 M6

M3 M4

R R

Figure 20: Conventional current-mode logic latch. [4]

that is present at the input of M1 and M2. In this mode, the latch is transparent tothe input signal and thus the output is the same as the input.

On the other hand, the cross coupled pair of the M3 and M4 are connected as apositive feedback circuit, which regeneratively amplifies the difference between theoutput nodes. This amplification occurs until either of the output nodes reach thesupply voltage and one of the transistors turn off. his regenerative process occursprovided that the output voltages QN and QP have crossed before the crossing ofCKN and CKP as can be seen in Figure 21. The use of regeneration of signals atthe output is one of the contributors why CML latches are fast. [4]

CML based circuits have non rail-to-rail output swings. The lower voltage outputlevel is limited by the use of resistive loads. One can see that the maximum lowervoltage level is:

Vout,low = VDD − RISS, (21)

where VDD is the supply voltage, R is the resistive load and ISS is the current providedby the tail current source. This non-zero lower voltage level is also beneficial fromthe speed point of view as less time is required to reach a non-zero level from VDD

and vice versa. [4]Characterizing the speed of the CML latch is possible by calculating the RC-time

constant of the latch. The time constant is defined by gate and stray capacitancesand the load resistors. In other words, the dimensioning of the circuit is critical forachieving the desired speed. [4, 10]

In the designed multi-modulus frequency divider, the CML based circuits aredesigned without tail-current sources because of low supply voltage. A conventional

32

DP

DNQPQN

CKPCKN

Δt

Figure 21: Regeneration of signals in a CML latch, when the clock signal has switched.[4]

CML latch, such as the one in Figure 20, does not suit low supply voltage ICimplementations because of the stacked nature of transistors. By omitting the tailcurrent source completely the level of stacking is reduced. The designed CML latchis shown in Figure 22. [4].

VBIASP

DP

DN

CKP

CKN

QN

QP

Figure 22: Transistor level implementation of the CML D-latch. [10]

Resistors are seldom designed directly in IC implementations. By designing

33

the resistive loads with triode mode PMOS transistors, it is possible to introducesome tuning into the circuit. Regarding the tuning, the biasing is critical from thespeed perspective as the resistance will affect the RC-time constant and the Vout,low

which both affect speed of the latch. In the end the speed of the latch defines whatfrequencies it is possible for the latch to operate at. Higher frequencies are possibleto achieve with smaller resistive loads, but it limits the output swing of the latch.This non rail-to-rail swing might be an issue in the succeeding circuits such as thephase interpolator or the Σ∆-modulator.

4.3.3 Current-Mode Logic XNOR

An XNOR-gate is used in this design to enable the desired division ratios. CML baseddesigns are used throughout the divider in order to guarantee proper interoperationof the individual circuits forming the divider. This is achieved by biasing the PMOStransistors using the same voltage and using equally sized transistors at the sametransistor stack level for the respective CML circuits of the divider.

XP

XN

YP YN

XP

OutN OutP

Vbiasp

Figure 23: Schematic of XOR/XNOR-gate used in the control logic for the dual-modulus divider. [4]

The CML based XNOR gate is shown in Figure 23. The XNOR gate is used forinversion and division by 3. The inversion capabilities can be confirmed by analyzingwhat happens when YP is fixed to LOW and YN to HIGH. When XP is then setto HIGH, the positive output OutP will be pulled to ground which is an indicationthat an inversion has occurred. Meanwhile the negative output OutN will be pulledto the supply voltage because of the differential nature of the circuit.

34

The operation of this circuit as a XNOR gate can be confirmed by considering 4different states:

1. XP and YP are LOW, then OutN is pulled to LOW and thus OutP is HIGH

2. XP LOW and YP HIGH, then OutP is pulled to LOW

3. XP HIGH and YP LOW, then OutP is pulled to LOW

4. XP and YP HIGH, then OutN is pulled LOW and thus OutP is HIGH

These four situations correspond to the truth table of XNOR shown in Table 4.From these states it is possible to deduce that the XNOR gate could act as a XORgate if the outputs are reversed in the differential design. The difference that thiswould have on the MMD is that the divide-by-3 operation will achieve different dutycycles of 66.7% versus 33.3% when using XOR or XNOR respectively.

4.3.4 Current-Mode Logic AND

The DivCtrl circuit consists of two AND gates that are based on the current-steeringprinciple of CML. The current is steered with the the control signals that enable twodifferent modes in this circuit. These modes are either the forwarding of its inputsor forcing a 0 at the positive output of this differential design. The design of theAND gate is shown in Figure 24

VBIASP

AP

AN

CTRLP

CTRLN

QN

QP

CTRLP

Figure 24: Schematic of an AND gate used in the control of the division ratio in themulti-modulus frequency divider.

One can see that by having CTRLP as 0, the circuit will force a 0 at the outputwhich enables the XNOR gate to act as an inverter. On the other hand when CTRLP

35

is set to 1, the circuit will pass its inputs directly into the output in accordance to adifferential pair. This is the operation of an AND gate and the logic provided bythis gate is sufficient to enable different division modes of the designed MMD.

The biasing of the PMOS transistor is used throughout the CML based circuitsin the multi-modulus frequency divider to guarantee equal output voltage swingsand level. The transistors are also matched in size along with other CML circuitsused in the MMD.

4.4 Design of Sigma-Delta -modulator Based Control Cir-cuitry

Σ∆-modulator based control circuitry is a core part of the proper operation of thefractional frequency divider. The circuit is responsible for controlling the division ra-tios of the MMD and providing proper control of phase interpolator that is responsibleof the phase offset compensation.

The designed digital control circuit has three functionalities: division modeselection of 2/3 or 3/4 of the MMD, toggling of the division ratio in a selecteddivision ratio pair and the control of the phase offset compensation. These controlsare synchronized to the output of the MMD which ensures that proper number ofN and N+1 division ratio pulses are chosen for a specific time-average fractionalfrequency before introducing any change. The design is illustrated in Figure 25.

13 8z-1

FCW1

13

eq

1

2

ctrl<1:0>

eq,t = sel<7:0>

clkΣΔ

ICW CtrlLogic

c

0 1ICW

0 1ICW

c

ctrl<1> ctrl<0>

HIGH HIGH

Figure 25: Functional block diagram of a digital Σ∆-based control circuit.

The main functionality of the control circuit is based on the 1st order Σ∆-modulator. A 1st order Σ∆-modulator can be thought of as an accumulator which

36

can be designed with a register and an adder. The functionality of the accumulatoris to produce a control bit for the MMD when the required number of pulses at theoutput of the MMD has occurred to warrant a change. The counting of the pulsesrequires memory and summation and in terms of electrical circuits, an adder and aregister.

The required number of pulses is defined by the fractional control word (FCW)which corresponds to α from Equation 16. In other words, the FCW is equal to thedesired fractional part of the division ratio.

The control bit for toggling the division ratio of the MMD is generated when thesummation of the FCW and the residue present from earlier summations exceedsone. The earlier non exceeding parts of the summations are stored as residue eq inthe register for future summations. The adder, register and their connections areillustrated in the lower half of the functional block diagram of the control circuit inFigure 25. The register is modeled as a delay element that will update its outputwhen a falling clock edge from the MMD output is detected. The triggering by thefalling edge is required to remove the possibility of the MMD being stuck in anerroneous state. [3]

Besides the control of the MMD, the digital control circuit will also provide therequired control for the phase offset compensating circuit. This control is definedby the residue of the accumulator which corresponds to the phase offset accrued bythe Σ∆-modulator. The residue can be extracted from the register that stores theresidues after each pulse of the MMD output.

In this design, there are two input control words and two output control signalsfor the MMD and phase interpolator. The first input control word is the IntegerControl Word (ICW) that is a 1-bit control word responsible for choosing eitherdivision ratio pairs of 2/3 or 3/4 of the MMD. The second control word is the FCWthat is used to determines the desired fractional part of the division ratio. It is a 13bits wide and is intentionally chosen to be wide as it is responsible for the achievabletime-average fractional frequency resolution.

The first output control signal is the control for the MMD. This is a 2-bit controlsignal that is generated by combining the carry bit of the accumulator and the ICW.Depending on the ICW either the Least Significant Bit or the Most Significant Bitof the 2-bit control signal of the MMD will be set to 1 for enabling division by 2/3or 3/4 respectively. The remaining bit will be the carry bit that is either 0 or 1depending on the state of the accumulator. For the division by 3/4, the carry bitis inverted as division by 3 will occur with control word 11bin which should be thedefault division ratio in the div-3/4 mode. The control sequences corresponding todifferent division ratios are collected in the Table 6 and can be achieved by usingtwo multiplexers and an inverter as is shown in the right upper corner of Figure 25.

The second output control signal is an 8-bit control signal for the phase interpolatorresponsible for phase offset compensation. The 8-bit control signal is a truncatedversion of the 13-bit residue present in the accumulator. Be reminded that the residueis directly correlated with the phase offset introduced by the Σ∆-modulator and thuscan be used to control the phase offset compensation.

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4.5 Design of Phase InterpolatorA phase interpolator is a circuit that can provide specific phases that lie betweentwo original signals with phase offsets. The proper selection of a phase can be usedno nullify the deterministic jitter produced by the Σ∆-modulator truncation error.A phase interpolator can produce relative phase offsets, which is to say that it cangenerate phase offsets between successive signal pulses.

In this design, an 8 stage phase interpolator is used for compensating the phaseoffset/deterministic jitters presented by the Σ∆-modulation of the multi-modulusdivider (MMD). The design consists of a 3-phase generator, phase selectors andindividual phase interpolation stages. The design is illustrated in Figure 26.

3-PhaseGenerator

fin/Nfrac=MMDout

fin

PhaseSelect

Phase SelectForwarder 1st

sel<7:0>

A8AB8B8

BufA8

A7B7 PI

StagePI

Stage

A0=fin/Nfrac

B0DTC=constant

sel7<7:0>

A6B6

sel6<7:0>

PI unit

PI unit

PI unit

A7

B7

AB

Ad

Bd

PhaseSelect

sel7<6:0>

sel6<7:0>

Phase SelectForwarder

sel7<7>

A6

B6

sel8<7>

Figure 26: Block diagram of the designed phase interpolator.

The core idea behind the designed PI is the repetitive use of interpolation andforwarding of the interpolated signal for succeeding PI stages. The first step in a PIstage is to interpolate a new signal from two existing signals. The new interpolatedsignal has equal phase offsets to the original signals which can be thought of as theinterpolated signal lying in the middle of the two original signals in time-domain.The next step after interpolation is to choose a pair of signals consisting of oneoriginal and one interpolated signal and then forwarding them to the next PI stagewhere the process is repeated. By selecting the interpolated signal and one originalsignal, the phase offset is halved at every single PI stage. In other words the phaseresolution at the output improves by a factor of two for each additional PI stage.

In an 8 stage phase interpolator the achievable resolution is 28 = 256 phases. Intheory this translates into an achievable phase resolution of:

θ

28 ≈ 0.0039 θ, (22)

where θ corresponds to the initial phase offset between the input signals to the phaseinterpolator. θ also determines the output range of the phase interpolator as it ispossible to essentially bypass all the PI stages by selecting either one of the twooriginal signals from the first stage down to the last stage. Thus the selection of θ

38

is critical for ensuring proper operation of the phase interpolator for compensatingphase offsets from the Σ∆-modulator.

4.5.1 Three Phase Generation

The initial phase offset θ has to be precisely generated in order for the phaseinterpolator to work properly as a phase offset compensator. This initial phase offsetshould correspond to the maximum deviation generated by the Σ∆-modulator whichin this case is one period of the pre-division clock signal Tin.

The phase generator is triggered by the pre-division clock signal in order togenerate phases of the MMD output that are correlated to the Tin. In the first stageof the PI, three phases are generated that are 0.5Tin apart from each other. Thesesignals are illustrated in Figure 27 together with an ideal signal waveform that hasproper instantaneous phase.

CLKin

MMDout,A

MMDout,ideal

-0.4Tin -0.8Tin -0.2Tin -0.6Tin 0Tin0Tin -0.4Tin

Nfrac=12/5=2.4

MMDout,AB

MMDout,B

Tin

Figure 27: 3-phase generator output signals and the ideal signal.

The three phases can be generated with the use of three latches that are connectedin succession similarly to a flip-flop structure. These phase offsets are produced byclocking with the original pre-division clock signal as shown in Figure 28. A 0.5Tin

resolution can be achieved by inverting one of the clock signal inputs as shown bythe latch in the middle of Figure 28.

From the three signals, two of them that are 0.5Tin apart from each other areselected for further phase interpolation stages for improving the resolution. Tosummarize, with the use of a 3-phase generator that is controlled by the pre-divisionclock, the desired PI output range of 1Tin has been set and the phase resolution canbe improved by introducing additional interpolation stages.

At this stage, the latches are still designed using current-mode-logic (CML) whichmeans that the single ended voltages do not swing from rail-to-rail. The rest ofthe phase interpolator is designed using standard CMOS logic which has rail-to-railsignal swings. The conversion from CML to CMOS is performed with a differential to

39

fin/Nfrac=MMDout

3-Phase Generation

Latch

fin

A

AB

B

Latch

Latch

Figure 28: Three phase generation of the multi-modulus frequency divider usinglatches.

single-ended conversion which achieves a rail-to-rail swing. This single-ended signalis then converted back into a differential signal for further processing in the phaseinterpolator.

A typical CMOS inverter based buffering does not provide sufficient bufferingbetween CML and CMOS logic at the interface between MMD and phase interpolator.The limited output swing of the CML is the main culprit and thus an additionalcircuit for conversion is required.

A differential pair based circuit can be used to reconstruct a single-ended rail-to-rail version of the output of the divider if such signal is desired and then later onregenerate it as differential for phase interpolator.

4.5.2 Phase Interpolation Stage

A phase interpolation stage consists of three distinct blocks that serve differentfunctions. These functions are related to the interpolation, selection of the phase forsuccessive stages and forwarding the control signal of the digital control circuitry forselecting proper phases. The block diagram of a PI stage is shown in Figure 29.

The phase interpolation block of a PI stage consists of three individual phaseinterpolation units. These PI units are fed with different combinations of the twoinput signals denoted as A and B shown in the left of Figure 29. These combinationsare AA, AB and BB. The combinations with the same signal do not experienceany interpolation but will instead be delayed by the static delay present in the PIunits. Only the AB combination will experience interpolation.

40

PI unit

PI unit

PI unit

A

B

0

1

0

1

selA

selB

AB

Out1

Out2

DFF

AB

sel<7> selA

DFF

Bd

selB

Phase interpolation Phase select

Phase SelectForwarder

sel<6:0> sel_out<7:0>

Out1 Buf

Ad

Bd

Figure 29: Block diagram of a phase interpolation stage.

During proper operation the interpolated AB signal will have equal phase offsetto the delayed A and B signals. In other words a new phase has been generatedby interpolating the two signals. The original signals, the delayed signals and theinterpolated signal are illustrated in Figure 30.

For the proper interpolation, it is necessary to emphasize the importance of usingthe PI units even for the original A and B signals. The interpolated AB signal is

41

A

B

AB

Ad

Bd

Figure 30: Phase interpolation concept using an interpolator with inherent delay.The result is a relative phase interpolation between respective PI Unit outputs.

only an interpolation of the delayed versions of the original signals Ad and Bd andnot the non delayed ones as can be confirmed from Figure 30. The absolute delay orthe static delay present in the path of a signal is not relevant during an interpolationstep, the more important part is the relative delay between the signals at the outputof the PI unit.

Now that three signals are presented by the phase interpolation block, the nextstep is the selection of only two of them for the next PI stage. The selection isperformed by choosing one of the original delayed signals and the interpolated signal.The phase offset between the signals can be halved in every additional PI stage byforwarding the pairs in this way.

The phase selection is performed by a pair of multiplexers that are controlled bya single select bit denoted as sel<7> in Figure 29. The mux inputs are routed in amanner that only Ad and AB or AB and Bd are forwarded to the next PI stage forthe reasons described earlier.

Timing is critical for properly selecting the desired phases. Regarding the timingof selecting proper phase in the muxes, the trigger signal for the flip-flops to passthe select signal to the muxes is given by the falling edge of the lagging signal in theinterpolator. These trigger signals are AB in the case of choosing between A andAB, and B in the case of AB and B. The corresponding select signals are shown asselA and selB that are triggered by the respective lagging signals in the flip-flops.

The third and last functional block of a PI stage is the Phase Select Forwarder.The purpose of this circuit is to pass the control signal sel<7:0> to the succeeding

42

stages while retaining proper timing. Be reminded that an 8 stage phase interpolatorrequires an 8-bit control word for determining which phase to produce at the outputof the phase interpolator for cancelling the deterministic jitter of Σ∆-modulator.

During each PI stage, the Most Significant Bit (MSB) sel<7> of the controlword is used to select the desired phases for the succeeding PI stages. Because onlythe MSB is used in a single stage, the control word has to be shifted by 1 bit intothe direction of the MSB in each of the PI stages. This is accomplished by thePhase Select Forwarder that only receives sel<6:0> of the earlier PI stage and shiftsthem to sel_out<7:0> for the next stage to use the MSB. The last bit in the newsel_out<0> is set to 0 as it is irrelevant.

This approach has been taken because of the ease of layouting. Otherwirseeach successive stage would have a different select signal clocking scheme. It is acompromise between layout, power consumption and design of dedicated sel forwardersfor each additional stage.

In order to retain proper timing and having the sel_out<7:0> signal ready for thenext PI stage, a synchronization signal is required. Be reminded that the selectionsignal for the muxes are triggered by the falling edge of the lagging signal of theinterpolation results. The Phase Select Forwarder is triggered by the rising edge ofthe leading signal of the MUX outputs, the Out1 signal as can be seen from Figure29. This ensures that the sel_out<7:0> signals experience similar delay to the phaseinterpolator itself at each PI stage and correct sel<7> signal is used to choose thephases at each stage.

In order to guarantee proper timing, the Phase Select Forwarder has to forwardthe select signal faster than the inherent delay of a PI Unit minus the setup timerequired for the flip-flop used to synchronize the select bit for the muxes.

The phase interpolator stage is designed with cascading in mind. With this designit is possible to chain individual PI stages for achieving the desired phase resolution.The only limitation in this case is the practical benefit of having a higher resolutionwith additional stages and then the achievable linearity of the cascaded circuit. Thelinearity limits the number of stages that can be used and the range of initial phaseoffset θ that determines the time-domain range of the output phases.

4.5.3 Phase Interpolator Unit

The core circuitry responsible for achieving phase interpolation is shown in Figure 31.The circuit consists of a phase interpolator circuit and a Schmitt trigger. The purposeof these two circuits is to do the phase interpolation and then signal restoration fora proper interpolation result.

The operation of these two circuits starts by considering how signals A and Baffect the output of each circuit. A has to always be the leading signal in order forthe circuit in question to operate as desired. Assume that B is grounded and a risingedge of signal A arrives at the phase interpolator input terminals. Because of the useof NMOS transistors in the bottom of the circuit, they will pull the output towardsground slowly because only 2 out of the 4 NMOS transistors are conducting. Nowafter some time corresponding to the phase offset of A and B has occurred, a rising

43

AB

A

B

A

A

Schmitt TriggerPhase interpolator

cap_C<2:0> cap_F<1:0>

ABtemp

Figure 31: Transistor level implementation of a phase interpolation circuit andSchmitt trigger.

edge also arrives at the B inputs. Now 4 of the NMOS transistors are conductingand the output node is pulled towards ground at twice the speed compared to only 2NMOS transistors.

Similarly, the inverse will occur when a falling edge arrives and the output isslowly pulled toward the supply voltage and faster after the phase offset time haspassed. The signal waveforms corresponding to this are illustrated in Figure 32. Thefigure also illustrates the situation where the same signal appears at both of theterminals A and B. These are denoted as Ad,temp and Bd,temp and in essence onlyexperience a critical static delay in the interpolator.

Notice from Figure 32, that the output of the phase interpolator circuit ABtemp

shows a waveform that is jagged and inverted when compared to the input signals.These are not desired features and thus a Schmitt trigger is used to restore the signaland produce a proper interpolation result.

The signal is restored using a Schmitt trigger because it can provide inversion andhas thresholds before any change at the output will occur, also known as hysteresis.The inversion and thresholds take care of the uneven rise and fall times of the signalcaused by the interpolating circuit.

From figures 32 and 33, it can be seen that the rise and fall times at the interme-diate node ABtemp between the phase interpolator and Schmitt trigger are criticalfor proper operation. The rise and fall times are critical because the low and highthreshold voltages of the Schmitt trigger can’t be changed after implementation.

44

A

B

ABtemp

Bd,temp

Ad,temp

i

Figure 32: Phase interpolation with static delay present.

Vth,highVth,lowAd,temp,ABtemp,Bd,temp

Ad,AB,Bd

Figure 33: Phase interpolation with static delay present and the Schmitt triggerthresholds.

To ensure that the interpolation works properly, the threshold values have to bechosen in such a way that the interpolation result ABtemp passes the thresholds afterboth A and B signals have arrived at the inputs. In other words, the Schmitt triggerthresholds have to be at a voltage where the output signal has not reached beforethe time between the phase offsets between the two input signals has occurred. Thethreshold should also be less than the time of the positive pulse of the duty cycle toensure that the signal has reached maximum and minimum values beforer anotherchange occurs.

In order guarantee that interpolation occurs, the rise and fall times have to be

45

adjustable for the signals at the intermediate node between the interpolator andSchmitt trigger. This adjustment can be achieved by controllable capacitor bankthat increase both rising and falling times when enabled.

In this design, a 5-bit capacitor bank is used to tune the required rise and falltimes to enable proper interpolation. 3 out of the 5 bits are used for coarse controland the remaining 2 are used for fine control. The capacitor bank can only be used toincrease the rising and falling times which means that it can enable the interpolationof lower frequencies that have longer absolute phase offsets than high frequency ones.

Be reminded that the initial phase offset are generated by the 3-phase generatorthat is triggered by the pre-division clock signal. In other words, the trigger pointof the interpolator is only sensitive to the frequency of pre-division clock signal asthe phases are generated in respect to that. This indicates that the capacitor banksettings have to be tuned according to the pre-division clock signal. Specific capacitorbank settings for a frequency can be used for range of pre-division clock frequencies.The main point is that the thresholds of the Schmitt trigger are not passed beforethe arrival of the lagging signal.

Vth,highVth,lowAd,temp,ABtemp,Bd,temp

Ad,AB,Bd

Figure 34: Phase interpolation with too low capacitance for the given thresholdvoltages results in incorrect interpolation.

The supported frequency range of interpolation is determined by rise and falltimes of the signals in an individual phase interpolation stage. The wider the tuningrange of this delay, the larger range of frequencies can be supported. Maximumsupported frequency is determined by the minimum delay of a stage. This is becauseof the short period of a high frequency signals. The lower frequency tuning rangecan be increased by introducing varactors that will increase the rise and fall times.This is because during each PI stage, the phase offset is halved and for a highfrequency signal this phase offset is too small in the time-domain for enabling properinterpolation.

Capacitor bank settings are tunable along the three different paths of Ad, Bd andAB. In theory each of the capacitor bank settings for a given phase interpolatorstage should be equal for all pi units. However, in an actual layout the parasitics andunequal loading of nodes will result in some discrepancy which results in different

46

capacitor settings for a given phase interpolator unit in a single PI stage.In case too much capacitance is used, the duty cycle of the interpolation signal

will distort or the thresholds are not reached and the signal does not propagate. Onthe other hand, if too little capacitance is present, the interpolation result will nothave equal phase offsets to the delayed versions of the original signals. This situationof having too low capacitance or fast rise and fall times is shown in Figure 34.

Schmitt trigger was chosen over a conventional inverter because of the thresholds.The thresholds give more leeway for the capacitors settings. In the case that aninverter is used, the output would change when the output reaches the middle pointof the supply voltage. In this case the rise time for the signal has to be preciselythe time equivalent to the phase offset between the two input signals. This kind ofaccuracy would in practice be difficult to attain. In a practical situation, the signalsdo not rise and fall as linearity as depicted in figures 33 and 34 but will insteadtaper down as the signal approaches the supply and ground voltages. This in turnintroduces even more challenges for selecting the proper rise and fall times such thatthe threshold is reached at the correct time-instance for phase interpolation in thecase that the conventional inverter was chosen over the Schmitt triggers.

Another point to take into account in the interpolator is the effect of duty cycleon the end result of the output signal. Phase interpolation for division ratios from 3to 4 have to have their inputs inverted in order to have a consistent duty-cycle. Thereason for this inversion is that for division by 3, the 33.3% duty cycle correspondsto a time period of 1Tin time period being in the HIGH state whereas the 50%duty-cycle of the division by 4 corresponds to 2Tin. In order to have consistentduty-cycles for the phase interpolation results, the 33.3% duty cycles have to beconverted to 66.7% which in time-domain corresponds to 2Tin time period of thesignal being in the HIGH state.

47

5 Layout and Simulation of the Fractional Fre-quency Divider

The designed fractional frequency divider consists of three distinct functional blocks.These blocks are the multi-modulus integer divider, the Σ∆-digital control circuitand the phase interpolator. The performance and behavior of these individual blocksare confirmed by performing circuit and logic simulations on a parasitic extractedlayout.

In all integrated circuits, the layout affects the performance of the circuit. Thedegradation of performance resulting from poor layouting are noticeable in designsthat employ differential signaling and rely on relative propagation delays. In otherwords, layout drawing is critical from the performance point of view of analog circuits.

The analog circuits consisting of the MMD and PI are simulated with ELDOcircuit simulator using Spice-netlists generated by Cadence Virtuoso. The generatednetlists take into account the post-layout parasitics which will degrade the overallperformance of the circuit.

The system level performance of the fractional frequency divider is evaluatedwith the help of mixed-mode simulations in Questa ADMS. In the mixed modesimulations, the signals in the interface between the analog and digital parts areconverted depending on a user-defined voltage threshold. The most importantmetrics that are attainable from the mixed-mode simulations are purity of the outputspectrum, operating frequency range and power consumption.

5.1 Layout of the Designed Fractional Frequency DividerThe layouts of the analog parts of the fractional frequency divider are drawn usingCadence Virtuoso. The final layout of the design is shown in Figure 35. The area ofthe layout is approximately 630 µm × 270 µm, and it is mostly formed by the phaseinterpolator.

In Figure 35, four different colors are used to highlight different parts of theFFD. The red rectangle highlights the multi-modulus integer divider and the 3-phasegenerator of the phase interpolator, the pink color represents the remaining partsof the first stage of the phase interpolator and the blue color is reserved for theremaining seven stages of the PI. The empty space in the upper-left corner markedby the black rectangle is reserved for the Σ∆-digital control circuit.

From Figure 35, it can be confirmed that most of the area is occupied by thedifferential PI. The PI occupies almost 90% of the drawn layout which leaves theremaining 10% for the MMD and Σ∆-digital control circuit. The layout constitutesmostly of the PI and thus effort is placed on drawing it.

The PI is designed in a way that individual PI stages can be chained to obtain thedesired phase resolution. As a result, the layout drawing procedure can be reducedfrom manually drawing the whole PI to only drawing a single PI stage. These PIstages can then be placed next to each other for achieving the chaining which reducesthe workload required for drawing the PI.

48

Figure 35: Final layout of the designed fractional frequency divider without the digitalpart. The red rectangle represents the multi-modulus integer divider and 3-phasegenerator, the pink color the first phase select and phase select forwarder of the phaseinterpolator, and the blue rectangles form the remaining 7 phase interpolator stages.The width of the layout is approximately 630 µm while the height is 270 µm.

Designing circuits with chaining in mind will inevitably reduce the workload oflayouting. However, chaining is not without its faults. One of the issues with thechaining of a drawn layout is that chaining is usually performed in a single axis whichmeans that the dimension in the same axis will grow in a different rate comparedto the axis that is perpendicular. In the case that a square layout is desired, thediscrepancy in dimensions resulting from chaining can be compensated by drawingthe width and height of a single stage in proportion to the total number of chainedstages. In this thesis the fractional frequency divider acts as a part of a larger chipand there is no desire to have a precisely square layout for the FFD.

Second issue with chaining is that the circuit will more likely include redundantcomponents that occupy layout area. In the case of the PI, the redundant componentsare in the Phase Select Forwarders shown in Figure 29. The redundant componentscome from part that generates the extra unused select bits for each additional PIstage. As a conclusion, the decision to use chaining can be though of as a compromisebetween the workload required for drawing the layout and optimal layout withoutredundant components.

The PI occupies most of the area in the layout and thus the minimization ofthe area occupied by a single PI stage is a priority. The minimization of the area isencouraged as the manufacturing cost of an integrated circuit is highly tied to thesize of the layout. Minimization of the area is desired but it has to be performed ina way that ensures the proper operation of the circuit.

49

PI unit

PI unit

PI unit

0

1

0

1

Phase selectPreceding Stage

0

1

0

1

Phase Interpolator Stage

Figure 36: The critical paths in the phase interpolator lie between the multiplexersand phase interpolation units. Various buffers, which are not shown, are placed inthe shown paths and also contribute to propagation delay.

The PI stage has multiple paths that require precision from the layout and routing.Precision is required because of propagation delays that are present in an actuallayout compared to an ideal schematic. Careful thought has to be placed on therouting whenever precise relative delays between different nodes of the circuit areexpected from the layout. In addition to paying attention to the routing, capacitivetuning of the critical paths can be introduced to alleviate the precision required fromthe layout.

The operating principle of the PI is based on producing relative delays betweenseparate nodes of the circuit. In other words, there are critical paths in the PIthat should have equal delays. In Figure 36, the critical paths of the PI stage arehighlighted from the perspective of proper timing. In the figure, each path thatshould introduce equal delay have the same color.

The first step in ensuring that different routes have the same propagation delayis to use equal trace widths and lengths between different nodes. One way to ensurethat the paths have equal lengths is by measuring the distance between two pointsand choosing the middle point as a common node. This common node can then befurther used as a starting point for more routing. Figure 36 illustrates the method byhaving the same colors represent equal lengths in the layout. This technique requiresthe use of multiple metal layers in order for the routing to occupy minimal layoutarea.

In the case that the circuit is manufactured, usually even equal trace widthsand lengths is not enough to guarantee perfectly equal propagation delays at thecritical paths of the IC. The precision of the manufacturing process and the distribu-tion of parasitics will affect the degradation of performance. The compensation of

50

Figure 37: One of the initial layouts of the PI stage for minimizing total layout areaoccupied by the complete PI. The highlighted boxes are PI unit, multiplexers and thephase select forwarder. This layout has difficulties for achieving proper trace lengthsand thus delays in the critical paths. The width of the layout is approximately 59 µmand the height is 284 µm.

51

Figure 38: Final layout of the PI stage. The highlighted boxes are PI unit, multiplexersand the phase select forwarder. This layout has more symmetry for achieving betterideal trace lengths. Width of the layout is approximately 70 µm while the height isapproximately 243 µm.

52

manufacturing related propagation delays is out of the scope of this thesis.The final drawn layout of the phase interpolator is a result of optimizing numerous

suboptimal layouts. Figures 37 and 38 show two different versions of layouts for thePI stage. In the figures, the red rectangles represent the PI units, the pink rectanglesare the multiplexers and the blue rectangle is the phase select forwarder that arepresented in Figure 29.

Occasionally the decision to go towards minimal layout will create some difficultiesfor achieving the desired performance. Figure 37 represents a situation whereminimization of the total area of PI has led to a layout which has difficulties forachieving equal delays across the critical paths. The difficulties stem from the lack ofsymmetry between the functional blocks that have critical paths between them. Inthis case, the PI units and the multiplexers do not have any symmetry lines betweenthem.

By introducing symmetry lines between critical functional blocks, it is morestraightforward to achieve equal length traces and in turn delays. In the Figure38, better symmetry has been achieved with the expense of slightly larger layout.By choosing the symmetry point to align both the PI units and the multiplexers,it is easier to achieved more equal propagation delays in the critical paths. Layoutdrawing can be an iterative process and thus the final layout for an individual PIstage is the one shown in the Figure 38 that has more symmetry. The area of thelayout is approximately 70 µm × 243 µm.

5.2 Simulation of Multi-Modulus Integer DividerThe multi-modulus integer divider (MMD) has two critical functionalities that areexpected of it in order for it to operate as a part of the designed fractional frequencydivider (FFD). The first critical function is the integer division of an input clocksignal that is generated by a separate frequency synthesizer. The second criticalfunctionality is the seamless transition of different division ratios. The functionalitiesand performance are confirmed by performing transient simulations which are usedto analyse the time-domain operation of the circuit.

The simulations are performed using ELDO circuit simulator with a post-layoutnetlist with parasitics and a constant CML bias voltage. The circuit is biased to avoltage of 280 mV which sets the PMOS transistors of the CML circuits into a statethat can operate at least in the desired frequency range of 6 GHz to 16 GHz. Properbiasing of the PMOS transistors affects the maximum dynamic frequency range ofdivision as biasing has an effect on the propagation delays of the CML circuits.

The maximum frequency and seamless toggling of division ratios are confirmedby two transient simulations with an input signal with a frequency of 15 GHz andfractional division ratios of 2.5 and 3.5. Fractional divisions by .5 are chosen as theyprovide the division scheme which include the most number of toggles of the divisionratio per input period. In other words, if the circuit is capable of dividing by .5 it isalso capable of dividing by other fractional division ratios in this case.

In Figure 39, an ideal input signal with a frequency of 16 GHz is divided by 2.5and 3.5 in the topmost and middle waveforms respectively. These two waveforms

53

show the non rail-to-rail differential single-ended swings of the CML latches. Thewaveforms also show that the designed divider is capable of operating at 16 GHzwith all of the desired integer division ratios of two, three and four and with theseamless toggling capability of the division ratios.

0 0.5 1 1.5 2 2.5

Time [ns]

0

0.5

1

Am

pli

tud

e [

V] MMD

out, N

frac=2.5

OUTn

OUTp

0 0.5 1 1.5 2 2.5

Time [ns]

0

0.5

1

Am

pli

tud

e [

V] MMD

out, N

frac=3.5

OUTn

OUTp

0 0.5 1 1.5 2 2.5

Time [ns]

0

0.5

1

Am

pli

tud

e [

V] CLK

in, f=16 GHz

Figure 39: Multi-modulus divider single ended differential output waveforms withfractional division ratios of 2.5 and 3.5. The input clock frequency is 16 GHz.

5.3 Simulation of the Sigma-Delta Digital Control CircuitThe Σ∆-digital control circuit is responsible for generating the required divisioncontrol and phase selection signals for the MMD and phase interpolator respectively.The most important point in simulating this circuit is the proper behavioral operation.With proper operation, the correct control and phase select signals are generatedand forwarded to their designated locations at the correct time-instance.

The Σ∆ control circuit is simulated as an ideal digital circuit within a mixed modesimulation where the Σ∆ clock signal is generated by the multi-modulus integerdivider. The simulations are only performed for behavioral analysis which doesnot take into account possible timing related issues that could surface during thelayouting of the digital design. As long as the behavior of the designed circuit is thedesired one, speed related optimization can be performed by the synthesis tools andoptimization of the VHDL code and architecture.

In Figure 40, a clock signal of 9 GHz is divided by a fractional division ratioof 2.4 which results in a time-average frequency of 3.75 GHz. Even with 13 bits,this division ratio can only be approximated as 2+819/2048 which is approximately2.39999. This also limits the accuracy of the phase interpolator when observed overa longer time period.

54

0 0.5 1 1.5 2 2.5

Time [ns]

0

0.5

1

Am

plitu

de [

V] Singe ended differential CTRL<0>

CTRL<0>p

CTRL<0>n

0 0.5 1 1.5 2 2.5

Time [ns]

0

0.5

1

Am

plitu

de [

V] Singe ended differential CTRL<1>

CTRL<1>p

CTRL<1>n

0 0.5 1 1.5 2 2.5

Time [ns]

0

0.5

1

Am

plitu

de [

V] Sigma-Delta Clock

0 0.5 1 1.5 2 2.5

Time [ns]

0

0.5

1

Am

plitu

de [

V] MMD

out

Figure 40: Σ∆-modulator 2-bit control signal to multi-modulus divider, the Σ∆ clockand the MMD output signal with a fractional frequency of 3.75 GHz. Fin = 9 GHzwith Nfrac = 2.4.

The control circuit reacts to the falling edges of the Σ∆ clock which ensures thatno forbidden states are present during the toggling of division ratios of the MMDas mentioned in Section 4.3.1. The main point behind Figure 40 is that only one ofthe differential control signals is required to toggle between two unity step divisionratios of the MMD as is described in Section 4.3.1 and that it is produced at thecorrect time instance for enabling correct waveform at the MMD output without theMMD getting stuck in a forbidden state.

The correct operation of the Σ∆-digital control circuit is easier to evaluate fromthe MMD output signal instead of the Σ∆ clock. The reason for this is that the MMDoutput is affected by the change in division ratios sooner than the Σ∆ clock as thereis one input clock period difference between the two. This offset is a consequence ofthe flip-flop separating the two signals as can be seen from Figure 18.

In order to confirm that the digital control circuit operates as expected a smallanalysis on the effect of the CTRL<1> on the MMD output is in place. Wheneverthe positive CTRL<1> is at logic LOW the MMD divides by 2, whereas it divides by3 when the control signal is at logic HIGH. The effect of the change in the divisioncontrol signal and in turn the division ratio in the MMD output can be seen fromthe lowest waveform in Figure 40 as an additional low state corresponding to one

55

input clock period whenever the positive CTRL<1> is set to 1. This additional lowstate corresponds to enabling division by 3 in the time-domain signal. Therefore, itcan be confirmed that the control signals for producing the desired division ratiosare generated at the correct time instance and the Σ∆-digital control circuit behavesas designed.

5.4 Simulation of Phase InterpolatorThe phase interpolator (PI) is designed with the core idea of compensating thedeterministic jitter produced by the Σ∆-digital control circuit and the multi-modulusinteger divider. In other words, the time-domain output signal of the PI should haveproper instantaneous phase and additionally a consistent duty cycle. The capabilityof the PI for performing this function can be evaluated by determining the accuracyof the delays generated by choosing different output phases of the PI. This accuracycan be considered as the linearity of PI which can be defined in multiple ways. Oneof these ways is the comparison of relative delays between consecutive output phasesof the PI and comparing them to the ideal offset between two phases. The linearitythat is determined in this way is known as Differential Nonlinearity (DNL). Optimallinearity in this case is achieved by having equal delays between each consecutivephase which correspond to the desired resolution of the phase interpolator.

The DNL is more specifically defined as:

DNL(i) = td,P I(i) − td,P I(i − 1)Tin/(28 − 1) − 1, (23)

where i is the index corresponding to a specific phase at the output of PI, Tin isthe period of the pre-division clock signal and td,P I(i) is the delay of the phaseinterpolator for a phase with index i. DNL is frequency dependent as the inputfrequency determines the time-domain range that has to be covered by the phaseinterpolator. An alternative parameter to DNL for evaluating linearity is the IntegralNonlinearity (INL) which determines the time-delays generated by the PI in respectto ideal delays that would be expected for a given resolution of a PI.

INL can in this case be defined as:

INL(i) = td,P I(i)Tin

− i

28 , (24)

where i is the index corresponding to a specific phase at the output of PI and td,pi(i) isthe delay corresponding to the index i phase and Tin is the period of the pre-divisionclock signal.

The PI produces 256 phases with relative delays between them. As a result oneof the phases has to be chosen as the reference which in the simulations is indexedas phase 0. The delays produced by choosing a specific phase of the PI are used tocompensate the deterministic jitter which is the residue of the Σ∆-digital controlcircuit and MMD. This residue is also the phase select signal for the PI which enablesthe proper phase compensation.

56

In order to evaluate the linearity of the PI, static settings for phase selectionare produced directly from ELDO and not from the Σ∆-digital control circuit. Therange of delay that is to be compensated is one period of the pre-division clock signalTin as is mentioned in Section 3.3.3. The delays produced by the PI are normalizedin respect to this period in order to better evaluate the feasibility of the PI forcompensating the deterministic jitter.

The input signals for the phase interpolator are generated using ELDO and theyhave different duty cycles depending on the division ratio of interest in the simulation.Duty cycles are chosen to be 50% for division ratios of two and four and 33.3% fordivision by 3. These duty-cycles are chosen based on what the multi-modulus integerdivider would generate. Division by 3 will generate a waveform with 33.3% and66.7% in div-2/3 and div-3/4 modes respectively. In terms of linearity, no significantchange is noticeable for these two duty cycles of division by 3 and thus only 33.3%duty-cycles are used for simulation with division by 3.

Various post-layout simulations are performed in respect to division ratios andpre-division clock frequency. The pre-division clock frequency determines the settingsfor the capacitor banks which enable the interpolation of range of frequencies. Thedivision ratio should not affect the used capacitor bank settings as these settings aredetermined by the pre-division clock frequency. Because the interpolation settingsare pre-division clock frequency dependent, various settings for the delay controllingcapacitor banks have to be found for optimal linearity. The optimal settings for aparticular pre-division frequency are affected also by the post-layout parasitics andthe actual drawn layout which introduce additional capacitance and delay becauseof imperfect symmetrical routing and loading of nodes.

The linearity of the PI is measured by extracting the time instance when theoutput differential signal rises above the middle point of 0 V for a specific phase aftera trigger point in time. The trigger point is chosen in such a way that the start-uptransients have disappeared from the output. Linearity can defined in various waysand thus a number of different figures are generated. Linearity can be estimated bycomparing time instances between different phases and these time instances can beplotted into a figure in regards to normalized time-delay and phase index such asin figures 41, 42 and 43. The DNL for different frequencies and division ratios areplotted in figures 44, 45 and 46, and the INL performances are in figures 47, 48 and49. These figures demonstrate the linearity of the PI with various pre-division inputfrequencies and division ratios.

From figures 41, 42 and 43, the most important point is that the range of delaythat the PI is able to cover is sufficient. In these figures, the delays are normalized inrespect to one period of the pre-division frequency which is the range of deterministicjitter produced by the Σ∆-digital control circuit. It can be seen that in the figures41, 43 and 42, the relative delays cover this required range with acceptable linearity.By comparing these figures with different division ratios and duty cycles at differentfrequencies, there is a clear trend that linearity starts deteriorating at higher pre-division clock frequencies. This effect can also be confirmed from the DNL andINL figures. The deterioration is caused by the ever smaller time-domain differencebetween successive pulses as the frequency increases. This affects the DNL and

57

0 50 100 150 200 250

Phase Index

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Dela

y/in

pu

t p

eri

od

PI normalized linearity for div 2 with duty cycle of 50%

6 GHz

9 GHz

12 GHz

Figure 41: Phase interpolator normalized post-layout linearity for division by 2 withvarying input frequencies with a duty cycle of 50%.

0 50 100 150 200 250

Phase Index

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Dela

y/in

pu

t p

eri

od

PI normalized linearity for div 3 with duty cycle of 33%

9 GHz

12 GHz

15 GHz

Figure 42: Phase interpolator post-layout normalized linearity for division ratio 3 atvarious input frequencies with duty cycle of 33%.

58

0 50 100 150 200 250

Phase Index

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Dela

y/in

pu

t p

eri

od

PI normalized linearity for div 4 with duty cycle of 50%

9 GHz

12 GHz

15 GHz

Figure 43: Phase interpolator normalized post-layout linearity for division ratio of 4with various input frequencies with duty cycle of 50%.

0 50 100 150 200 250

Differential Phase Index

-3

-2

-1

0

1

2

3

DN

L [

LS

B]

PI DNL for div 2 with duty cycle of 50% and various pre-division input frequencies

6 GHz

0 50 100 150 200 250

Differential Phase Index

-3

-2

-1

0

1

2

3

DN

L [

LS

B]

9 GHz

0 50 100 150 200 250

Differential Phase Index

-3

-2

-1

0

1

2

3

DN

L [

LS

B]

12 GHz

Figure 44: Phase interpolator post-layout normalized Differential Nonlinearity fordivision by 2 with varying input frequencies with a duty cycle of 50%.

59

0 50 100 150 200 250

Differential Phase Index

-3

-2

-1

0

1

2

3

DN

L [

LS

B]

PI DNL for div 3 with duty cycle of 33% and various pre-division input frequencies

9 GHz

0 50 100 150 200 250

Differential Phase Index

-3

-2

-1

0

1

2

3

DN

L [

LS

B]

12 GHz

0 50 100 150 200 250

Differential Phase Index

-3

-2

-1

0

1

2

3

DN

L [

LS

B]

15 GHz

Figure 45: Phase interpolator post-layout normalized Differential Nonlinearity fordivision by 3 with varying input frequencies with a duty cycle of 33%.

0 50 100 150 200 250

Differential Phase Index

-3

-2

-1

0

1

2

3

DN

L [

LS

B]

PI DNL for div 4 with duty cycle of 50% and various pre-division input frequencies

9 GHz

0 50 100 150 200 250

Differential Phase Index

-3

-2

-1

0

1

2

3

DN

L [

LS

B]

12 GHz

0 50 100 150 200 250

Differential Phase Index

-3

-2

-1

0

1

2

3

DN

L [

LS

B]

15 GHz

Figure 46: Phase interpolator post-layout normalized Differential Nonlinearity fordivision by 4 with varying input frequencies with a duty cycle of 50%.

60

0 50 100 150 200 250

Phase Index

-0.05

-0.04

-0.03

-0.02

-0.01

0

0.01

0.02

0.03

0.04

0.05

INL

[L

SB

]

PI INL for div 2 with duty cycle of 50% and various pre-division frequencies

6 GHz

9 GHz

12 GHz

Figure 47: Phase interpolator post-layout normalized Integral Nonlinearity for divisionby 2 with varying input frequencies with a duty cycle of 50%.

0 50 100 150 200 250

Phase Index

-0.05

-0.04

-0.03

-0.02

-0.01

0

0.01

0.02

0.03

0.04

0.05

INL

[L

SB

]

PI INL for div 3 with duty cycle of 33% and various pre-division frequencies

9 GHz

12 GHz

15 GHz

Figure 48: Phase interpolator post-layout normalized Integral Nonlinearity for divisionby 3 with varying input frequencies with a duty cycle of 33%.

61

0 50 100 150 200 250

Phase Index

-0.05

-0.04

-0.03

-0.02

-0.01

0

0.01

0.02

0.03

0.04

0.05IN

L [

LS

B]

PI INL for div 4 with duty cycle of 50% and various pre-division frequencies

9 GHz

12 GHz

15 GHz

Figure 49: Phase interpolator post-layout normalized Integral Nonlinearity for divisionby 4 with varying input frequencies with a duty cycle of 50%.

0 0.5 1 1.5 2 2.5

Time [ns]

-1

-0.5

0

0.5

1

Am

pli

tud

e [

V]

Phase interpolator output without inversion of input signal

fin

=15 GHz, Nfrac

=3.5

0 0.5 1 1.5 2 2.5

Time [ns]

-1

-0.5

0

0.5

1

Am

pli

tud

e [

V]

Phase interpolator output with inversion of input signal

fin

=15 GHz, Nfrac

=3.5

Figure 50: Phase interpolator post-layout differential output with and withoutinversion of input signal for consistent duty-cycle for division ratios between 3 to 4.

62

INL metrics as they are defined in respect to the pre-division clock period as isshown equations (23) and (24). As a result, it can be concluded that from purelytime-domain perspective, the range of deterministic jitter can be covered by the PIwith better compensation performance in the lower frequencies.

Besides linearity, another important consideration is the shape of the outputsignal in time-domain. The required shape at the output is determined by thesuccessive signal processing blocks after the PI. For example one could considerimplementing a quadrature phase generator at the output of the PI for generatingsignals for down-conversion mixer. In this case the quadrature phase generator wouldinduce some specifications for the PI output.

The time-domain output signal of the PI for MMD division-by-3/4 mode doesnot achieve consistent duty cycle without inversion of the MMD output as mentionedin Section 4.5.3. The effect of division by 3/4-mode having different duty-cyclesdepending on the inversion can be seen from Figure 50. In the upper waveform noinversion is used which results in correct instantaneous phase but non-consistentduty cycle. For division by 3 in the div-3/4 mode, the duty cycles is changed from33.3% to 66.7% in order to retain consistent duty cycle at the output of the phaseinterpolator. This can be implemented by inverting the input signal of the phaseinterpolator. The results can be seen from the lower waveform of the Figure 50,which shows the same instantaneous phase but with a consistent duty-cycle.

In conclusion, it has been shown that the PI is capable of compensating therequired one input period of pre-division clock signal and that a consistent duty-cycle can be achieved by using no-inversion for division-by-2/3 and inversion fordivision-by-3/4 modes of the MMD.

5.5 Combined Fractional Frequency Divider System Simu-lation

Simulation of the complete fractional frequency divider requires the simulation ofboth analog and digital circuits together. This simulation is denoted mixed-modesimulation and is performed using Questa ADMS.

The performance of the FFD is evaluated by performing transient simulations andtransforming the output signals from time- to frequency-domain with Fast-FourierTransform (FFT). With this transformation it is possible to evaluate the purity ofthe spectrum and the fundamental output frequency.

The FFT is performed with a frequency resolution of 20 MHz and a uniformwindow. The resolution of this transform is related to the sampling frequency andnumber of samples. These two terms in turn are related to the required simulationtime for achieving the required number of samples for achieving a specific FFTresolution.

The mixed-mode transient simulations are performed with the same biasing ofthe MMD as in Section 5.2 and with a pre-division clock with a frequency of 9 GHz.The FFD is programmed to divide by a fractional division ratio of Nfrac = 2.4 whichshould generate an output signal with a fundamental frequency of 3.75 GHz. Theoutput spectrum can be expected to not purely consist of a single frequency as the

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output waveform is a square wave in nature and the phase compensation is notperfect either.

The functionality of the FFD can be evaluated by analysing the waveform attwo different stages. These stages are right before and after the phase compensationperformed by the PI. In Figure 51, the output of the 3-phase generator, and theMMD output in turn, is shown with three phases with offsets of 0.5Tin. This createsthe required output phase range of 1Tin for the phase interpolator as discussed inSection 4.5.1.

Clearly from Figure 51, the waveform does not achieve a proper instantaneousphase. This results in a time-average signal of 3.75 GHz which requires the phaseinterpolator to compensate the phase offsets for achieving proper instantaneous phase.The spectrum corresponding to this waveform before phase compensation is shown inFigure 52. The spectrum shows significant spurs close to the fundamental frequencyof 3.75 GHz.

The time-average fractional frequency signal is processed by the phase interpolatorin order to generate a spectrally pure output. The phase compensation is performedby the phase interpolator with the proper phase selection control signals producedby the Σ∆-control circuit. This post-layout simulated compensated time-domainsignal is shown in Figure 53 and the corresponding spectrum is in Figure 54.

This signal has a good instantaneous phase and the spectrum is significantlyless noisy compared to the signal before any phase compensation procedures. InFigure 54, the most notable noise components are only the harmonics that are tobe expected for a square wave signal. All other spurs are below 40dB from thefundamental frequency of 3.75 GHz.

With these simulation results, it can be confirmed that a standalone fractionalfrequency divider can be designed using a multi-modulus counter based integerdivider, a Σ∆-digital control circuit and a phase interpolator. This combined systemdemonstrates the feasibility of designing distinct blocks with dedicated functionalitythat can achieve instantaneous phase with fractional division ratios from a frequencysynthesizer.

In addition to confirming the functionality of the FFD, the maximum operat-ing frequency and power consumption at different frequencies are also importantparameters to know. The fractional divider is capable of operating with an inputfrequency range of 6–16 GHz. The maximum operating frequency is in this casedefined differently from the input frequency range of the FFD. Maximum operatingfrequency is defined as the frequency where the phase interpolator or the MMD stopworking. The phase interpolator is deemed not working when the signals at the inputand output have different fundamental frequencies.

The maximum operating frequency is determined by using an integer divisionratio and using static settings for the phase interpolator. With static settings, nointerpolation is performed on the signal. In other words, the maximum operatingfrequency is determined for an integer divider that bypasses the PI. From simulations,is is confirmed that the maximum frequency is limited by the capabilities of thephase interpolator. The phase interpolator works up to 8.5 GHz for the post-layoutparasitic extracted version.

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0 0.5 1 1.5 2 2.5 3 3.5

Time [ns]

-0.2

0

0.2

0.4

0.6

0.8

1A

mp

litu

de

[V

]Phase interpolator single ended input A

A

0 0.5 1 1.5 2 2.5 3 3.5

Time [ns]

-0.2

0

0.2

0.4

0.6

0.8

1

Am

pli

tud

e [

V]

Phase interpolator single ended three phase inputs A, AB and B

Figure 51: Three phases for the phase interpolator input. The phases are 0.5Tin

apart from each other where fin = 9 GHz.

0 5 10 15 20 25 30 35

Frequency [GHz]

-140

-120

-100

-80

-60

-40

-20

0

10

Lo

g(|

P1

(f)|

) [d

B]

Normalized Single sided spectrum of differential in A to phase interpolator

Figure 52: Single sided normalized power spectral density of differential input Awhen fin = 9 GHz and Nfrac = 2.4.

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0 0.5 1 1.5 2 2.5

Time [ns]

-1

-0.5

0

0.5

1

Am

pli

tud

e [

V]

Differential output of phase interpolator

fin

=9G, Nfrac

=24

Figure 53: Differential output of phase interpolator for fin = 9 GHz and Nfrac = 2.4.Almost constant duty-cycle resulting in proper instantaneous phase.

0 5 10 15 20 25 30 35

Frequency [GHz]

-140

-120

-100

-80

-60

-40

-20

0

10L

og

(|P

1(f

)|)

[dB

]

Normalized Single sided output spectrum

X 3.75

Y 0

Figure 54: Single sided normalized power spectral density of differential output ofphase interpolator when fin = 9 GHz and Nfrac = 2.4.

Another important parameter to evaluate besides the maximum frequency isthe power consumption. The power consumption numbers are collected in Table 7and the numbers show that power consumption is highly dependent on the outputfrequency of the MMD, the signal that is to be fed to the PI. The reason for thehigher current consumption at higher frequencies lies in the structure of the phaseinterpolator. The number of components in the PI is significantly more than in theMMD which means that a lot more capacitance is charged and discharged duringthe operation. With higher frequency, a lot more charging and discharging occurs.This results in higher average power consumption at higher output frequencies.

All of the simulations that are presented thus far have been simulated together withpost-layout parasitics. The impact of the layout on the system performance can bedetermined by comparing these simulation results with schematic level performance.For instance, the maximum frequency where the phase interpolator fails to operate atall becomes lower and the current consumption increases when comparing performancebetween schematic post-layout simulations In Table 8 these values are collected. From

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the table it can be deduced that the maximum operating frequency of the PI hasdegraded almost 26% whereas the current consumption has increased by roughly 32%between the schematic and post-layout versions. The degradation in performancecan be attributed to the parasitic capacitances which limit the performance of thePI and also increase the current consumption.

Table 7: Simualted power consumption of the post-layout multi-modulus integerdivider and phase interpolator of the fractional frequency divider with respect todivision ratio and frequency

fin [GHz] Division Ratio fout [GHz] Current (mA) @ 0.9V6 3 2 686 2 3 949 3 3 94

12 3 4 1159 2 4.5 134

Table 8: Comparison table of frequency of failure for the phase interpolator andcurrent consumption between schematic and post-layout parasitic extracted versions.

Parameter Schematic Post-LayoutTotal Failure of PI at frequency of [GHz] 11.5 8.5Current Consumption (mA) @ fout = 3 GHz 71 94Current Consumption (mA) @ fout = 4 GHz 87 115

5.6 Performance Summary of the Fractional Frequency Di-vider

The performance of the designed fractional frequency divider can be summarizedinto a few key parameters. These parameters are input and output frequency range,division ratio, resolution of the output, jitter at the output and the capability forinstantaneous frequency switching. These parameters are in Table 9 for the designedFFD.

The input and output frequency ranges of 6 GHz to 16 GHz and 3 GHz to 4 GHzare tied to each other with the division ratios of the FFD. The FFD is capableof producing signals with frequencies above 4 GHz, but the signal has significantamount of jitter for specific input frequency and division ratio combinations. Thissuggests that the capabilities of the phase interpolator are the limiting factors forthe performance of the FFD as the PI is responsible for removing jitter.

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Table 9: Summary of the designed fractional frequency divider.

This WorkTechnology [nm] 28Supply [V] 0.9Input Frequency Range [GHz] 6–16Output Frequency Range [GHz] 3–4Division Ratio 2–4Frequency Raster [MHz] < 7.80Period Jitter (Peak-to-Peak) [ps] @ 4 GHz < 11Instantaneous Switching Yes

The output signal of the FFD has a theoretical resolution of 8 bits which is thedesigned resolution of the phase interpolator and in turn the resolution of the divisionratio. This gives the FFD a frequency raster that is less than:

fraster < fin( 1N

− 1N + 1

28)

= 8 × 109(12 − 1

2 + 128

) [Hz] ≈ 7.80 [MHz] (25)

Unfortunately because of the nonlinearity of the PI, the effective resolution of theFFD is less than the theoretical resolution which means that the frequency raster isalso slightly larger than the one calculated in Equation (25). The effective resolutionof the FFD is difficult to quantify as it is tied to the amount of jitter that is stillpresent after phase interpolation. In addition, the performance of phase interpolationis also dependent on the used fractional division ratio and input frequency whichfurther complicates the quantification of the effective resolution of the FFD.

Jitter that remains at the output of the FFD is the result of the nonlinearity ofthe PI. One jitter type that can be used for determining the performance of theFFD is period jitter. Period jitter is calculated by subtracting the period of the idealoutput frequency from the periods generated by the FFD. The difference betweenthe ideal and generated periods is the period jitter.

In the case of the designed FFD, the period jitter in the output is dependenton the input frequency and the fractional division ratio that is used. Figures 55and 56 show two cases where the maximum output frequency of 4 GHz is generatedwith different input frequency and division ratio combinations. The figures show theperiod jitter before and after the phase interpolator which clearly demonstrates thatthe PI is removing jitter from the signal generated by the MMD. From these figures,it is possible to deduce that the jitter remaining in the output signal is not solelydefined by the output frequency but by the combination of division ratio and inputfrequency. The difference in peak-to-peak period jitter between the two cases is 5ps as it is 6 ps when using a division ratio of 2.6054687 and 11 ps when the 4 GHzoutput is produced by using a division ratio of 3.5664062.

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Figure 55: Period jitter for input frequency of 10.422 GHz and division ratio of2.60546875. This combination produces an output frequency of roughly 4 GHz. Onthe left the jitter is determined before the phase interpolator and on the right afterthe phase interpolator. The number of counted pulses is 1000.

Figure 56: Period jitter for input frequency of 14.266 GHz and division ratio of3.56640625. This combination produces an output frequency of roughly 4 GHz. Onthe left the jitter is determined before the phase interpolator and on the right afterthe phase interpolator. The number of counted pulses is 1000.

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6 ConclusionModern wireless transmission systems have ever more demanding requirements forfrequency synthesizers. These requirements stem from various radio standards thatcurrent mobile devices have to support. This multi-standard support results inthe increased complexity for designing frequency synthesizers that are capable ofmulti-band operation.

This issue can be solved by improving frequency synthesis circuits with fractionalfrequency dividers. With the help of fractional frequency dividers, better frequencyresolution and wider frequency ranges can be supported together with a high frequencyfrequency synthesizer.

Fractional frequency dividers can be designed using different topologies and one ofthem is the counter-based divider approach. A counter-based divider is only capableof dividing by integer ratios and in order to achieve fractional ratios a division ratiobased on time-averaging is the only feasible way. This method produces errorsin time-domain which are required to be compensated in order to achieve properinstantaneous phase. This is critical in applications that requires the phase to becorrect for specific frequency.

In this thesis, an open-loop Σ∆ fractional frequency divider is designed. Thefractional frequency divider is based on three different functional blocks consisting ofa multi-modulus integer divider, a Σ∆-digital control circuit and a phase interpolator.The fractional division ratios are achieved by careful switching of the division ratios.This produces a waveform which has truncation errors produced by approximatingfractional numbers with integer ones. These truncation errors result in time-domainphase offsets that affect the instantaneous phase performance of the fractionalfrequency divider. A phase interpolator based phase offset compensation circuit isdesigned and used to remove this error in order to achieve proper instantaneousphase.

The performance of the designed open-loop fractional frequency divider is demon-strated and evaluated by performing mixed-mode transient simulations of the completesystem. With the simulations it is confirmed that individual blocks operate at thedesired input frequency range of 6 GHz to 16 GHz and produce an output in therange of the 3 GHz to 4 GHz which is of interest for the new 5G communicationstandards. The FFD is capable of providing a spectrally pure output waveform withgood instantaneous phase. The FFD was designed in 28 nm CMOS and occupies anarea of 0.17 mm2. It consumes 103.5 mW of power, when producing an output signalof 4 GHz with a peak-to-peak period jitter of less than 6 ps. The frequency raster ofthe FFD is less than 7.8 MHz.

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