Design of 0.68-mW LC-based Digitally Controlled Oscillator ...low power digitally controlled...

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.5, OCTOBER, 2017 ISSN(Print) 1598-1657 https://doi.org/10.5573/JSTS.2017.17.5.611 ISSN(Online) 2233-4866

Manuscript received Sep. 26, 2016; accepted Sep. 18, 2017 1 Department of Smart Automobile, Pyeongtaek University, Pyeongtaek-si 450-701, Korea 2 College of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746, Korea E-mail : [email protected] (Corresponding Author : Kang-Yoon Lee) This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2016R1C1B1009560).

Design of 0.68-mW LC-based Digitally Controlled Oscillator (DCO) for Bluetooth Low Energy (BLE)

Transceiver

Sang-Sun Yoo1 and Kang-Yoon Lee2

Abstract—This paper presents the design method of a low power digitally controlled oscillator (DCO) for Bluetooth Low Energy (BLE) transceivers. Through minimizing parasitic capacitance and maximizing the main inductance, the DCO can mitigate initial oscillation conditions with low supply voltage. The proposed design procedure focuses on how to optimize switched capacitors and their number in capacitor banks within the specifications. A small number of switched capacitors can reduce parasitics and power consumption. The proposed DCO is fabricated using a 55-nm 1P6M CMOS process and meets the specifications of BLE with 0.68-mW power consumption. The phase noise of the DCO is -114.2 dBc/Hz @ 1 MHz at 4.96 GHz. The tuning range of the DCO is set to 4.5-5.3 GHz, which is sufficient to support BLE applications despite the process, voltage, and temperature (PVT) variations. Index Terms—ADPLL, BLE, DCO, IoT, low power, low voltage, subthreshold, VCO

I. INTRODUCTION

Recently, the demand for the internet-of-things (IoT)

has increased in many RF applications such as wearable devices, health care, and sensor networks [1, 2]. IoT applications require small size and low cost as well as long battery life. The Bluetooth low-energy (BLE) standard is a good candidate for low power IoT applications with high security [3]. BLE operates in the 2.4-GHz industrial, scientific, and medical (ISM) band and uses Gaussian frequency-shift keying (GFSK) with a modulation index of h=0.5 for signaling [4]. Since the GFSK signal has only frequency differences with a constant envelope, phase locked loop (PLL)-based modulators are widely used instead of the IQ-based modulator [5]. All digital phase locked loop (ADPLL) has many advantages compared to analog PLL (APLL) in terms of area, integration, and development time [6]. ADPLL can be designed with a higher density for better integration than conventional APLL because of its highly digitized implementation and the use of a digital loop filter (DLF) [7]. Moreover, ADPLL can significantly reduce power consumption by using the open loop direct modulation method [8]. In this modulation method, many ADPLL blocks for phase locking can be turned off, as shown in Fig. 1. The retimer, time-to-digital converter (TDC), and digital phase detector (DPD) do not operate while the ADPLL-based transceiver transmits the modulated signals. In the open loop transmitting mode, the most power-hungry block in ADPLL is a digitally controlled oscillator (DCO), which can easily generate GFSK modulated signals directly with a Gaussian filter (GF). A divider-by-2 is an essential block to avoid local oscillator (LO) pulling [9]. Since the power consumption of true-single-phase-clock (TSPC) dividers is determined

612 SANG-SUN YOO et al : DESIGN OF 0.68-mW LC-BASED DIGITALLY CONTROLLED OSCILLATOR (DCO) FOR …

by CMOS process according to the operating frequency, the divider-by-2 is not a dominant block for reducing the power consumption. In addition, the power consumption of DLF and GF is negligible compared to that of DCO because the operation frequency is the same as the reference clock of 32 MHz. For these reasons, the power consumption of DCO determines that of the ADPLL when transmitting the modulated signal.

In this paper, a low power DCO design is proposed. To reduce power consumption, the DCO adopts a low supply voltage with CMOS complementary architecture. Since the main inductor of the DCO is designed to be as large as possible, the minimum oscillation condition can be mitigated and power consumption is also reduced with low supply voltage. In satisfying the requirement for the tuning range, the design procedure focuses on how to maximize the main inductor by minimizing the parasitic capacitance, taking into consideration the process, voltage, and temperature (PVT) variation. The DCO was implemented using a 55-nm CMOS technology and the power consumption is 0.68 mW with low phase noise.

This paper is organized as follows. Section II explains the factors taken into consideration for low power consumption in the DCO design such as the architecture, optimization of capacitor banks, and configuration of switched capacitors. Section III covers the DCO core design and metal capacitors for the fine frequency step. Section IV verifies the measured performance of DCO with discussions. Finally, section V presents a conclusion.

II. THE CONSIDERATION FOR LOW POWER

LC-BASED DCO

1. Determination of Architecture and LC Tank In LC-based oscillator design, CMOS complementary

architectures, as shown in Fig. 2, are conventionally employed for low power consumption because their gm can be two-fold that of other architectures such as NMOS and PMOS only gm-cell architecture [10]. Power consumption in CMOS complementary architecture can be reduced following two approaches. In the first approach, a current source is used to limit the current in the oscillator core, while in the second approach the supply voltage is lowered. Since the current source is one of the dominant noise sources in LC oscillators, some techniques for canceling noise are required [11, 12]. In the deep sub-micron CMOS process, approaches in which a low supply voltage is adopted are more helpful because the threshold voltage of MOSFET is significantly decreased.

The first step in the design of the oscillator is determining the main inductor and total capacitance. For low power consumption, the main inductance and quality factor (Q-factor) of DCO should be maximized because the minimum oscillation condition of gm is defined as

0

12m

L

gf LQp

> (1)

where L and QL are the inductance of the LC tank in DCO and the Q-factor of the main inductor, respectively.

CK

R

Fig. 1. ADPLL based transmitter with open loop GFSK modulator.

VDD

L

CCp Cp

Cp.SW Cp.SW

Fig. 2. Simplified schematic for CMOS complementary LCoscillator.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.5, OCTOBER, 2017 613

Increasing the main inductance has some limitations due to the trade-off between the inductance and the tuning range of DCO. The total capacitance in a DCO is composed of parasitic capacitance (Cp), switch parasitic (Cp,SW), and total switchable capacitance (DCtot) in LC-Tank, as shown in Fig. 2. Cp,SW varies with the gate voltage of the switch and with oscillation swings. The minimum and maximum frequencies are defined as follows.

max

, ,

12 ( )p p SW off

fL C Cp

=+ (2)

min

, ,

12 ( )p p SW on tot

fL C C Cp

=+ + D (3)

Cp contains many types of parasitics from gm-cells,

buffers, the main spiral inductor, routing lines, and so on. The main inductance of DCO can be maximized and the current of DCO is decreased as (Cp + Cp,SW) becomes smaller in size. However, the increase of Cp,SW is unavoidable because it is proportional to DCtot about constant of b which differs from the CMOS processes.

,p SW totC Cbµ × D (4)

Since the large DCtot increases the size of the switches and capacitors, Cp,SW is compelled to be increased by force due to the large DCtot. Assume that the inevitable minimum parasitic capacitance (C0 = Cp,SW,off + Cp) is 500 fF for the tuning range of 1 GHz and the maximum frequency of fmax is 5.4 GHz. The main inductance of L is determined to be about 1.74 nH from Eqs. (2, 3). If the required tuning range is increased, Cp,SW is also increased because it is proportional to DCtot. As a result, the required main inductance should be decreased and the power consumption can also be increased as well. Considering PVT variation, determining the optimum tuning range is the most important factor in reducing power consumption.

2. Determination of Capacitor Banks

After the main inductor is determined with maximum

frequency (fmax), tuning range (fmax-fmin), and total switchable capacitance (DCtot), the design of the

capacitor bank is initiated as the second step. In a DCO design, the minimum frequency step should be carefully determined because it is related to the frequency tolerance, phase noise, and quantization noise [13]. In the BLE system, the required tolerance of carrier frequency accuracy is ±1 ppm and the modulated frequency deviation is 50 kHz [4]. This means that the minimum frequency resolution of DCO (Dfmin) should be less than 2.4 kHz. From Eq. (5), the required minimum switchable capacitance of DCfine can be calculated as 1 aF when the inevitable parasitic capacitance of C0 = (Cp,tot,SW,off + Cp,tot) is assumed to be 500 fF (contained with the parasitic of driving buffer).

finemin

max 02Cf

f CDD

= - (5)

A DCfine of 1 aF is a serious burden in terms of the feasibility and controllability [14]. If C0 can be increased, the requirement of DCfine can also be mitigated. However, a large C0 causes the small main inductance and large power consumption. The 1/16 SD dithering can help to reduce the requirement of DCfine by about 16-fold without increasing the C0 [15]. As a result, the specification for DCfine is mitigated to 16 aF. Fig. 3 shows the characteristics and relationships between the capacitor banks in a DCO when the DCO has three types of capacitor banks: MSB, LSB, and fine tuning bank. The codes for the MSB/LSB bank are fixed during frequency locked loop (FLL) or adaptive frequency calibration (AFC) is operated to search for the desired oscillation frequency. Afterward, the code for the fine frequency bank is determined for fine locking in ADPLL.

MSB MSB totN C C´ D @ D

2LSB LSB MSBN C C´ D @ ´ D

fine 4Fine LSBN C C´ D @ ´ D

Fig. 3. The characteristic of capacitor banks and relationships between the banks.


In a DCO, the sum of the fine frequency steps must be 3~5 times larger than the 1-LSB step to prepare for PVT variations [16]. The relationship between DCLSB and DCfine can be expressed as

fine4 LSB FineC C N´ D £ D ´ (6)

where DCLSB is a unit switchable capacitance in LSB capacitor bank and NFine is the number of fine tuning capacitors. Although the relation between the fine tuning capacitor units implies a trade-off between the two unknown variables of NFine and DCLSB, the unknown variables can be easily fixed. The total fine frequency range (DfFine,tot=NFine×DCfine) is determined to retain the phase lock by the frequency variations according to the variation of temperature. Since the relock-time of time-division-multiplexing (TDD) system is very short, the frequency variation is also small by the variation of temperature. 5 MHz of total frequency range due to fine capacitor bank (DfFine,tot) is sufficient to endure the variation of temperature. Although DfFine,tot is sufficient for about 5 MHz, DCLSB is determined with the minimum value using a process design kit (PDK) to avoid using series connected capacitors, which increase the chip area. In the 55-nm CMOS process, the value is about 0.5 fF to ensure the reliability and the frequency range due to 4·DCLSB is about 12 MHz. Therefore, from Eq. (6), NFine becomes a binary number of 128 (DCfine = 16 aF). Due to the nonlinearity of the MSB capacitor step, some overlaps are required between a unit capacitance of DCMSB and the sum of the DCLSB in the capacitor bank. The relationship is expressed as 2LSB LSB MSBN C C´ D @ ´ D (7)

where DCMSB is unit switchable capacitance in MSB capacitor bank and NLSB is the number of capacitors in LSB bank. In addition, the total frequency range of Dftot is related to DCtot and is approximately expressed to determine the number of MSB capacitors (NMSB) and DCMSB. MSB MSB totN C C´ D @ D (8)

From Eqs. (7, 8)

2MSB LSB LSB totN N C C´ ´ D @ ´ D (9) From Eqs. (2, 3), the required DCtot can be calculated

as 175 fF assuming C0=500 fF and Dftot=0.8 GHz. Due to the two unknown variables in Eq. (9), many solutions are possible, as shown in Table 1. When NLSB is 32 and NMSB is 24, the designed DCO has the smallest numbers of MSB/LSB capacitor units. Therefore, the DCO can have the smallest parasitic capacitance due to the routing lines and the lowest power consumption.

3. Configuration of Switched Capacitor

The dominant parasitic capacitance is obtained from

switched capacitors in an LC-based oscillator. The size of switches and the configuration of the switched capacitors determine the parasitic capacitance and the performance of the oscillator. Fig. 4(a) shows the conventional switched capacitor [17, 18]. In this case, the source voltage of the switch is always fixed to zero volts. When

Table 1. Required number of unit capacitors in MSB/LSB Bank

Cases Sum NLSB NMSB NLSB + NMSB

8 93 101 16 47 63 32 24 56 64 12 76

Fig. 4. (a) Operation conditions for a switched capacitor with fixed bias according to a large oscillation swing, (b) Configuration of the proposed switched capacitor and its operations according to the large oscillation swing.


a DCO has a small swing, the fixed bias is not problematic. However, when the DCO has a large swing, the fixed bias can cause the degradation of phase noise. In the OFF-mode for the switch, since the impedance of the switch is a few mega ohms, a large oscillation swing is directly connected between the source of the switch and the capacitor without degradation of the swing. Assuming the voltage swing is about 0.8 V in the switch node, the oscillation swing changes from -0.4 to 0.4 V while the gate voltage of the switch is fixed to 0 V. Therefore, the switch can be operated in linear or saturation mode while the voltage swing is changed. This means that the switch is not completely turned off, which can degrade the performance of the DCO.

To solve the above problems, two inverters are adopted as control logics for changeable biasing as shown in Fig. 4(b). In the ON-mode for the switch, the gate voltage of the switch is VDD and the source voltage is zero. Otherwise, in the OFF-mode, the gate voltage of the switch is zero and the source voltage become the output voltage of low dropout (LDOout) with about 0.8 V. The source voltage of the switch is changed from 0.4 to 1.2 V due to the oscillation swing. In this case, the switch is not operated in the deep triode or saturation region because Vgs,sw is always less than 0 V. In the changeable biasing configuration, as shown in Fig. 4(b), reliability problems can sometimes occur. If the voltage swing is larger than 0.8 V or LDOout > 0.8 V, Vgs,sw can be more than -1.2 V at the maximum swing point. In this case, thick-oxide MOSFET should be employed as a switch for reliability instead of a low voltage threshold (LVT) MOSFET. The size of the thick-oxide MOS switch needs to be increased to maintain the same turn-on-resistance for the LVT MOSFET. When a DCO is designed with a thick-oxide MOSFET switch, the performance of the DCO may be degraded because the large sized switches create large parasitic capacitance. For low power consumption of the DCO, an LVT MOSFET switch is better as the switch because it has a low turn-on resistance and a small size. For these reasons, the output voltage of low dropout (LDO) in the proposed DCO is regulated to 0.8 V, and the amplitude of the oscillation swing is limited to 0.8 V. Different supply voltages (0.8 V and 1 V) are then applied to two inverters as shown in Fig. 4(b). These processes are useful to minimize the turn-on-resistance for the switches. A Vgs,sw of 1 V can

produce lower turn-on-resistance than that of 0.8 V. However, different supply voltages should be carefully employed, since they can cause unwanted leakage current while increasing performance of the LC-based DCO.

III. DESIGN OF DCO

Fig. 5 shows the simplified schematic and configuration of three capacitor banks. All capacitor banks are designed with unit weighted structures instead of binary weighted structures in order to ensure linearity in the frequency step. Although the area of the unit weighted capacitor bank is 5%~10% larger than that of the binary capacitor bank, the former has many advantages in terms of linearity and flexibility in design [19]. Compared to a binary weighted structure, the use of equal-weighted capacitors offers better element matching and DNL performance. In addition, since the unit weighted structure can have non-binary number of capacitors, optimal design is possible with the flexibility in the capacitor bank. Proposed DCO employs 24 capacitors which is not a binary number in MSB bank. If the DCO must have a binary number of capacitors, many performance may be degraded due to unwanted excess capacitance. 31-LSB capacitors are adopted in LSB bank for 5-bit control and 1-capacitor is used as dummy for keeping the same environment between others. 128-capacitors in fine frequency bank are separated to two groups: 127-fine capacitors and 1-dithering capacitor [14]. The MSB/LSB capacitor banks are designed with changeable biasing switched capacitors as mentioned in

Fig. 5. Schematic of designed DCO and proposed metal capacitor for high frequency resolution with high linearity.


section II. In the fine capacitor bank, the configuration of the unitcell differs from that of the MSB/LSB tuning bank. The unit switchable capacitance in the fine tuning bank is about 16 aF. The impedance of the capacitor for fine tuning is sufficiently large compared to the turned-off-resistor of a switch. This means that the amplitude of the large swing is divided by the ratio of impedance. Therefore, fixed biasing causes no problem when some of the switches are turned off. In the MSB/LSB capacitor banks, metal-oxide-metal (MoM) and metal-insulator-metal (MiM) capacitors are widely employed instead of MOSFET capacitors to increase the Q-factor of the LC-tank. In deep sub-micron CMOS processes, the density of the MoM capacitor increases remarkably due to the finger space of a few tens of nanometers. The MoM capacitor finally overcomes the disadvantages of the MiM capacitor such as large capacitance variations and high cost for mask production [20]. To reduce the cost, the fabricated DCO is designed with MoM capacitors. To reduce the chip area, in the MSB capacitor bank, the MoM capacitors are stacked from M2 to M5 for high capacitor density. On the contrary, the MoM capacitors in the LSB capacitor bank are stacked from M3 to M5 because the LSB capacitor bank needs the minimum capacitance in the PDK, as mentioned previously.

The phase noise of the DCO is related to the frequency resolution, which is limited by the unit switchable capacitance [13]. Many studies have focused on minimizing the unit switchable capacitance for fine frequency tuning [14, 21, 22]. In fine tuning bank, to obtain a small switchable capacitance and high linearity, customized lateral metal capacitors are proposed and fabricated as shown in Fig. 5. The configuration of the capacitor is similar to that of the MoM capacitor. The spacing between fingers has longer distance than that of the MoM capacitor for small capacitance. The capacitances are involved in two layers, M3 and M5. M4 is used only as a floating dummy in order to reduce the variations. The increased parasitic capacitance due to the dummy from the electromagnetic (EM) simulation is negligible. The disadvantage of lateral metal capacitors is the relatively large area needed because of the long distance between fingers. The increased areas can be minimized by sharing the metal capacitor and active components for switching and biasing. The proposed switchable capacitor can obtain high linearity without

increase of the chip area because the components are shared. According to the results of RC-extraction and EM-simulation, the designed capacitor can be easily calculated and its simulated value is 16 aF. One of the 128 capacitors in the fine tuning bank is selected as a dithering capacitor to create 1/16 capacitance.

IV. MEASUREMENT RESULTS

The proposed DCO is designed and fabricated with 55-nm CMOS technology. A 2.5D-EM simulation was accompanied with RC-extraction. After the active components in the layout of the DCO are completely eliminated, interactions and parasitic inductances between routing lines are calculated using EM-solver. DC, periodic steady state (PSS), harmonic balance (HB), and transient simulation can then be performed by utilizing the extracted EM-data. These EM-based post layout simulations can increase the accuracy in simulations for oscillation frequency, frequency step, power consumption, and phase noise [23]. Since the added parasitic inductance by routing lines in the designed DCO is predicted to be about 0.19 nH from EM-solver, the main inductor was trimmed from 1.74 nH to 1.55 nH which differs from the assumption in section II.

The measurement results for oscillation frequency are well matched with the EM-based post layout simulation as shown in Fig. 6. For the exact comparison between the measurements and the simulations, the process control monitor (PCM) data of fabricated samples are examined. The PCM data corresponds to the measurement data from the process-monitoring-tags inserted in a wafer to monitor the variation of MoM capacitance. Fortunately, the capacitor density of the measured sample is 1.85 fF/mm2, which is the same density of MoM capacitor as that of the post-simulation. This is one of the reason for the well match between the simulation and the measurement results. If the capacitor densities are different between a simulation condition and that of a fabricated sample, the comparison is difficult and the simulation condition should be modified. In addition, since the post layout simulation contains the interactions of parasitic inductances from the extracted EM-data, the errors between simulations and measurements can be minimized. Although the MoM capacitors may have variations of about ± 20%, the tuning range of the DCO


covers all BLE channels from 4804 MHz to 4960 MHz as shown in Fig. 6. The maximum difference between simulations and measurements is only about 10 MHz. This means that the frequency steps are well matched with the measurements as well as with the oscillations frequencies. Fig. 7 shows the frequency responses and resolutions by control codes for fine frequency tuning. Without the use of time-averaging methods, the oscillation frequency is linearly tuned according to fine frequency control words. In Fig. 7, although Dffine has some fluctuations, oscillation frequencies are monotonically increased. Considering the error due to measurement, the fluctuations do not cause problems. The average Dffine is about 3.2 kHz after dithering at 2.4 GHz, which is slightly larger than the expected Dffine of 2.4 kHz. In fact, the simulation results of Dffine is slightly different between the results using RC-extraction and the results using EM-solver. The simulation results using EM-solver are well matched with measurements compared to that of RC-extraction in terms of average

Dffine in the fabricated DCO. Since the distance between the fingers are considerably long, the simulation results using EM-solver might have higher accuracy than those of RC-extraction. Fig. 8 shows the phase noise of the designed DCO at 4.96 GHz which is the highest channel for BLE. The proposed DCO has low phase noise of -114.2 dBc/Hz @ 1 MHz with low power consumption of 0.68 mW. The phase noise is measured at the output test buffer before the divider-by-2. The modulation characteristics for GFSK are shown in Fig. 9. The waveform shows the modulation results of the output of the proposed DCO. As can be seen from the results, the direct modulation wave of the DCO meets the specification of the required frequency deviation from 185 kHz to 250 kHz [4]. In many field tests, the test of the carrier frequency offset and drift is the most important for the direct modulation transmitter. Especially, the carrier drift of f[n]-f[n-5] should be less than 20 kHz in the worst case. By using the stable LDO and bypass capacitor, the specification of the frequency drift can be satisfied with temperature variations, as

Fig. 8. Measurement results of phase noise.

Fig. 9. GFSK modulated signal by using designed DCO.

0 200 400 600 8004200

4400

4600

4800

5000

5200

5400

-40

-20

0

20

40

Ocs

cilla

tion

Freq

uenc

y (M

Hz)

Frequency Control Words

Simulation with EM data Measurement Simulation with MoM -20% Simulation with MoM +20%

Diffe

nenc

e be

twee

n M

eas.

and

EM-b

ased

Sim

. (M

Hz)

Fig. 6. Comparison of oscillation frequency between measurement and simulation results.

103. 3.22 16

Avg f kHzD = @´

-20 0 20 40 60 80 100 120 140

4845

4850

4855

4860

4865

60

80

100

120

140

160

180

200 Measured oscillation frequency

Df in

Fin

e Tu

ning

Ban

k (k

Hz)

Osc

illatio

n Fr

eque

ncy

(MHz

)

Fine Frequency Control Words

Fig. 7. Oscillation frequency and frequency step of DCfineaccording to fine frequency control words.


shown in Fig. 9. In addition, the shielding methods between PA and DCO are useful to minimize the frequency drift [24].

Other performance results are summarized in Table 2. The fabricated DCO has better performances than previous works with respect to power consumption and phase noise. The overall performance of the DCO can be represented by a figure-of-merit (FoM) as follows [25].

0( ) 20log 10log1

DCoffset

offset

f PFoM PN f

f mWæ ö æ ö= - + -ç ÷ ç ÷ç ÷ è øè ø

(10) The FoM of the designed DCO is 190 dBc/Hz, which

is superior to those of previous works. In comparison with [28], the proposed DCO has lower power consumption and a smaller area.

Fig. 11 shows the micro-photograph of the DCO and the size is about 360×220 mm2. The location of the gm-cell has a trade-off between power consumption and frequency range. If the gm-cell is located at the end of the capacitor bank, the DCO has a large effective inductance when all switches are turned off. The inductance can help to reduce the current consumption. However, the tuning

range of the DCO is slightly decreased due to parasitic inductance. In contrast, the gm-cell located in the neck of the inductor can help in tuning the range of DCO. However, since the Q-factor of the inductor can be degraded by the gm-cell, power consumption may be increased. The location of the gm-cell in the fabricated DCO is at the end of the capacitor bank to reduce power consumption.

V. CONCLUSIONS

A design procedure for a sub-mW DCO is proposed. The procedure focuses on reducing parasitic capacitance to maximize the main inductance of DCO. In addition,

Fig. 10. Result of test for direct modulation.

Table 2. Summary of performance of designed DCO and comparison with previous works

This Work VLSI’2013 [26] JSSC’2014 [27] JSSC’2015 [28] Application BLE BLE ZigBee WSN

Frequency (MHz) 4497-5312 4804-4960a 9600b 4400-5400 Supply voltage (V) 0.8 1.3 1.2 0.35

Current (mA) 0.85 0.7 1 4.7 Phase noise (dBc/Hz) -114.2 @ 1 MHz -101 @ 1 MHz -104 @ 1MHz -120 @ 1 MHz

FoM (dBc/Hz) 190 175 180 193 CMOS process 55 nm 65 nm 65 nm 65 nm

Area (mm2) 0.07 mm2 0.1 mm2 0.06 mm2 0.19 mm2

a. Bluetooth channel b. VCO frequency for ZigBee (div4)

DCO coreTest buffer gm cell

DigitalBlock

Fig. 11. Microphotograph of designed DCO.


capacitor banks are optimized for low power consumption without degradation of DCO performances. The proposed DCO is designed using a 55-nm 1P6M CMOS process with customized metal capacitors for linearization. The DCO has linear oscillation frequency steps with low power consumption of about 0.68 mW. The DCO has low phase noise of -114.2 dBc/Hz @ 1MHz at 4.96 GHz and a superior FOM of 190 dBc/Hz. The performance of the DCO can meet the specifications of BLE. Finally, the DCO can directly generate GFSK modulated signals.

ACKNOWLEDGMENTS

The authors would like to thank Dr. S. Ko and Dr. C.-W. Yao for their contributions to this work, as well as Dr. D.-H. Shin for supporting EMX.

REFERENCES

[1] S. M. R. Islam, D. Kwak, M. H. Kabir, M. Hossain, and K.-S. Kwak, “The Internet of things for health care: A comprehensive survey,” IEEE Access, vol. 3, pp. 678-708, Jun. 2015.

[2] S. Amendola, R. Lodato, S. Manzari, C. Occhiuzzi, and G. Marrocco, “RFID technology for IoT-based personal healthcare in smart spaces,” IEEE Internet Things J., vol. 1, no. 2, pp. 144–152, Apr. 2014.

[3] K.-H. Chang, “Bluetooth: a viable solution for IoT?” IEEE Wireless Commun., vol 21, no. 6, pp. 6-7, Dec. 2014.

[4] Bluetooth Specification, Volume 6 (Low Energy Controller), Bluetooth SIG, Dec. 2009.

[5] K.-H. Huang and C.-K. Wang, “A cost effective binary FSK demodulator for low-IF radios,” in Proc. Int. Symp. VLSI Technology, Systems, and Applications, 2001, pp. 133–136.

[6] C.-W. Yao and A. L. Willson, “A 2.8-3.2-GHz fractional-N digital PLL with ADC-assisted TDC and inductively coupled fine-tuning DCO,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 698–710, Mar. 2013.

[7] R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS

process,” IEEE Trans. Circuits Syst. II, vol. 50, no. 11, pp. 815–828, Nov. 2003.

[8] P. Su and S. Pamarti, “A 2.4 GHz wideband open-loop GFSK transmitter with phase quantization noise cancellation,” IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 615–626, Mar. 2011.

[9] B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice Hall, 1998.

[10] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717–724, May 1999.

[11] E. Hegazi, H. Sjoland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921–1930, Dec. 2001.

[12] P. Andreani and H. Sjoland, “Tail current noise suppression in RF CMOS VCOs,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 342–348, Mar. 2002.

[13] C. M Hung, R.B. Staszewski, N. Barton, M.C. Lee, and D. Leipold, “A digitally controlled oscillator system for SAW-less transmitters in cellular handsets,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp 1160-1170, May 2006.

[14] S.-S. Yoo, Y.-C. Choi, H.-J. Song, S.-C. Park, J.-H. Park, and H.-J. Yoo, “A 5.8-GHz high-frequency resolution digitally controlled oscillator for using the difference between inversion and accumulation mode capacitance of pMOS varactors,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 2, pp. 375-382, Feb. 2011.

[15] R. B. Staszewski, C. M. Hung, D. Leipold, and P. T. Balsara, “A first multi-gigahertz digitally controlled oscillator for wireless applications,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 11, pp. 2154-2164, Nov. 2003.

[16] H. Lee, J.-K. Cho, K.-S. Lee, I.-C. Hwang, T.-W. Ahn, K.-S. Nah, and B.-H. Park, “A S-D fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1164–1169, Jul. 2004.

[17] T.-P. Wang and S.-Y. Wang, “Frequency-tuning negative-conductance boosted structure and applications for low-voltage low-power wide-


tuning-range VCO,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 6, pp. 1137–1144, Jun. 2015.

[18] W. Wu, J. R. Long, and R. B. Staszewski, “High-resolution millimeterwave digitally controlled oscillators with reconfigurable passive resonators,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 2785–2794, Nov. 2013.

[19] C.-H. Lin and K. Bult, “A 10-b 500-MSample/s CMOS DAC in 0.6 mm2,” IEEE J. Solid-State Circuits, vol. 33, pp. 1948–1958, Dec. 1998.

[20] G. Huang, et. al., “A 45 GHz CMOS VCO adopting digitally switchable metal-oxide-metal capacitors,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 1, pp. 270-272, May 2011.

[21] J. H. Han and S. H. Cho, “Digitally controlled oscillator with high frequency resolution using novel varactor bank,” Electron. Lett., vol. 44, no. 25, pp. 1450-1452, Dec. 2008.

[22] L. Fanori, A. Liscidini, and R. Castello, “Capacitive degeneration in LC-tank oscillator for DCO fine-frequency tuning,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2737–2745, Dec. 2010.

[23] S.-S. Yoo and K.-Y Lee, “A frame-based EM-simulation for design of LC oscillator with MoM capacitor banks,” Int J RF Microw Comput Aided Eng., vol. 27, no. 7, pp. 1-9, Sep. 2017.

[24] S.-S. Yoo, K.-Y Lee, and H.-J. Yoo “Coupling-shielded inductor for high isolation between PA and LC-based DCO,” IEEE Electron Device Lett., vol. 38, no. 1, pp. 24-27. Jan. 2017.

[25] L. Fanori and P. Andreani, “Highly efficient class-C CMOS VCOs, including a comparison with class-B VCOs,” IEEE J. Solid-State Circuits, vol. 48, no. 7, pp. 1730–1740, Jul. 2013.

[26] S. Chakraborty et al., “An ultra low power, reconfigurable, multi-standard transceiver using fully digital PLL,” in Proc. Symp. VLSI Circuits, 2013, pp. 148–149.

[27] Z. Lin, P. Mak, and R. P. Martins, “A 2.4 GHz ZigBee receiver exploiting an RF-to-BB-Current-Reuse Blixer+Hybrid filter topology in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 6, pp. 1333–1344, Jun. 2014.

[28] A. G. Roy, S. Dey, J. B. Goins, T. S. Fiez, and K. Mayaram, “350 mV, 5 GHz class-D enhanced swing differential and quadrature VCOs in 65 nm

CMOS,” IEEE J. Solid-State Circuits, vol. 50, no. 8, pp. 1833–1847, Jul. 2013.

Sang-Sun Yoo received his B.S. degree from Dong-guk University, Seoul, Korea, in 2004, and his M.S/Ph.D. degree received from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 2012. He worked for System LSI

division in Samsung Electronics from 2012 to 2015 where he focused on ADPLL for 3/4G mobile applications as a senior design engineer. From 2015 to 2016, he was a Research Assistant Professor in KAIST and Sungkyunkwan University. Since 2017, he has been with the Department of Smart Automobile, Pyeongtaek University, where he is currently an Assistant Professor. His research interests include RF systems for mobile communications, reconfigurable RFICs, automotive ICs, ADPLL, RFID, and sensor communications. Dr. Yoo was the recipient of the Best Paper Award of the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS in 2011.

Kang-Yoon Lee received the B.S., M.S. and Ph.D. degrees in the School of Electrical Engineering from Seoul National University, Seoul, Korea, in 1996, 1998, and 2003, respectively. From 2003 to 2005, he was with GCT Semiconductor Inc., San Jose,

CA, where he was a Manager of the Analog Division and worked on the design of CMOS frequency synthesizer for CDMA/PCS/PDC and single-chip CMOS RF chip sets for W-CDMA, WLAN, and PHS. From 2005 to 2011, he was with the Department of Electronics Engineering, Konkuk University as an Associate Professor. Since 2012, he has been with College of Information and Communication Engineering, Sungkyunkwan University, where he is currently an Associate Professor. His research interests include implementation of power integrated circuits, CMOS RF transceiver, analog integrated circuits, and analog/digital mixed-mode VLSI system design.

Design of 0.68-mW LC-based Digitally Controlled Oscillator ...low power digitally controlled...

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