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A CMOS CURRENT-CONTROLLED OSCILLATORAND ITS APPLICATIONS

Chunyan Wang,M . Omair Ahmad, Fellow, IEEE andM.N.S.Swamy, Fellow, IEEE

D e p a r t m e n t of Electr ical and C o m p u t e r E n g i n e e r in gCon cord ia University,

1455 de M a i s o n n e u v e B l v d . W e s tMont rea l , Quebec ,Canada H3G 1M8

E-mail: [chunyan, omai r, swamy]@ece.concordia.ca

ABSTRACTIn this paper, we present the design ofa new current-controlled oscillator (ICO). The control current of thisI C 0 i s in a nano or sub-nano Ampere range and thesensitivity of the frequency of its output voltage to the

control current is about700 MH z per PA. Th e circuit canoperate with a low supply voltage, e.g.VDU< 1 V when itis implemented with a0.18-pm technology. It requires nobias current, thus have very low power dissipation. Thecircuit can be easily implemented using a standard digitalCMOS technology. Some applications of the proposedICO, particularly those for AID conversion, are alsodescribed in the paper.

1. INTRODUCTION

Current-controlled oscillators ( K O ) are importantbuilding blocks in the design of electronic signal

generation, processing or data-conversion circuits. Manyof the existing current-controlled oscillators are basedonmulti-vibrators or ring oscillators, in which m ultiple stage sof delay elements are included. Logic gates andoperational amplifiers (OpAmp) are often usedas suchdelay elements. In the former, the current available tocharge or discharge a capacitanceof each of the gates isadjusted in order to change the frequencyof oscillation[11.In the latter, the control current is used to adjust the circuitbias so that the gain of the OpAmps can he modified inorder to adjust the frequency [Z] - [ 5 ] In either case, acurrent variation of several nano-Amperes may not belarge enough to result in a significant change of thefrequency.

In this paper, we propose the design of a current-controlledoscillator that is ableto operate with a control currentin anA or sub-nA range. Some of the applications of theproposed circuit arealso considered.

2. CIRCUIT DESCRIPTION

As shown in Figure I the proposed current-controlledoscillator consists of a CMOS latch (Invl and InvZ),aPMOS switch pair (PI and P2), and two NM OS switchpairs ( N I and N,, N3 nd N4 . Voltages V and V are,respectively, the r e m and set signals of the latch, and V,and V are the complementary output voltages of thecircuit.

Figure I Circuit diagram of the proposed current-controlled osc illator. The control current i i s steeredalternatively to the capac itor at the nodeV, or Vb, resultingin an alternative set or resetof the latch. The frequencyo fthe complementary output voltages, V , and V,, arecontrolled by the current i

As Pi and P, are controlled by V and V only one of themis turned on. The control current i is thus switched tocharge the gate capacitor of the transistorN I or N p raisingthe respective voltage V or V . Then, the rising voltagebecomes high enough to set(or reset) the state of the latch.

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After that the current i will be switched to charge theother gate capacitor. Therefore,i is switched alternativelyto the two gate nodes ofN I and N,, V, and Vbare raised tothe high level alternatively, i.e. the latch is set, or reset,alternatively, and V , and V , change their levelsperiodically. Mean while,V , and V , are applied at the gatesof the two transistors,N j and N4 respectively, so that Vand Vbare pulled down to 0 V alternatively.

The following pointsi n the circuit design should be noted.

A differential PMOS switch pair, controlled by theoutput voltages of the circuit, is used to steer thecontrol current i , alternatively to the tw o nodesV and

V b

The cycle time, K of the pulse signals depends on thetime required for V, or V, to be changed from zerotothe level high enough to toggle the state of the latch. Ifthe circuit structure ar e fixed and the device param etersare given, the frequency of theI C 0 will depend on thevoltage ratedVJdt = i / Ca and d V d d t= i /Cb, where C ,and c are the capacitances at node V, and V,,respectively. As all the switches can be m inimum-sizedtransistors, C and Cb are usually small. A smallcurrent variation of the control current can make asignificant change in the voltage variation rate.Thus,the frequency can be highly sensitive to the currentvariation. This feature also implies that the decrease oftransistor feature size leads toa decrease in C , and Ci.e., an increase in the sensitivity of theI C 0 to thecontrol current.

A very weak control current may resultin a relativelylong rise time of V, and Vb However, the rise or falltime of the output signals,V, and V,, depends mainlyon the current driving capacity of the inverters and theregenerative process of the latch. Thus, the quality ofthe output pulses of theIC0 is not affected by the weakcontrol current.

Six MOS switches are used to switch the controlcurrent and discharging currents.All these switches arecontrolled by the voltage signals generated in thecircuit. The circuit is, in fact,a switched-current circuitoperating without any external control voltages,

It should also be noted that the proposed I C 0 operateswith a supply voltage (VDD)lower tha n (Vt, IV,where V,, and Vt p are, respectively, the threshold voltages

of the NMOS and PMOS transistors of the inverters.IfV D D > (Vtn lVtpl). the circuit ma y have an unstableequilibrium when V and V , are both at the level of thethreshold voltage of the inverters. In this case,all the MOSswitches are turned on, andi is divided by the two PMO Sswitches. Such a state may be terminated by some randomexcitations, such as heat agitation, andthe duration of sucha state s thus undetermined. If V D D < (Vt, lVtp'), theinverters have a voltage transfer characteristic withhysteresis as shown in Figure 2 In this case, the twotransistors in each inverter will never be turned onsimultaneously, and thus, the state of the unstableequilibrium is eliminated.

Figure 2 Voltage transfer characteristic of the in vertersemployed in the proposed K O . The supply voltage of thecircuit is smaller than (Vtn IV the sum of the NMOSand PMOS threshold voltages. This kind of inverter isofte n used in electronic instrumentations.

3. SIMUL TION RESULTSThe I C 0 (Figure I has been simulated using the transistormodels of a 0.18-pm technology. All the transistors of thisI C 0 are minimum-sized. The waveformsof the signals,when the control currenti = 2 nA and the supply voltageVDD= 0 6 V, are shown inFigure 3. Figure 4 illustrates thefrequency-versus-current characteristics of the circuit. Dueto the limitation of appropriate use of the transistormodels, the minimal value ofi is chosen as 2 nA in thesimulation. How ever, wecan be sure that. in practice, thecontrol current can be much lower. The sensitivityof theIC0 is about 0 7 M Hd nA . The power dissipat ion of the

circuit depends on the frequency of the o utput voltage andit is 0 7 p W when the output frequency is about140 MHz.

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Tmnsient Response 0

time

Figure 3obtained when VDD = 0.6 V and i = 2 nA

Simulation waveforms of the proposedKO

Figure 4 Frequency-versus-current characteristicsofthe proposed ICO The supply voltageVoo = 0.6 V

4. APPLICATIONS

I C 0 circuits, in genera l, can he used in signal processingand communication systems for example,in frequencymodulation or signal generation. It can also he animportant part in a PLL circuit. However, the proposedI C 0 is particularly useful for optical signal sensing andprocessing. An incident light can he converted linearlyinto a current signal and then this curre nt can be processedby the circuits involving the IC0 and other processingunits. In this process, two featuresof the proposed I C 0need to he highlighted. First, the high sensitivity of thefrequency of the proposed IC0 to theinput current makes

the circuits capable of effectively respon dingto very weakcurrents converted from optical signals. Thus, theapplication of theI C 0 can improve the circuits capabilityof operating with weak optical signals. Second, theI C 0converts a current signal into a voltage o ne that carries theinformation through the duration of its cycle, instead of itsmagnitude. The dynam ic rangeof the circuit is, therefore,not limited by the supply voltage, thus mak ing the circuitto have a large dynam ic range as w ell as a high sensitivity.

Since the IC0 converts an analog current signal to avoltage pulse signal, it is obviously to he used for an Dconversion. Figure shows such an example. Thephotocurrent i converted from the inc ident signal is

fed to the ICO The number of the pulsesof the output ofthe I C 0 is then counted during a period ofT that is relatedto the weakest input signal. At the endof the period, thecounter will output a n-bit digital signal converted fromthe input current of theKO.

igure 5electrica l conversion andAID conversion.

Diagram of a circuit performing optical-to-

As the IC0 outputs a voltage pulse signal, the informationcarried by its analog input can be processed digitally. Thecircuit shown in Figure 6 is such an e xamp le. This circuithas two optical incident signals, and its operation iscontrolled by a clock signalelk.Dur ing the first half ofelk,the signal QINyis converted into a pulse train and thecounter counts up. When elk starts the other half, thecounter starts to count down with the number of the pulsesrelated to J / ~ ence, at the end of the elk cycle, thedifference between lNv - IM( can be read at the digitaloutput of the circuit. In this circuit, the two currents,idx

and ialc are processed in the sameICO Thus, there is noproblem of the mismatch of the conversion gains. Thiscircuit can also be used for a comparison of two opticalsignals. If the outputs of the two AND gates are applied,successively only to the up input of the counter, when

elk = 0 and elk = I , respectively, the result of q I NY , N ~will he obtained.

The IC0 can also be used fo r data conversion s along withother types of computations. An example is showninFigure 7. In this circuit. the pulse width of the output

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Figure 6

downclk Counter

IelCl

I

Diagram of a circuit performing optical-to-electricalconversion. subtractionand AID conversion.

signal of the IC 0 is T and the cycle durationof the pulsetrain applied to the other input of the AND gate is ywhere Ty