Design Methodology for Systems-on-Chip What is needed and what is not Daniel D. Gajski Center for...

Design Methodology for

Systems-on-ChipWhat is needed and what is not

Daniel D. GajskiCenter for Embedded Computer Systems

University of California, Irvine

www.cecs.uci.edu/~gajski

Copyright 2002 Daniel D. Gajski 2IEEE OCCS, 8/26/02

Who we are?

• Center for Embedded Computer Systems (www.cecs.uci.edu)

• Independent Research Organization in UC

• 15 faculty and over 60 Ph.D. students

• Methodology group:• first system contract 1989 from SRC• over 50 person years in system methodology since 1990• over 10 Ph.D. in system design flow since 1990• published first books on:

– RTL Sythesis 1992

– Embedded Systems 1994

– System Design 2001

• developed SpecC language• leaders in SpecC Open Technology Consortium (www.specc.org)• “Inspired” SystemC


Outline

• System gap• Semantics, styles and refinements• RTL Semantics• System-Level Semantics• Where are we going?• Conclusion


Past Design Flow

Simulate

Capture & Simulate

Physical

Logic

Specs

Design

Manufacturing

Algorithms

System Gap

1960’s


Past and Present Design Flow

Describe

SimulateSimulate

System Gap

Capture & Simulate

Physical

Logic

Specs

Design

Manufacturing

Algorithms

1960’s

Describe & Synthesize

Manufacturing

Specs

Algorithms(software)

Physical

Logic

Design

1980’s


Past, Present and Future Design Flow

Communications

Functionality

Connectivity

Protocols

TimingDescribe

SimulateSimulate

Physical

Logic

Specs

Design

Manufacturing

Capture & Simulate

Algorithms

Describe & Synthesize

Manufacturing

Specs

Algorithms(software)

Physical

Logic

Design

Specify, Explore & Refine

Architecture

Manufacturing

Executable Spec

Algorithms

Physical

Logic

Design

System Gap

1960’s 2000’s1980’s


Missing Semantics:Simulation Dominated Design Flow

Finite State Machine

3.4152.715

case X is

when X1 =>

when X2 => Table Lookup

Controller Memory

• Simulatable but not synthesizable


Y Chart

Behavior Structure

Physical

Synthesis

PhysicalDesign


Y Chart

Behavior Structure

Physical

Logic

Transistor

RTL

System


Y Chart

Behavior Structure

Physical

Logic

Transistor

RTL

System

MoC

MoC

MoC

MoC


Abstraction Algebra

Algebra := < {objects}, {operations} >

SoC Algebra := < {models}, {transformations} >

Ordered set of transformations < tm, … , t2, t1 > is a refinement iff

model B = tm( … ( t2( t1( model A ) ) ) … )

Question: { models } ? ; { transformations } ?


Why Abstraction Algebra?

1. Enabling standard for ESDA

2. Discover truth behind system-level myths

3. Define system-level field (abstract semantics)

4. Introduce interoperability

5. Identify system-level methodology

6. Apply system-level methodology to SystemC, SpecC

and others.


Semantics, Styles & Refinements

• Each model uses well defined semantics• Each model has simple style• Each style uniquely expressed

– no syntactic variance or semantic ambiguity

• Each model needs style checker

• Each model can be refined from its predecessor• Clear refinement rules• Clear application order of refinement rules• Model refinements are verifiable


RTL Computational Models

• Finite State Machine with Data (FSMD)• Combined model for control and computation

– FSMD = FSM + DFG

• Implementation: controller plus datapath

FSMD model

S1 S2

S3

Op2 Op3

Op4

Op6

Op1

Op5Op1 Op2

Op3

Op1 Op2


RTL Processor

Bus1

Bus2

Bus3

Datapath

D Q

D Q

D Q

Control

inputs

Next-Sate

Logicor

Addressgenerator

Outputlogic

orProgrammemory

Stateregister

orPC

Controloutputs

Register

Selector

Register

Datapathoutputs

RFCache

ALU

Signalstatus

Controller

Latch

Datamemory

IR

SR

Cotrolsignals


RTL Synthesis

Op2 Op3

Op4

Op6

Op1

Op5Op1 Op2

Op3

Op1 Op2

S1 S2

S3

FSMD modelRTL Processor

D

Q

D

Q

D

Q

Controlinputs

Next-statelogic

orAddress

generator

Outputlogic

orProgrammemory

Stateregister

orPC

Controloutputs

Controlsignals

Bus1

Bus2

Selector

Register

Datapathoutputs

ALU

Bus3

Datapath

Signalstatus

Controller

Register Memory

RF

SR

IR

Latch

Datamemory

RTL


RTL Synthesis

Op1 Op2

Op3

Op1 Op2

S1 S2

S3

FSMD model

Allocation

Rescheduling

Variable binding Operation Binding

Bus Binding

FSM Synthesis

RTL Processor

D

Q

D

Q

D

Q

Controlinputs

Next-statelogic

orAddress

generator

Outputlogic

orProgrammemory

Stateregister

orPC

Controloutputs

Controlsignals

Bus1

Bus2

Selector

Register

Datapathoutputs

ALU

Bus3

Datapath

Signalstatus

Controller

Register Memory

RF

SR

IR

Latch

Datamemory

Op2 Op3

Op4

Op6

Op1

Op5

RTL


System Computational Models

• Program State Machine– States described by procedures in a programming language

• Example: SpecC! (SystemC!)

PSM modelProc

Proc

Proc

Proc

Proc


System Synthesis

PSM model

Proc

Proc

Proc

Proc

Proc

Memory

Memory

µProcessor

Interface

Comp.IP

Bus

Interface

Interface

Interface

Custom HW

System architecture

System


System Semantics

Objects:- Behaviors- Channels

Composition:- Hierarchy- Order • Sequential • Parallel • Piped • States- Transitions • TI • TOC, TOS, ...- Synchronization

Objects:- Components • Proc • IP • Memories • IF- Connections • Buses • Wires

Composition:(same as in Behavior Model)

System


System Synthesis

PSM model

Proc

Proc

Proc

Proc

Proc

Memory

Memory

µProcessor

Interface

Comp.IP

Bus

Interface

Interface

Interface

Custom HW

System architecture

Profiling

Allocation IF Synthesis

Refinement

Behavior Binding Channel Binding

System

Variable Binding


System Synthesis (continued)

RTL/IS Implementation+ results

Mem RFState

Control

ALU

Datapath

PC

Control Pipeline

IF FSM

IF FSMIP Netlist

RAM

IR

Memory

State

State

HCFSMD model

FMDS4

FSMD5

FSMD3

FSMD2

FSMD1

RTL MoC


EDA Approach: Simulation

System

RTL

Logic

TransistorVHDL, Verilog,


C++ Approach: Syntax

System

RTL

Logic

Transistor


MoC Approach: Diversity

System

RTL

Logic

Transistor

MoC


SystemC Approach: Language First

Source: J. Kunkel, VP Synopsis, (CODES, May 2002)

C++

SystemC

CSupported

Subset


SpecC Approach: Semantics First

System

RTL

Logic

Transistor

MoC


SystemC/SpecC

SpecC

C++

SystemC

C


Quote from SystemC

FUNCTIONAL SPECIFICATION FOR

SYSTEMC 2.0

Version 2.0-MJanuary 17, 2001

1.8 ACKNOWLEDGEMENTS

“Many companies and individuals have contributed time and resources in the development of both SystemC 1.0 and SystemC 2.0. Some of these contributors are listed in the contributors section of this specification and in the SystemC 1.0 Users’s Guide.

It should be noted that the fundamental mechanisms used to model communication and synchronization in SystemC 2.0 - interfaces, channels, and events - were inspired by similar constructs in Professor Daniel Gajski’s SpecC language. (For further information, see “SpecC: Specification Language and Methodology” at www.wkap.nl)”


Conclusion

Work to be done:

1. Abstraction Levels

2. Model Semantics

3. Refinement Rules

4. Methodology

5. Language

6. Simulation, Synthesis, Verification Tools

7. ESDA Market/Community Emergence

Prediction: No success in 7 without 1-6

Design Methodology for Systems-on-Chip What is needed and what is not Daniel D. Gajski Center for...

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