Design and Simulation of a 4.0 GHz Low-Noise RFAmplifier with Avago MGA-665P8 MMIC

Sahand NoorizadehSchool of Electrical and Computer Engineering

Georgia Institute of TechnologyAtlanta, Georgia 30332–0250

Email: sahand@gatech.edu

Abstract—To achieve a desired gain or noise figure at a specificfrequency, a two-port RF amplifier network requires an appro-priate input and output matching network. More often than not,optimum gain and noise figure cannot be reached simultaneouslyand depending on design specifications, a compromise must bemade. Any two-port amplifier network can be characterizedby its S-parameters and noise parameters. This information isusually given over a wide range of frequencies in the datasheetof ready-to-use commercial amplifiers. These parameters alsocan be measured with an RF network analyzer. The conditionfor maximum power coupling from one stage to another is thatthe output impedance of the source stage should be a conjugatematch of the input impedance of the load stage. Input and outputmatching networks need to be designed to meet this conditionif the maximum power gain is the goal. Reflection coefficientsand VSWRs at the interface of stages of an amplifier circuitare the parameters that characterize matching conditions of thecircuit. A general rule in safe and good design is to reduce thepower reflection back to the source as much as possible but againthis rarely translates into having an optimum noise figure. Thedesign process of an RF amplifier requires monitoring multipleparameters simultaneously. By changing one or more parametersthe effect on the circuit performance can be monitored to achievea design goal. This process is known as optimization and itbecomes very cumbersome and time-consuming if performedwithout the aid of a computer. There many commercial CADsoftwares available that perform optimization and simulate thecircuit. A commonly used software is Agilents Advanced DesignSystem (ADS.)

I. INTRODUCTION

MGA-665P8 is an 8-pin low-noise MMIC that contains amulti-stage amplifier with the frequency range of 0.5 GHz to 6GHz and voltage bias range of 3V -5V . This MMIC was usedto design an amplifier circuit with input and output matchingnetworks designed with microsrip lines on a Duroid RO3006substrate with ϵr = 6.15, the thickness h = 25 mils, and themetalization thickness t = 0.5 mil. All the design and simula-tions were done using Agilents ADS software by importing theADS model of MGA-665P8 into ADS library. The first stepin the design was determining the S and noise parameters ofMGA-665P8 using the S-parameters simulation tool. This datawas then used to find the reflection coefficients at the input andoutput interfaces of MGA-665P8 and the matching networks todetermine their impedances. These impedances were then usedto design the matching networks with microstrip lines. Thedesign was optimized using ADS optimization tool by varyingthe lengths of the microstrip lines. Simulation results included

plots of noise figure, gain, VSWRs, and the S-parameters.Optimization process resulted in a noise figure only 0.001 dBabove the minimum achievable noise figure and consequently,the gain was 0.536 dB below the maximum achievable gain.The only hard toll taken by optimizing for minimum noisefigure was on the output VSWR which was 2.031.

II. INITIAL CALCULATIONS

Since a different DC bias network from the one recom-mended by Avago was used which would result in an slightlydifferent S-parameters, the S and noise parameters were ob-tained by ADS simulation tool. A different DC bias networkwas used because the recommended circuit in the data sheetwas designed for 5.25 GHz. The simulated device parametersat 3.0V DC are listed in Tables I and II. For simplicity

TABLE ISIMULATED S-PARAMETERS OF MGA-665P

S11 S12 S21 S22

0.274 -101.65 0.003 116.325 6.808 -168.45 0.048 -169.737

TABLE IISIMULATED NOISE PARAMETERS OF MGA-665P

Γopt Fmin RN

0.79 dB 0.399 8.481Ω

purposes, the biased circuit was exported to create hierarchy.The new component became a two-port biased MGA-665P8.Having obtained the device parameters, the stability of theamplifier was checked using the Rollets stability factor K andthe ∆ factor that were calculated using (1) and (2).

∆ = S11S22 − S12S21 (1)

K =1− |S11|2 − |S22|2 + |∆|2

2|S12S21|2(2)

Using the S-Parameters of Table I, since K = 22.611 ≫ 1and |∆| = 0.0317 ≪ 1, it was concluded that the biasedMGA-665P8 amplifier was unconditionally stable [1].

In designing for minimum noise figure, ΓS had to be setequal to Γopt and ΓL = Γ∗

OUT . The values of calculated reflec-tion coefficients and their related impedances normalizedto the

systems intrinsic impedance,Z0 = 50Ω, are listed in Tables IIIand IV respectively. Equations (3) to (6) were used to generatethe values in these tables.

TABLE IIICALCULATED REFLECTION COEFFICIENTS

ΓS ΓIN ΓOUT ΓL

0.399 43.43 0.273 -101.74 0.04 -164.64 0.043 164.64

TABLE IVCALCULATED NORMALIZED IMPEDANCES

Zs ZIN ZOUT ZL

1.5+j0.9 Ω 0.8-j0.5 Ω 0.9-j0.02 Ω 0.9+j0.02 Ω

ΓOUT = S22 +S21S12ΓS

1− S11ΓS(3)

ΓL = Γ∗OUT (4)

ΓIN = S11 +S21S12ΓL

1− S22ΓL(5)

Z =1 + Γ

1− Γ(6)

III. IMPLEMENTATION

The input matching network had to transform the impedanceof the source, 50Ω, to Z∗

IN and the output matching networkhad to transform Z∗

OUT to load’s impedance, 50Ω. The SmithChart utility and the Line Calc. tool of ADS were used todesign an appropriate matching scheme and calculate widthand length of microstrips used in the input and the outputmatching networks based on a Duroid RO3006 substrate withϵr = 6.15, the thickness h = 25 mils, and the metalizationthickness t = 0.5 mil. Figure 1 shows the microstrip lines ofthe input and output matching networks and their dimensions.

Fig. 1. Biased amplifier and microstrip line matching networks.

IV. SIMULATION AND OPTIMIZATION

The design goal for the amplifier of this project was toachieve minimum output noise figure at 4.0GHz. The amplifierwith the matching networks that were calculated and designedwas simulated with ADS‘ S-Parameters Simulation tool whichalso included noise simulation. The initial results were lessthan optimum. S22 and S11 did have their highest and lowestvalues respectively at 4.0GHz but the plots of the minimumpossible noise figure and the output noise figure showed theminimum output noise figure at 4.5GHz. To achieve the goalof this design, the optimization tool of ADS was used to varythe lengths of the striplines with the goal of minimizing theoutput noise figure nf(2). This optimization process startedwith the initial calculated lengths of the striplines and wasrepeated two more times with optimized values. Power Gain,VSWR, and the K-factor measurement tools were added tomonitor the overall performance of the amplifier circuit.

V. RESULTS AND DISCUSSION

Optimization process resulted in minimum output noisefigure, nf(2), at 4.0GHz. The plot of the minimum achievableoutput noise figure, NFmin, and the output noise figure,nf(2), is shown in Figure 2. With this result, the design goalis achieved since the output noise figure is only 0.001 dB morethan the minimum noise figure. The S-parameter plot, shownin Figure 3, also shows desired results at 4.0GHz since S22 isvery close to its maximum value and S11 is at its lowest value.Figure 4 that the power gain at 4.0GHz is almost 0.5 dB lessthan the maximum achievable stable power gain. This resultshows that the trade off between maximum power gain andminimum noise figure did not reduce the gain too much. Thisis because MGA-665P8 is designed for minimum noise forthe frequency range of the 0.5GHz to 5GHz and its datasheetspecifies a power gain of 16 dB [2]. Figure 5 shows the plot

Fig. 2. Plot of the output noise vs. minimum possible noise.

of V SWRIN and V SWROUT . V SWROUT ≈ 1 becausethe circuit was designed so that ΓL = Γ∗

OUT . And since thecircuit was designed so that ΓS = Γopt, which means theinput matching network is conjugate matched to the amplifier’sinput impeddance at 4.0GHz, V SWRIN is larger than 1. Thismeans that a portion of the power is being reflected back to thesource. This design did not have any constraints on VSWR’s

but usually a safe rule of thumb is to keep VSWR’s below1.5.

Fig. 3. S-parameters of the simulated optimized circuit.

Fig. 4. Plot of the network gain vs. maximum possible gain.

Fig. 5. Plot of the input and output VSWR’s.

VI. CONCLUSION

The design of a low-noise RF amplifier requires input andoutput matching network to meet the design requirements.Achieving the minimum noise figure does not always accom-pany maximum gain and often one or more parameters need tobe sacrificed to meet the design specifications. VSWR valuesindicate how much power is being reflected back to the source(or amplifier’s output.) VSWR’s always have to be monitoredto ensure that a large amount of power will not reflect to

Fig. 6. Plot of Rollet’s stability factor K.

damage the source. ADS is a convenient and quick tools fordesigning and simulating RF circuits and its optimization toolsallow fine tunning of the design before fabrication.

REFERENCES

[1] Gonzalez, Guillermo - Microwave Transistor Amplifier Design[2] http://www.avagotech.com