Department of Computer Science and Engineering, University of California, Riverside.
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Transcript of Department of Computer Science and Engineering, University of California, Riverside.
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
RISE & Co-S: A high performance Co-proceSsing Sensor architecture for
offloading sensing and data processing
Anirban Banerjee, Abhishek Mitra, Walid Najjar, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos
Department of Computer Science and Engineering, University of California, Riverside.
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Roadmap
Problem Addressed Motivation Contribution Sense and Store RISE:Storage RISE:Processing Experimental Results Conclusions Future Work
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Problem Addressed
To design a sensor platform satisfying the following constraints: Small form factor Energy frugal operation High computational capability Gigabyte scale data storage
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Motivation
The need for a powerful sensor to match requirements for CCB, UCR. Ecological monitoring
CO2, Temperature, Humidity Live species monitoring
Bird call patterns using spectrograms
There is a clear need for a sensor platform which can balance both energy frugalness and computational capability.
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Contribution
Developed the RISE (RIverside SEnsors) platform.
Supplement the RISE with a CoS (Co-proceSsing architecture).
Propose and implement “Sense and Store” paradigm.
Developed Gigabyte-scale Storage Board with indexing capability.
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
RISE Co-S Architecture
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Sense and Store
Pre-defined queries, e.g. max, min, top-k, avg….
Store queried values. Retrieve Queries from the index. Archive Data for offline processing. NAND Flash memory for bulk data NOR Flash memory for index
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Sense and Store (Motivation)
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128 256 512 1024 2048Data KB
En
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mJ)
SD-CARD (RISE)
M25P80 NOR-FLASH(RISE)EEPROM (MICA)
Wireless FSK 19.2kbaud
Graph depicting the Energy expended for a particular Store Vs Send ratio.
Comparison of the Energy expended while transferring data using wireless and various storage options.
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Sense and Store (Motivation)128 POINT FFT BENCHMARK RESULTS
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
RISE:Storage Design / Features
Upto 2GB SD-Card / NAND Data archival, avoids expensive erasure
operation throughout lifetime of node 1 MB on-board byte programmable NOR
Index stored on NOR Flash Avoids need to preserve it onto the volatile
SRAM
Software Driver SPI Bus Interface
SD-Card NOR Flash
Archival of sensory data Fast retrieval / search using index Updating the index Updating Top-k values in the index
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Local Access Methods
Flash Card stores temporal data [ (ts,val1,val2,….),(ts,val1,val2,….),…,(ts,val1,val2,….) ]
Example Query: “Find the timestamps on which val1 (the temperature) was 95F?”
Naïve Solution: Linear Scan over all pages on flash Card.
Problem: Too expensive to search all pages. E.g. a 256MB Flash Card features 500,000 pages!
Our Solution: MicroHash - which is an access method (index) deployed directly on the flash card to assist query evaluation.
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
MicroHash Overview An efficient access method that provides random
and sorted access to records stored on the flash medium.
Data and Index Pages are sequentially stored on Flash in a heap (sorted by timestamp).
A buffer in SRAM / NOR keeps in memory the directory, index and data pages with the highest hit ratio. MicroHash structure provides a built-in wear leveling mechanism (evenly distributes page writes) and also minimizes number of expensive random page deletions.
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Read Performance Improvements Pages are read in 512B blocks When pages are not fully occupied (i.e.
index pages) then a lot of padding is transferred to SRAM.
Since read can be performed at any granularity, we perform a Two-Phase Page Read (2PPR).
Flash Card
SRAM
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Single vs Two PhasePage Read
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Flash Card
SRAM
1 2
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2PPR - Phase 1: Read 8 byte Header and determine useful size of page.
2PPR - Phase 2: Read in SRAM the useful bytes identified in Phase
Note: To initiate a read we need a 9-byte SD-Transaction.
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
RISE:Processing Reduce Phonetic renderings of bird songs
into unique harmonics 128 point FFT on 16-bit data sampled at
10Ksps Calculate power spectral density Indexing the occurrence of harmonics USART interface from the M16C to the
Chipcon CC1010 host
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
FFT / Harmonics Extraction
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Energy Graph – FFT on Node
Energy Expended for Audio Sampling, FFT, Storage and Tx
0.00E+00
2.00E+02
4.00E+02
6.00E+02
8.00E+02
1.00E+03
1.20E+03
1.40E+03
1.60E+03
1.80E+03
2.00E+03
64 256 1024 4096 16384 65536 262144 1048576
Audio Samples
Energy(S&Snd)
Energy(S&St) FFT onCoSEnergy(S&St) FFT onRISE
Energy required to sample, Calculate FFT, Extract, Store and Transmit Harmonics, as compared to transmitting raw audio samples
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Conclusions
Developed RISE - CoS: a powerful, energy frugal platform.
Propose and Implement “Sense and Store” paradigm.
Developed Giga-scale STB for in-situ data logging.
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Future Work
32-bit, ARM-7 uC onto the CoS. (Preliminary results are encouraging)
Integrate Microscopic, sub-surface camera equipment onto RISE.
Make use of on-chip, security features of SD Card.
IEEE SECON-2005, Tue, September 27, 2005 (C) Anirban Banerjee and Abhishek Mitra
Thank You
Anirban Banerjee, Abhishek Mitra, Walid Najjar, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos (anirban, amitra, najjar, csyiazti, vana, dg) @cs.ucr.edu