1

Lab 1 Objective:

DDeessiiggnniinngg ooff IInnvveerrtteerr

Apparatus:

Transistor, Resistors, Power Supplies, Digital Millimeter, Jumpers, Connecting wires,

bread board

Theory:

Transistor inverter is essentially an overdriven common emitter circuits. The input may be a

square wave pulse waveform, or even a sine wave, provided that input amplitude is sufficient to

drive the transistor into saturation and cutoff. When input is zero, there is no collector current

and the output is approximately VCC , which is taken as high or logic level ‘1’. When input

becomes positive, transistor switches into saturation and the output becomes VCE(sat) , taken as

low or ‘0’ . Thus, a positive going output produces a negative going output, and vice versa. The

output waveform is then inverse of input, hence the name inverter.

Inverter symbol is also shown above. It inverts the input from ‘0’ to ‘1’and ‘1’ to ‘0’. The small

circle is referred as inverting bubble or inverting circle. This circle shows logic inversion

2

BE Junction OFF BE Junction ON

BC Junction OFF Cut-off Forward Active

BC Junction ON Reverse Active Saturation

MODES OF OPERATION OF BJT INVERTER

The logic ‘0’ is represented by the voltage range 0 < VIN < Vcc/2, since the input in this range

will generate a logic ‘1’ output state. Similarly logic ‘1’ is represented by voltage range Vcc/2

<VIN ≤V cc. The input voltage Vin = Vcc/2 has an undefined output and will cause unpredictable

result.

The voltage transfer characteristic for logic inverter is shown. It shoes the linearized form of an

idealized voltage transfer characteristic. Indicated on the output (vertical)axis are the voltages

VOH and VOL, which correspond to the output high and output low levels, respectively. On the

input (horizontal) axis, the input low voltage is VIL and input high voltage is VIH. Input voltage is

increased from zero, VIL is the maximum input voltage that provides a high output voltage(logic

1 output). Furthermore, VIH has the definition of being the minimum input voltage that provides

a low output voltage (logic 0 output). The Values VOH , VOL , VIL and VIH are referred to as the

3

critical voltages of VTC. In order that the high and low voltage levels always be distinguishable,

we must always have

VOH > VIH

and

VOL < VIL

Manufacturers usually specify worst case values for these four voltages. One final critical point

labled on VTC is the midpoint voltage VM. It is defined as a point on the VTC where VOUT = VIN

and ideally appears at the center of transition region.

Designing:

Design RTL inverter using 3904 transistor. The value of VCC is 10V, input is ±3v square wave

5KHz. Use IC = 1mA and find speedup capacitor, also find the critical voltages and draw VTC.

4

Circuit Diagram:

5

Input Output Waveforms:

6

Questions:

What is the purpose of speed up capacitor?

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How can we protect Base-Emitter junction from excessive reverse bias voltage?

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7

Lab 2

Objective:

SScchhmmiitttt TTrriiggggeerr CCiirrccuuiitt

Apparatus:

NPN transistor, resistors, power supplies, Signal Generator, bread board, jumpers, Oscilloscope

Theory:

Schmitt trigger is fast operating voltage level detector, when the input voltage arrives at upper

and lower triggering levels the output voltage rapidly changes. This circuit operates from almost

any input waveform and always gives a pulse type output. Transistor Schmitt trigger circuit can

be designed to trigger at specified upper and lower levels of input voltage.

8

The region between upper and lower triggering levels is called threshold region. When the input

is higher than a certain chosen threshold, the output is high; when the input is below another

(lower) chosen threshold, the output is low; when the input is between the two, the output retains

its value. The trigger is so named because the output retains its value until the input changes

sufficiently to trigger a change.

The trigger for this circuit to change states is the any input voltage level or any random wave.

The output state depends on the input level, and will change only as the input crosses a pre-

defined threshold.

Operations of Schmitt trigger Circuit:

Schmitt Trigger is an emitter coupled binary trigger circuit. It is termed a binary trigger circuit

since two stable states occur- the transistor Q1 may be ON and Q2 OFF or vice versa. In the

absence of an input to transistor Q1 the voltage divider network RB2 and R1 along with RC1

maintains the base of Q2 at a slightly positive potential relative to the emitter and thereby Q2

operates in the saturation region. Owing to the current flow in Q2, the voltage developed across

the common emitter resistor, RE maintains Q1 at cut-off. Since the base of Q1 is at ground

potential, it is negative relative to the emitter. Thus the stable state in the absence of a signal is

Q2 ON and Q1 OFF and the output voltage is in the low state. The switching action may be

started by raising or lowering the bias on Q1.

9

When an input sine wave is applied, as soon as the input voltage attains a value equal to the sum

of the voltages across RB1 and RE, Q1 turns ON since its base becomes more positive relative to

the emitter. Q1 is driven to conduction in the saturation region. The collector voltage of Q1 drops,

which in turn is coupled by the network RB2-R1 to the base of Q2. This eliminates the forward

bias on Q2 and hence it is driven to cut-off. This state persists as long as the input voltage is

greater than the sum of the voltages across Rb1 and RE. When Q2 is driven to cut-off, output

voltage switches to the difference between VCC and the voltage across RC2.

Schmitt trigger circuit outputs for various input waveforms

When the input voltage drops below the sum of the voltages across RB1 and RE Q1 turns OFF and

by regenerative action Q2 again turns ON. The output voltage falls back to the sum of the

voltages across RE and the saturation voltage of Q2. Thus a square wave is produced.

The turn ON voltage is usually called the upper trigger point or UTP and the turn OFF voltage is

called lower trigger point or LTP. UTP is always greater than LTP since the voltage required to

turn ON a device is more than that required to turn it OFF.

10

Designing:

Design a Schmitt trigger circuit to have UTP = 3V, IC is to be 2mA, the supply is 12 V. The circuit is to be triggered at maximum frequency of 1 KHz, determine the speed up capacitor.

11

Input and Output waveforms:

What is hysteresis?

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Can Schmitt trigger become Zero voltage comparator? If yes, how?

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12

Lab 3

Objective:

DDeessiiggnn aa SScchhmmiitttt TTrriiggggeerr UUssiinngg OOPP--aammpplliiffiieerr 774411((iinnvveerrttiinngg aanndd nnoonn-- iinnvveerrttiinngg mmooddee))

Apparatus:

Operational amplifier, bread board, jumpers, oscilloscope, probes

Theory:

Invertin Schmitt trigger: The IC Operational amplifier may be employed as a Schmitt

trigger circuit, in inverting and non inverting mode. The design of such a circuit is quite

simple. The input from the triggering voltage is applied to the inverting terminal. The non-

inverting terminal is connected to the junction of R1 and R2 ; these resistor operate as the

potential divider from output to ground. The voltage at the non inverting terminal is the

voltage across R2 as shown in the figure.

13

When the circuit is positively saturated, a positive voltage is feedback to the non-inverting input.

This positive input holds the output in the high state. Similarly, when the output voltage is

negatively saturated, a negative voltage is feedback to the non-inverting input, holding the output

in the low state. In either case, the positive feedback reinforces the existing output state. Schmitt

trigger is an assembly that gives output between two levels.

When a VIN of operational amplifier is less than V2 then non inverting output voltage is almost VCC.

VO= VCC-1 and V2= [ R2 *(VCC - 1)] / (R2 + R1 )

And the upper trigger point is the quality applied in the non-inverting terminal, that is

UTP = [ R2 *(VCC - 1)] / (R2 + R1 )

When input voltage rises than UTP, output becomes almost -VEE

VO = -VEE +1 and V2= [ R2 (-VEE + 1)] / (R2 + R1 )

And lower trigger point becomes equal to the V2, which is a negative quantity

LTP = [R2 (-VEE + 1)] / (R2 + R1 )

It is seen that UTP and LTP are equal in magnitude but opposite polarity

Designing:

A 741 operational amplifier is to be employed as Inverting Schmitt trigger circuit with a UTP of 3V. Design a suitable circuit and calculate the actual trigger points. Supply voltages are ± 15V. Take RL about 10 kΩ. Where maximum Ibiasing is 500nA (from data sheet)

14

Input and Output Waveforms (INVERTING)

15

Non-Inverting Schmitt trigger: The Op amp may also be employed as a Schmitt trigger

circuit, in non inverting mode. In this mode, the input voltage is applied to the non-inverting

terminal through R1 resistor and R2 is connected between output and non-inverting terminal.

This means that the circuit output goes positive when the Vi in increased from the UTP, and

goes negative when the Vi is lowered than LTP level.

Assume that the output is at negative saturation level (-VEE + 1). If the input is zero, then the

voltage across R1 is

VR1 = [R1 (-VEE + 1)] / (R2 + R1 )

So the voltage at the non-inverting terminal is a negative quantity. And this keeps the output

to negative saturation level. The inverting terminal is grounded. For the output to go

positive, Vi must be raised until the voltage at the non-inverting terminal is slightly above

the inverting terminal level(i.e. Ground). The input level that makes the non-inverting

terminal equal to inverting terminal voltage is UTP actually. After input reaching the UTP

the output becomes positive saturation level (VCC-1). Similarly LTP is numerically equal to

the UTP but with reverse polarity.

16

Designing:

A Non-Inverting Schmitt trigger circuit is to be designed to have trigger points of ±2v. The

available Supply is ± 14v. Use op-amp 741, design a suitable circuit. Where maximum Ibiasing is

500nA(from data sheet)

17

Input and Output Waveforms: (NON-INVERTING)

What is Slew rate? What is the maximum operating frequency of the op-amp?

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In inverting mode, How can we make LTP close to ground while UTP is remains same?

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18

Lab 4

Objective:

MMoonnoossttaabbllee MMuullttiivviibbrraattoorr

Apparatus:

Transistors, Resistors, Power Supplies, Bread Board

Theory

Monostable Multivibrators (also known as a one-shot multivibrator) have only ONE stable

state and they deliver a single output pulse when it is triggered externally only returning back to

its first original and stable state after a period of time determined by the time constant of the RC

One transistor is normally on and the other is normally off. This condition is reversed by the

application of triggering pulse, which turns on the normally off transistor and switches off the

19

normally on transistor. The reversed condition lasts only for a brief time period, dependent upon

the circuit components.

Consider the collector couples monostable mutivibrator circuit shown. The collector terminal of

Q2 is coupled via R1 and R2 to the base of Q1. In normal dc condition of the circuit, base current

IB2 is provided from VCC to Q2 via resistance RB. Thus, Q2 is normally on. At this time the diode

D1 is forward biased and has no significant effect on Q2. With Q2 in saturation the collector

voltage of Q2 is (VCE(sat) + VD1) above ground level. The base voltage VB1 if Q1 is determined by

a negative supply voltage VBB, and by R1 and R2, as well as the collector voltage of Q2. With Q2

collector near ground level, VB1 is likely to be a negative (i.e. Q1 base is biased bellow its

grounded emitter). Therefore, with Q2 normally on, Q1 is normally off.

When Q2 is off its collector current is zero. Therefore, there is no voltage drop across RL1, and Q1

collector is at the VCC level approximately. Also with Q2 on, voltage Q2 base is VB2 = VBE + VD1.

On the right hand terminal of capacitor C1 is VB2, and on the left-hand terminal it is VCC. Hence

the capacitor voltage is Eo = VCC – VB2, positive on the left hand side.

Now consider what would occur if the Q1 was triggered on to saturation for a brief instant. The

collector voltage of Q1 drops almost to ground level. Capacitor C1 will not lose its charge

instantaneously; therefore, when the left hand terminal of C1 is drops to VCE(sat), the right hand

terminal will drop to (VCE(sat)- Eo). Consequently Q2 base goes to (VCE(sat)- Eo) i.e. Q2 is biased

off. With Q2 off, VC2 rises, and Q1 base is biased above the ground level, and Q1 remains on. But

Q1 will remain on for a brief time.

The transistor switching process is illustrated in by the waveforms in figure shown below. Prior

to Q1 being triggered on, the voltages are: VB1 = -V, VC1 = VCC, VB2 = VBE+VD,

VC2=VCE(sat)+VD. When Q1 is triggered on, VB1 = VBE, VC1= VCE(sat), VC2 ≈ VCC

VB2=(VC1-Eo)≈-Eo.

With the exception of VB2 all the voltages remain constant while Q2 stays biased off. VB2 does

not remain constant because C1 discharges via RB. Voltage Eo across C1 is initially positive on

L.H.S and negative on the R.H.S. The current I flowing into the R.H.S of the C1 tends to

discharge C1 and then recharge it with reverse polarity. VB2 begins to rise towards the ground

level.

20

When C1 is discharged to ec≈0V, Q2 base emitter and D1 begins to forward bias again. At this

point the IC2 begins to flow again and VC2 starts to fall again. When VC2 falls, it causes VB1 to fall

again; consequently VC1 rises and causes VB2 to rise. The result of this is that Q1 rapidly switches

off and Q2 rapidly switches on again, when C1 is discharged to approximately zero volts. At this

time, the negative spike at Q1 base is due to speedup capacitor C2 transmitting at the Q2 collector

voltage change to base of Q1 and then discharging. When Q1 switches off and Q2 switches on

again, C1 rapidly recharged to Eo via RL1 and Q2 base. The circuit is returned to its normal stable

state and remains in this condition until Q1 is triggered on again.

Refer again to the waveforms in the figure. It is seen that when the voltage at Q2 collector is

appositive going pulse, that at Q1 collector is a negative going pulse. These two pluses are equal

in width and either or both may be taken as output from the circuit. The pulse width of output

depends upon the values of RB and C1. If RB is made variable output PW can be adjusted.

21

The purpose of D1 is to protect base-emitter voltage is transistor Q2 against excessive reverse

bias. When Q1 is triggered on, VB2 falls to approximately –VCC. Most transistors will not survive

a reverse base-emitter bias of more than 5V, while the most diodes might easily take reverse bias

of 50V without breakdown. So D1 is placed in series with the transistor emitter.

The output pulse width for monostable multivibrator is dictated by the time taken for C1 to

discharge from its initial voltage level to approximately zero volts. Therefore, C1 is calculated

as

t = CR ln [(E-Eo) / (E-ec)]

where ec≈0, E=VCC, Eo = -(VCC – VB2 ) = -(VCC-VBE-VD1),

t is the specified PW, and R= RB; so

C1= t / RB ln [(E-Eo) / (E-ec)]

The speedup capacitor C2 is determined by a method similar to that employed in inverter circuit

and Schmitt trigger circuit.

Designing:

A collector coupled monostable multivibrator is to operate from ±9V supply. Transistor collector currents are to be 2mA. Select a suitable capacitor to give an output pulse width of 250ms.

22

23

Output :

Questions:

How pulse width can be varied?

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What is the purpose of using diode in the circuit?

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How we can trigger the monostable?

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24

Lab 5 Objective:

AAssttaabbllee MMuullttiivviibbrraattoorr

TThheeoorryy::

An astable multivibrator is a two-stage switching circuit that generates a square wave with no

external triggering pulse. The circuit switches between its two stable states, remaining in each

state for a duration that depends on the discharging of the capacitive circuit. Each transistor has a

bias resistance RB and each is capacitor-coupled to the collector of other transistor. This is

similar to the arrangement of normally on transistor of the monostable. Consequently each

transistor in astable circuit functions in the same way as the normally on transistor in monostable

circuit. When Q1 is on and Q2 is off, capacitor C1 is charged to (VCC – VBE1 ), positive o the right

hand side. For Q2 is on and Q1 is off, capacitor C2 is charged to (VCC – VBE2 ), positive on the left

hand side.

25

Circuit Operation: When supply voltage, VCC is applied, one transistor will conduct more than

the other due to some circuit imbalance. Initially let us assume that Q1 is conducting and Q2 is

cut-off. Then VC1, the output of Q1 is equal to VCE(SAT) which is approximately zero and VC2 is

equal to VCC.

Refer to circuit waveforms in figure; it is seen that prior to time t1 , transistor Q1 is on and its

collector is at VCE(sat). Also, Q2 is off, and its transistor Q1 is on and its collector voltage is VCC.

Thus capacitor C1 is charged to (VCC – VBE1). At t1, the base voltage of transistor Q2 rises above

the ground, causing Q2 to switch on. The collector current IC2 now causes Q2 collector voltage to

fall to VCE(sat). Since C1 will not discharge instantaneously, the Base voltage of Q1 becomes

VB1 = VC2 – (charge on C1)

= VCE(sat) – (VCC – VBE1)

26

VB1 ≈ - VCC

With the emitter grounded, and its base at – VCC. Q1 is biased off. Therefore, at time t1, collector

voltage of Q1 rises to VCC. The rise of VC1 is not instantaneous, because C2 charged via RL1 as Q1

switches off.

Between times t1 and t2, the base voltage of Q2 remains at VBE, and Q2 remains biased on. During

this time, however C1 discharges via RB1. Therefore the voltage at the Q1 base rises from -VCC

towards VCC. When Q1 base rises above ground, the transistor begins to switch on. The falling

collector voltage of Q1 is coupled to Q2 base via C2, thus causing Q2 to switch off. As Q2 turns

off its collector voltage rises, and C1 is recharged via RL2 and Q2 base. This pumps a large

current into the base of Q1, making it switch on very fast. Consequently, the Q1 collector voltage

falls very rapidly to switch on. The switchover process is reversed when C2 discharges

sufficiently to allow Q2 base to rise above the ground.

The output pulse width from either transistor is equal to the time during which the transistor is

off. This is the time taken by capacitor to discharge approximately from –VCC to zero volts.

t = CR ln [( E – Eo ) / (E – ec )]

in this equation, t = PW, C = C1 = C2 , R= RB1 = RB2

and E is Supply voltage, VCC ; Eo , the initial capacitor charge, is almost equal to –VCC . (Note

that it is taken as negative, because capacitor is charged with reverse polarity to approximately

+VCC if the transistor switchover did not occur). The final capacitor charge at switchover is ec =

0 volts. So above equation becomes:

PW = CR ln [(VCC – (-VCC )) / (VCC - 0)]

= CR ln 2

PW ≈ 0.69 CR

And the output frequency is f = 1 / (2PW)

27

Designing:

Design an Astable MV to generate a 1KHz square wave. The supply voltage is 5V, and the load current is to be 20 µA. Take IC >> (load current) .

28

Output Waveforms:

Questions:

How we can change the PW of output? And how frequency is controlled?

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How frequency can be synchronized with some external frequency?

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29

Lab 6 Objective:

555555 TTiimmeerr AApppplliiccaattiioonn 11:: AAssttaabbllee

Apparatus:

555 timer, resistors, capacitors, jumpers, oscilloscope

Theory:

Astable multivibrator is a timing circuit whose 'low' and 'high' states are both unstable. This

circuit is also known as a 'pulse generator' circuit. An astable multivibrator is simply an

oscillator. The frequency of the pulses and their duty cycle are dependent upon the RC network

values.

The Astable multivibrator does not require any external trigger to change the state of the output.

Hence the name free running oscillator

In the 555 Oscillator above, pin 2 and pin 6 are connected together allowing the circuit to re-

trigger itself on each and every cycle allowing it to operate as a free running oscillator.

30

During each cycle capacitor, C charges up through both timing resistors, RA and RB but

discharges itself only through resistor, RB as the other side of RB is connected to the Discharge

terminal, pin 7. Then the capacitor charges up to 2/3Vcc (the upper comparator limit) which is

determined by the 0.693(RA+RB) C combination and discharges itself down to 1/3Vcc (the lower

comparator limit) determined by the 0.693(RB.C) combination.

Output "ON" and "OFF" time periods are determined by the capacitor and resistors

combinations.

The time period of the output is given by:

t1 = 0.693(RA+RB)*C

t2 = 0.693*RB*C

The duty cycle (the percentage of logic high to total period) can be expressed as:

Duty cycle = ((RA + RB)/( RA + 2RB)) x 100%

If both timing resistors, RA and RB are equal, the output duty cycle will be given as 2:1 or 66%.

31

Designing:

Design 555 Astable having PRF is 1kHz. And duty cycle 66% . supply voltage is 15V

32

Output waveform:

What is the effect on frequency, when RB is altered?

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How can we make duty cycle almost 50%?

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33

Lab 7 Objective:

555555 TTiimmeerr aapppplliiccaattiioonn 22:: MMoonnoossttaabbllee

Apparatus:

555 Timer, Resistors, Capacitors, Jumpers, Oscilloscope

Theory:

The 555 can be operated in either of two modes: Astable or Monostable. Monostable or 'on-shot'

mode produces a triggered output pulse of duration determined by an external resistor and an

external capacitor. 555 timer is seen to consist of a potential dividing network, two voltage

comparators, a set reset flip flop, an output stage and transistors

34

Operation: This circuit diagram shows how a 555 timer IC is configured to function as a basic

monostable In this circuit, the supply voltage is connected across terminal 8 and terminal 1.

Terminal 2(trigger) is directly connected to a trigger pulse source. CA is a capacitor which

charges from VCC via RA when npn transistor Q1 is off. Terminal 4(reset) is connected to VCC.

Terminal 5 is left open circuited, and output is taken from terminal 3. Resistor RA is connected

between terminal 6(or terminal 7) and VCC. Terminal 6 and terminal 7 are connected together.

The Capacitor CA is connected between terminal 6 and terminal 1(ground).

A negative pulse applied at terminal 2 triggers an internal flip-flop that turns off terminal 7's

discharge transistor, allowing CA to charge up through RA. At the same time, the flip-flop brings

the output (terminal 3) level to 'high'. When capacitor CA as charged up to about 2/3 VCC, the

flip-flop is triggered once again, this time making the terminal 3 output 'low' and turning on

terminal 7's discharge transistor, which discharges CA to ground. This circuit, in effect, produces

a pulse at terminal 3 whose width t. The time t required for CA to charge through 2/3 VCC

determines the output pulse width. This time is readily calculated from the equation

t = CR ln [(E-Eo) / (E-ec)]

for the circuit in the figure C=CA, R=RA E=VCC, Eo=0

35

and ec is the final capacitor voltage i.e. 2/3 VCC. Applying these quantities to the equation

t = 1.1 RA CA

CA should be normally chosen as small as possible to ensure that Q1 has no difficulty in

discharging it rapidly. If CA is to be as small as possible, then the charging current must also

be as small as possible. The minimum level of charging current occurs when the capacitor

voltage is at maximum level, i.e. when ec= 2/3 VCC. At this instant voltage across RA is

VRA = VCC – 2/3 VCC = 1/3 VCC

And the capacitor charging current is

IC(min) = (1/3 VCC)/ RA

Or RA = VCC / [3 IC(min)]

IC(min) should be chosen much greater than the threshold current Ith which flows into

terminal 6.

Designing:

Design a 555 monostable circuit to have 1ms pulse width. The supply voltage is 15V. where Ith=

0.25µA.

36

Output waveform:

37

Questions:

Why IC(min) is made much greater then threshold current Ith?

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Can output PW be less then trigger input length?

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38

Lab 8 Objective:

Bistable Multivibrator

Apparatus: Transistors, resistors, probes, oscilloscope, jumpers, DMM

Theory: Bistable multivibrator also known as flip flop is a switching circuit with two stable states.

The circuit can be triggered from one stable state to another by applying an input voltage via a

suitable triggering technique. The triggering may be applied to collector, base or emitter

Operation:The collector coupled bistable multivibrator circuit is shown in the figure, has two

stable states. Either Q1 is on and Q2 is off; or Q2 is on and Q1 is biased off. The circuit is

completely symmetrical. Load resistors RL1 and RL2 are equal, and the potential dividers (R1, R2)

39

and (R’1, R’2) form similar bias networks at the transistor bases. Each transistor is biased from

the collector of the other device. When either transistor is on, other is biased off.

Consider the condition when Q1 on and Q2 is off. With Q2 off, there is no collector current

flowing through RL2. Therefore RL2, R1 and R2 can be treated as a potential divider biasing Q1

base from VCC and –VBB. With Q1 on, its collector is at VCE(sat), and R’1 and R’2 bias VB2 below

ground level. Since the emitters are grounded, Q2 is off. The circuit can remain in this condition

(Q1 on, Q2 off) indefinitely. When Q1 is triggered off, Q2 switches on, and remains on with its

base biased via RL1 R’1 and R’2. At the time, the base of Q1 is biased negatively from Q2

collector. Thus, Q1 remains on indefinitely. The output voltage at each collector is approximately

VCC.

Capacitor C1 and C2 operates as speed capacitors to improve the switching speed of transistors.

However, in Bistable, circuit C1 and C2 are termed as Commutating or memory capacitors.

Consider the condition, when Q1 is on and Q2 is off. Capacitor C1 is charged to voltage across R1,

and C2 is charged to the voltage across R’1. The voltage across R’1 (at the base of on transistor) is

several volts greater than across R1 (at the base of the off transistor). Therefore when Q1 is on, C1

is charged to a voltage greater then the voltage on C2. Now consider what occurs when the on

transistor is triggered off for a brief instant. With both transistors off, both collector voltages are

at approximately VCC level. Also each base voltage becomes

VB = VCC –(charge on the capacitor at transistor base).

Since C2 has a smaller charge than C1, VB2 is greater than VB1. One transistor must begin to

switch on and one with highest base voltage switches on first. Thus Q2 (the formally off

transistor) switches on before Q1 and, in doing so, it biases Q1 off. Once switchover occurs, C2

becomes charged to a greater voltage than C1.

It is seen that the charge on the capacitors enables them to ‘remember’ which transistor was on

and which transistor was off, and facilitates the circuit changeover from one state to another. The

voltage on the commutating capacitors must not change significantly during the turn off time of

the transistors. If the capacitors are allowed to discharge by 10% by the difference between

maximum and minimum capacitor voltages, following equation may be applied.

t = 0.1 CR

therefore,

C = t(off) / (0.1R)

40

In this case, C = C1 = C2 and t(off) is the turn off time for the transistors; R is the resistance “seen”

looking into the terminals of R1 or R’1. With one transistor on, the maximum value of R

approximates R1R2. This gives

C1 = C2 = t(off) / (0.1 R1R2)

As for the switching circuits, the presence of capacitor limits the maximum frequency at which

bistable circuit may be triggered. To determine the maximum triggering frequency, the recovery

time for the capacitors must be calculated. This is the time for the capacitors to discharge from

from maximum voltage to minimum voltage, or vice versa. The maximum triggering frequency

is then calculated as 1/(recovery time). Recovery time is

tre = 2.3 CR

where again R = (R1R2) and maximum frequency is

fmax = 1 / tre

Designing: Design a collector coupled bistable multivibtartor to operate from ± 5V supply. Use 2N3904

transistor, with IC = 2mA. Determine the suitable commutating capacitors for this flip flop. Also

calculate maximum triggering frequency where t(off) = 250 ns

41

42

Output waveform:

Questions:

Why capacitors are called Commutating or memory capacitors?

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What is the difference between Symmetrical and asymmetrical triggering?

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43

Draw few triggering circuits and also explain working of each?

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Lab 9 Objective:

RRCC rraammpp ggeenneerraattoorr

Apparatus:

Resistors, power supply, capacitor, transistor

Theory:

A simple ramp generator can be constructed by sharing a capacitor via a series resistor in

conjunction with a discharge transistor. The simplest ramp generator circuit is a capacitor

charged via a series resistance. A transistor must be connected in parallel with the capacitor to

provide a discharge path, as shown in the figure. Capacitor C1 is charged from VCC via R1. Q1 is

biased on via RB so the capacitor is normally discharges state.

When a negative going input pulse is coupled by C2 to Q1 base, the transistor switches off. Then,

C1 begins to charge; this provides an approximate ramp output until the input pulse ends. At this

point, Q1 switches again and rapidly discharge the capacitor.

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The output from a simple CR circuit is exponential rather than linear. For voltages very

much less than the supply voltage, however, the output is approximately linear. When the

transistor is on, capacitor is discharged to VCE(sat). Hence, VCE(sat) is the saturation level of output

ramp. Output amplitude control can be provided by making the charging resistance (R1)

adjustable.

Capacitor C2, which couples the input pulse to the transistor base, should be selected as

small as possible, for both minimum cost and smallest physical size. The minimum suitable size

can be determined by allowing the base voltage of Q1 to rise during the input pulse time. The

base voltage starts approximately at 0.7 V when Q1 is on. Then VB is pulled negative by the input

pulse, but starts to rise again as C2 is charged through RB. To ensure that Q1 is still off at the end

of the pulse time, VB should not rise above -0.5V.

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If VB is allowed to rise to -0.5V, then the voltage change on the capacitor is ΔV = (Vi- VBE)-0.5

when time t is equal to the pulse width, then the simple constant current capacitor equation may

be employed to find C2,

C = It / ΔV

Designing:

Design a simple RC ramp generator to give an output that peaks at 5V. The supply voltage is

15V, and the load to be connected at the output is 100KΩ. The ramp is triggered by a negative

going pulse with an amplitude of 3V, PW=1ms, and the time interval between pulses is 0.1ms

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Output waveform:

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Question:

How we can increase the peak of the ramp?

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What are the applications of ramp generator circuit?

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Lab 10

Objective:

Drawing schematics and simulating the output of the basic digital

functions (with CMOS) using Dsch 3.0 software

Introduction:

The DSCH3 program is a logic editor and simulator. DSCH3 is used to validate the architecture

of the logic circuit before the microelectronics design is started. DSCH3 provides a user-friendly

environment for hierarchical logic design, and fast simulation with delay analysis, which allows

the design and validation of complex logic structures.

Some techniques for low power design are described in the manual. DSCH3 also features the

symbols, models and assembly support for 8051 and 18f64. DSCH3 also includes an interface to

SPICE. But here we will use it for only drawing the schematic of the functions and logic

verification. Different menus of DSCH are shown below

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The MOS as a switch

The MOS transistor is basically a switch. When used in logic cell design, it can be on or off.

When on, a current can flow between drain and source. When off, no current flow between drain

and source. The MOS is turned on or off depending on the gate voltage. In CMOS technology,

both n-channel (or nMOS) and pchannel MOS (or pMOS) devices exist. The nMOS and pMOS

symbols are reported below. The symbols for the ground voltage source (0 or VSS) and the

supply (1 or VDD) are also reported in figure

The n-channel MOS device requires a logic value 1 (or a supply VDD) to be on. In contrary, the

p-channel MOS device requires a logic value 0 to be on. When the MSO device is on, the link

between the source and drain is equivalent to a resistance. The order of range of this ‘on’

resistance is 100Ω-5KΩ. The ‘off’ resistance is considered infinite at first order, as its value is

several MΩ.

Draw schematic using CMOS and verify the truth table by timing diagram. Nand2, Nor3 & F=[a+(b.c)]’

F = [a+(b.c)]’ :

Truth table:

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Schematic diagram:

Timing diagram:

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NAND2: this gate is characterized by an output that is zero unless both of the inputs are 1.

Truth table

Schematic diagram:

Timing diagram:

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NOR3: this is three inputs NOR gate. It gives output ‘0’ to all the combinations of the input

except when all input are 0’s. When all the inputs are zeros, output is ‘1’.

Truth table

Schematic diagram:

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Timing diagram:

Questions: What are assert high and assert low switches?

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Can we change the scale of the timing diagram? If yes how?

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