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CSE140L: Components and Design Techniques for Digital Systems Lab

Tajana Simunic Rosing

Source: Eric Crabill, Xilinx

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Overview• Lab #2 due• Lab #3 assigned

– Teams of two; two teams of three possible• Put names of team members under either Group A or Group B column

at: https://spreadsheets.google.com/ccc?key=tIV_VNAr3RYsrk_SleglkZA&hl=en• Two Groups: A & B; priorities for HW use are as follows on daily basis:

– Group A 7-9am,11-1pm, 3-5pm, 7-9pm, 11pm-1am, 3-5am– Group B 9-11am, 1-3pm, 5-7pm, 9-11pm, 1-3am, 5-7am– If you don’t sign up ASAP, you have the lowest priority

– Get access to CSE 3219 lab• Robin Knox: rsknox@ucsd.edu

– EBU3B Room 2248 – Card programming times: M-Th 10-12 & 2-4pm

• What we’re up to:– FFs in Verilog (lab_wk4/5.pdf)– FSM in Verilog (lab_wk6.pdf)

Lab 2 Schedule For Demosin EBU3 3219

Date Time02/03/2010 5-6 PM02/04/2010 5-7 PM02/05/2010 10- 12 AM02/06/2010 2 -4 PM02/07/2010 8-10 PM

You can register your slot under following link

https://spreadsheets.google.com/ccc?key=0Aup_6ARWLx4WdGNNTlpValg1c2lrcXNGaHQ4S3J0dkE&hl=en

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CSE140L: Components and Design Techniques for Digital Systems Lab

Flip Flops & Verilog HDL

Tajana Simunic Rosing

Source: Eric Crabill, Xilinx

5

module designS (clk, s, r, d, q);input clk, s, r, d;output q;reg q;

always @(posedge clk)if (r) q = 1'b0;else if (s) q = 1'b1;else q = d;

endmodule

module designA (clk, s, r, d, q);input clk, s, r, d;output q;reg q;

always @(r)q = 1'b0;

always @(s)q = 1'b1;

always @(clk)q = d;

endmodule

Set/reset• Synchronous/asynchronous reset/set

– single thread that waits for the clock– three parallel threads – only one of which waits for the clock

Synchronous Asynchronous

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clock

dataD Q D Q

Non-ideal FF behavior

• Setup time– minimum time before the clocking event by which the input must be stable (Tsu)

• Hold time:– minimum time after the clocking event until which the input must remain stable (Th)

• Propagation delay– Amount of time for value to propagate from input to output (Tpd)

D

Clk

Q

T su 1.8ns

T h 0.5ns

T w 3.3 ns

T pd3.6 ns 1.1 ns

T su 1.8ns

T h 0.5 ns

T pd3.6 ns 1.1 ns

T w 3.3 ns

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D-FF original state: IN = 0, Q0 = 1, Q1 = 1due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

CLK1 is a delayedversion of CLK0

InQ0Q1

CLK0CLK1

100

Clock skew

• The problem– correct behavior assumes next state of all storage elements

determined by all storage elements at the same time– this is difficult in high-performance systems because time for clock

to arrive at flip-flop is comparable to delays through logic– effect of skew on cascaded flip-flops:

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Metastability

• Violating setup/hold time can lead to a metastable state– Metastable state: Any flip-flop state other than a stable 1 or 0

• Eventually settles to one or other, but we don’t know which– Fix: for internal circuits make sure to observe setup time; not possible for external

inputs (e.g. button press)• Partial solution

– Insert synchronizer flip-flop for asynchronous input• flip-flop w very small setup/hold time, but doesn’t completely prevent metastability

clk

D

Q

setup timeviolation

metastablestate

ai

ai

synchronizer

a

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Metastability

• One flip-flop doesn’t completely solve problem– Add more synchronizer flip-flops to decrease the probability of

metastability– Can’t solve completely – just decrease the likelihood of failure

ai

synchronizers

lowverylow

veryverylow

incrediblylow

Probability of flip-flop being metastable is…

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small, but non-zero probability that the FF output will get stuck

in an in-between state

oscilloscope traces demonstratingsynchronizer failure and eventual

decay to steady state

logic 0 logic 1logic 0

logic 1

Synchronization failure

• Occurs when FF input changes close to clock edge– the FF may enter a metastable state – neither a logic 0 nor 1 –– it may stay in this state an indefinite amount of time– this is not likely in practice but has some probability

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D DQ Qasynchronous

inputsynchronized

input

synchronous system

Clk

Dealing with synchronization failure• Reduce the probability of failure:

– (1) slow down the system clock (2) use fastest possible logic technology in the synchronizer(3) cascade two synchronizers

• (1) slow down the system clock: this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems

• (2) use fastest possible logic technology in the synchronizerthis makes for a very sharp "peak" upon which to balance

• (3) cascade two synchronizers this effectively synchronizes twice (both would have to fail)

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D Q

D Q

Q0

Clock

Clock

Q1

Async Input

Clocked Synchronous

System

D Q

D Q

Q0

Clock

Clock

Q1

Async Input D Q

Synchronizer

Handling asynchronous inputs

In is asynchronous and fans out to D0 and D1

one FF catches the signal, one does not

inconsistent state may be reached!

In

Q0

Q1

CLK

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CSE140L: Components and Design Techniques for Digital Systems Lab

FSMs

Tajana Simunic Rosing

Source: Vahid, Katz

Hardware Description Languages and Sequential Logic

• Flip-flops– representation of clocks - timing of state changes– asynchronous vs. synchronous

• FSMs– structural view (FFs separate from combinational logic)– behavioral view (synthesis of sequencers – not in this course)

• Datapath = data computation (e.g., ALUs, comparators) + registers– use of arithmetic/logical operators– control of storage elements

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Controller Design• Five step controller design process

3.4

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Controller Design: Laser Timer Example

• Problem: Pressing button (b) once turns on laser for 3 clock cycles

• Step 1: Capture the FSM• Step 2: Create architecture• Step 3: Encode the states• Step 4: Minimize logic• Step 5: Implement & test

• How about synthesis into FPGA?

a

Combinationallogic

State register

s1 s0

n1

n0

xb

clk

FSM

inpu

ts

FSM

outp

uts

Controllerx

b

clk

laser

patient

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Laser Timer• Pressing button (b) once turns on

laser for 3 clock cycles• Step 1: Capture the FSM

3.3

Controllerx

b

clk

laser

patient

Off OffOn1Off Off Off On2 On3Off

clk

State

Outputs:

Inputs:

x

b

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Controller Design: Laser Timer Example• Step 1: Capture the FSM

– Already done

• Step 2: Create architecture– 2-bit state register (for 4 states)– Input b, output x– Next state signals n1, n0

• Step 3: Encode the states– Any encoding with each state

unique will work

x=1 x=1 x=1

x=0

b

b’

01

00

10 11On2On1

Off

On3

a

Inputs: b; Outputs: x

Combinationallogic

State register

s1 s0

n1

n0

xb

clkFS

Min

puts

FSM

outp

uts

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Controller Design: Laser Timer Example (cont)• Step 4: Create state table

x=1 x=1 x=1

x=0

b

b’

01

00

10 11On2On1

Off

On3

Inputs: b; Outputs: x

Combinationallogic

State register

s1 s0

n1

n0

xb

clk

FSM

inpu

ts FSMoutputs

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Controller Design: Laser Timer Example (cont)• Step 5: Implement

combinational logic Combinationallogic

State register

s1 s0

n1

n0

xb

clk

FSM

inpu

ts FSMoutputs

x = s1 + s0

n1 = s1’s0b’ + s1’s0b + s1s0’b’ + s1s0’bn1 = s1’s0 + s1s0’

n0 = s1’s0’b + s1s0’b’ + s1s0’bn0 = s1’s0’b + s1s0’

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Controller Design: Laser Timer Example (cont)• Step 5: Implement

combinational logic (cont)

x = s1 + s0n1 = s1’s0 + s1s0’n0 = s1’s0’b + s1s0’

Combinationallogic

State register

s1 s0

n1

n0

xb

clk

FSM

inpu

ts FSMoutputs

n1

n0

s0s1

clk

Combinational Logic

State register

b

FSM inputs

x

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Understanding the Controller’s Behavior

s0s1

b x

n1

n0

x=1 x=1 x=1b

01 10 11On2On1

Off

On3

00

0 0

0

00

0

b’

0

0

0

00

x=0

000

clk

clk

Inputs:

Outputs:

1

0

10

b

1

0

10

0

s0s1

b x

n1

n0

x=1 x=1 x=1

b’

01 10 11On2On1

Off

On3

clk

b

x

00

0 0

x=0

000

state=00 state=00

s0s1

b x

n1

n0

x=1 x=1 x=1

x=0

b

b’

01

00

10 11On2On1

Off

On3

1

0

1

1

0

00

110

clk0 1

01

state=01

Laser timer in Verilog

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module LaserTimer(b, x, clk, rst);input b, clk, rst;output x;reg x;

parameter S_Off = 2'b00,S_On1 = 2'b01,S_On2 = 2'b10,S_On3 = 2'b11;

reg [1:0] currentstate;reg [1:0] nextstate;

// state register procedurealways @(posedge rst or posedge clk)beginif (rst==1) // initial state

currentstate <= S_Off;else

currentstate <= nextstate;end

// combinational logic procedurealways @(currentstate or b)begincase (currentstate)

S_Off: beginx <= 0; // laser offif (b==0) nextstate <= S_Off;else nextstate <= S_On1;

endS_On1: begin

x <= 1; // laser onnextstate <= S_On2;

endS_On2: begin

x <= 1; // laser still onnextstate <= S_On3;

endS_On3: begin

x <= 1; // laser still onnextstate <= S_Off;

endendcase

end

endmodule // LaserTimer