CSE140L: Components and Design Techniques for Digital ... · 1 CSE140L: Components and Design...
Transcript of CSE140L: Components and Design Techniques for Digital ... · 1 CSE140L: Components and Design...
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CSE140L: Components and Design Techniques for Digital Systems Lab
CPU design and PLDs
Tajana Simunic Rosing
Source: Vahid, Katz
Updates & Outline• Lab #3 due• Lab #4 – CPU design• Today:
– CPU design– PLDs
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Simple in-order processor
Objectives:
• Implementing a real processor
Challenges:• Design and implement the processor data path• Design and implement the processor control units• Make the whole thing work
Sample processor design overview
InstructionMemory
Control unit
RegisterFile
ALU
PC
Address
7-bit instruction
Instruction format
3-bit OP code 4-bit data
• Each Instruction has a size of 7 bits
Instruction format
Determines the instruction (i.e 100 = add)
Instruction set
R3 = R1 + R2
Instruction memory• Holds the whole program instructions• Implemented as a ROM
InstructionMemory
Address
7-bit instruction
module instruction_ROM(addr, inst);input [3:0] addr;output [6:0] inst;wire [6:0] memory [15:0];
assign memory[0] = 7'b0000000;assign memory[1] = 7'b0010001;assign memory[2] = 7'b0100010;assign memory[3] = 7'b1000000;assign memory[4] = 7'b0110000;assign memory[5] = 7'b0100100;assign memory[6] = 7'b1100000;assign memory[7] = 7'b1110011;assign memory[8] = 7'b0000000;assign memory[9] = 7'b0000000;assign memory[10] = 7'b0000000;assign memory[11] = 7'b0000000;assign memory[12] = 7'b0000000;assign memory[13] = 7'b0000000;assign memory[14] = 7'b0000000;assign memory[15] = 7'b0000000;assign inst = memory[addr];
endmodule
Program counter
PC
Address to memory
clk resetenable load
Branch address
• Generate the next instruction address
• For non-control flow instructions• PC = PC + 1 (Enable signal = 1)
• For control flow instructions• PC = Branch address (load signal = 1)
Instruction decoder
Control unit
Instruction 3bit OP
Data path control signals
• Decodes the instruction by reading the3-bit OP code bits from the memory
• Generate the control signals to the restof the processor (i.e. tells the ALU to
add when there is an ADD instruction)
Register file
RegisterFile
Control signals
ALU
ALU output
Instruction (bit0-bit3)
• Contains THREE 4-bit registers and the Flag bit• Each register is made up of D-FF
• Challenge:• Determine the appropriate interfacing
with the rest of you processorCompareflag
ALU
ALU
Control
ResultsInput operands
• Performs Addition, Multiplication and comparison• Two input 4-bit operands• Outputs: 4-bit results and 1-bit Compare
Interfacing
Sample code
Testing design
• Testing phase is essential to ensure that design is bug free
• Here are some tips• Generate test cases for all the instructions• Generate test cases with various input conditions• Generate test cases for some interesting combinations of
instructions (e.g. control flow with non-control flowinstructions)
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CSE140L: Components and Design Techniques for Digital Systems Lab
PLDs (cont.)
Tajana Simunic Rosing
Source: Xilinx
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Programmable Logic Devices (PLD)• PLDs combine PLA/PAL with memory and other advanced
structures– Similar to PLA/PAL, hence Field-Programmable Gate Arrays
• Types:– Antifuse PLDs– EPLD & EEPLD– FPGAs with RAMs– FPGA with processing
• Digital Signal Processing• General purpose CPU
Field-Programmable Gate Arrays
• Logic blocks– To implement combinational
and sequential logic• Interconnect
– Wires to connect inputs andoutputs to logic blocks
• I/O blocks– Special logic blocks at
periphery of device forexternal connections
• Key questions:– How to make logic blocks programmable?– How to connect the wires?– After the chip has been manufactured
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Antifuse PLDs• Actel’s Axcelerator Family
• Antifuse: – open when not programmed– Low resistance when programmed
Actel’s Axcelerator C-Cell
• C-Cell– Basic multiplexer logic plus
more inputs and support for fast carry calculation
– Carry connections are “direct” and do not require propagation through the programmable interconnect
Actel’s Accelerator R-Cell
• R-Cell– Core is D flip-flop– Muxes for altering the clock and
selecting an input– Feed back path for current value
of the flip-flop for simple hold– Direct connection from one C-cell
output of logic module to an R-cell input; Eliminates need to use the programmable interconnect
• Interconnection Fabric– Partitioned wires– Special long wires
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Altera’s EEPLD• Altera’s MAX 7k Block Diagram Global Routing:
ProgrammableInterconnectArray
LogicArrayBlocks
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EEPLD
• Altera’s MAX 7k Logic Block
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SRAM based PLD• Altera’s Flex 10k Block Diagram
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SRAM based PLD• Altera’s Flex 10k Logic Array Block (LAB)
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SRAM based PLD• Altera’s Flex 10k Logic Element (LE)
CLB
CLB
CLB
CLB
SwitchMatrix
ProgrammableInterconnect I/O Blocks (IOBs)
ConfigurableLogic Blocks (CLBs)
D Q
SlewRate
Control
PassivePull-Up,
Pull-Down
Delay
Vcc
OutputBuffer
InputBuffer
Q D
Pad
D QSD
RDEC
S/RControl
D QSD
RDEC
S/RControl
1
1
F'G'
H'
DIN
F'G'
H'
DIN
F'
G'H'
H'
HFunc.Gen.
GFunc.Gen.
FFunc.Gen.
G4G3G2G1
F4F3F2F1
C4C1 C2 C3
K
Y
X
H1 DIN S/R EC
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FPGA with DSP• Altera’s Stratix II: Block Diagram
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FPGA with DSP
• Altera’s Stratix II: – DSP Detail
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FPGA with General Purpose CPU & Analog• Actel’s Fusion Family Diagram
– FPGA with ARM 7 CPU and Analog Components
Programmable Logic Summary• Discrete Gates• Packaged Logic• PLAs• Ever more general architectures of programmable combinational +
sequential logic and interconnect– Altera– Actel– Xilinx