CSE140L: Components and Design Techniques for Digital Systems Lab Verilog HDL · 2017-08-22 ·...
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Transcript of CSE140L: Components and Design Techniques for Digital Systems Lab Verilog HDL · 2017-08-22 ·...
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CSE140L: Components and DesignTechniques for Digital Systems Lab
Verilog HDL
Source: Eric Crabill, Xilinx
Instructor: Mohsen ImaniUC San Diego
System Tasks• The $ sign denotes Verilog system tasks, there
are a large number of these, most useful being:– $display(“The value of a is %b”, a);
• Used in procedural blocks for text output.• The %b is the value format (binary, in this case…)
– $monitor• Similar to display, but executes every time one of its parameter
changes– $finish;
• Used to finish the simulation.• Use when your stimulus and response testing is done.
– $stop;• Similar to $finish, but doesn’t exit simulation.
3
Blocking/Non-Blocking Assignments
• Blocking assignments (X=A)– completes the assignment before continuing on to next
statement
• Non-blocking assignments (X<=A)– completes in zero time and doesn’t change the value of
the target until a blocking point (delay/wait) isencountered
• Watch out for assignments with delay!– Examples follow….
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Nonblocking delay – expected behavior
Source: http://www.sunburst-design.com/papers/CummingsHDLCON1999_BehavioralDelays_Rev1_1.pdf
module testbench (x, y);output x, y;reg [1:0] cnt;
initial begincnt = 0;repeat (4) begin#10 cnt = cnt + 1;$display ("@ time=%d, x=%b, y=%b, cnt=%b",
$time, x, y, cnt); end#10 $finish;
end
assign x = cnt[1];assign y = cnt[0];
endmodule
Driving a simulation through a “testbench”
2-bit vector
initial block executedonly once at startof simulation
directive to stopsimulation
print to a console
Delay Control• Generation of clock and resets in testbench:
reg rst, clk;
initial // this happens once at time zero
begin
rst = 1’b1; // starts off as asserted at time zero
#100; // wait for 100 time units
rst = 1’b0; // deassert the rst signal
end
always // this repeats forever
begin
clk = 1’b1; // starts off as high at time zero
#25; // wait for half period
clk = 1’b0; // clock goes low
#25; // wait for half period
end
“case” Statements in Verilog
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always_combbegin
case ( sel_i )2’d0 : z_o = a_i;2’d1 : z_o = b_i;2’d2 : z_o = c_i;2’d3 : z_o = d_i;default : z_o = 1’bx;
endcaseendendmodule
What does the following piece of code represent?always_combimplicitly assumea completesensitivity list.It’s the same as:always @(*)
Useful forhomework 3
Synchronous design: specify a clock
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always @(posedge clk) begin
// do stuff
end
• When writing a module with a clock signal, use behavioraldescription with the clock in the sensitivity list
Useful forhomework 3
Generate a clock in a testbench
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initialbegin
// initialize your module inputs hereend
always#5 clk = ! clk;
• When testing a module with multiple inputs, make sureyou start from a known condition
• How to generate a clock signal in a testbench?
Useful forhomework 3
Circuit Delay
• Transistors have instrinsic resistance and capacitance
• Signals take time to propagate from the input to the outputof a gate
• Sometimes delays are labeled as @<delay_value> incircuit drawings
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A B0 00 11 01 1
0110
SCout0001
S = A BCout = AB
HalfAdderA B
S
Cout +
A B0 00 11 01 1
0110
SCout0001
S = A B CinCout = AB + ACin + BCin
FullAdder
Cin
0 00 11 01 1
00001111
1001
0111
A B
S
Cout Cin+
1-Bit & Multi-bit Adders
A B
S
Cout Cin+N
NN
Types of multi-bit adders– Ripple-carry (slow)
– Carry-lookahead (faster)
– Two-level logic adder (evenfaster)
Symbol
S31
A30 B30
S30
A1 B1
S1
A0 B0
S0
C30 C29 C1 C0
Cout ++++
A31 B31
Cin
• Chain 1-bit adders together
• Carry ripples through entire chain
• Disadvantage: slow
Ripple-Carry Adder
tripple = NtFA
where tFA is the delay of a full adder
• Ripple-carry adder delay
Two-level Logic Adder• No matter how many inputs you have,
– look at the truth table,– convert to Kmap,– apply the algorithm for two-level logic minimization
• Very fast adder, but….• Beyond 8 inputs, a shockingly large amount of gates!
– Number of gates increases exponentially
Ripple carryadder
Two-level logicadder
FAST
COMPLEX
Carry-lookaheadadder (next slide)
Carry-lookahead adders
c4 c3 c2 c1 c0
b3 b2 b1 b0a3 a2 a1 a0
s3 s2 s1 s0
First operand
Second operand
Carries
Carry-lookahead adders• Adder with propagate (P) and generate (G) outputs:
Ci+1 = Ai Bi + Ci (Ai xor Bi)
PropagateGenerate
The carry at some level is equal to 1 if either the generate signal isequal to one or if the propagate and the previous carry are both 1
Ci+1 = Gi + Ci Pi
Full-Adder• Two scenarios (actually three)
– When would we always generate a carry-out based on the Ai and Bi inputsalone
– When would we always propagate the carry?– When would we actually kill the carry (meaning there is guaranteed to be no
carry-out)?
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FullAdder
CinCout
si
ai bi
Carry-Lookahead Adder• Applying these equations for a 4-bit adder we can solve for the
multiple carry-in bits:
C1 = G0 + P0C0C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
Carry-Lookahead Adder
• 4 bit adders with internal carry look-ahead P and G logic
• Second level carry-lookahead unit creates the GROUP P and G signals
4-bit Adder
4 4
4
A[15-12]B[15-12] C12
S[15-12]
P G4-bit Adder
4 4
4
A [11-8] B[11-8] C8
S[11-8]
P G4-bit Adder
4 4
4
A[7-4] B[7-4] C4
S[7-4]
P G4-bit Adder
4 4
4
A[3-0] B[3-0] C0
S[3-0]
P G
Lookahead Carry UnitC0
P0 G0P1 G1P2 G2P3 G3 C3 C2 C1
C0P3-0 G3-0
C4
C16
Carry-lookahead adders
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Example: 4-bit CLA adder
c1 = G0 + P0 c0c2 = G1 + P1 c1c3 = G2 + P2 c2c4 = G3 + P3 c3
c1 = G0 + P0 c0c2 = G1 + P1 (G0 + P0 c0) = G1 + P1G0 + P1P0c0c3 = G2 + P2 c2 = (derive at home)c4 = G3 + P3 c3 = (derive at home)
All “G” and “P” are immediatelyavailable, but “c” are not.
Gi = ai bi generatePi = ai xor bi propagate
So you need to make substitutions: