CSE-267 Microprocessor and Interfacing

8/2/2019 CSE-267 Microprocessor and Interfacing

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Data Bus: A data bus carries data. Most processors have internal data buses that carry information

inside the processor and external data buses that carry information back and forth between the

processor and memory. It is 16 bit memory.

Address Bus: An address bus carries address information. In most processors, memory is connected to

the processor with separate address and data buses. The processor places the requested address in

memory on the address bus for memory or the memory controller. It is 20 bit memory and 8bit each

block.

What is the difference between Address Bus and Data Bus?

Data bus is bidirectional, while address bus is unidirectional. That means data travels in both directions

but the addresses will travel in only one direction. The reason for this is that unlike the data, the address

is always specified by the processor. The width of the data bus is determined by the size of the individual

memory block, while the width of the address bus is determined by the size of the memory that should

be addressed by the system.

How to calculate memory size?

Calculating maximum memory size we need to consider two elements:1. The number of memory location (addresses)2. The size of each memory location

The following are assumed in the higher courses.

The size of each memory location=Data bus width=memory word size

As example: Calculate the maximum memory size of a computer with a 24bit address bus and a memory

word size 16 bits.

A 24 bit address bus allows 2 24 address = 16 MB of addresses.

Each address contains 16 bits = 2 bytes

Maximum memory size =16 MB X 2 Bytes = 32 MB

Working Principles of 8086 Microprocessor: Execution of instructions can be used to explain theworking principles of the microprocessor. Those are given below:

o The BIU outputs the contents of the instruction pointer register (IP) onto the address bus,causing the selected byte or word to be read into the BIU.

o Register IP is incremented by 1 to prepare for the next instruction fetch.o Once inside the BIU, the instruction is passed to the queue.o Assuming that the queue is initially empty, the EU immediately draws this instruction from the

queue and begins execution.

o While the EU is executing this instruction, the BIU proceeds to fetch a new instruction.Depending on the execution time of the first instruction, the BIU may fill the queue with several

new instructions before the EU is ready to draw its next instruction.

The Bus Interface Unit (BIU) is programmed to fetch a new instruction whenever the queue has room for

two additional bytes. There are three conditions that will cause the Execution Unit (EU) to enter a "wait"

mode or BIU to suspend fetching.

The first one occurs when the instruction requires access to a memory location. Here the BIU


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must suspend fetching instructions and output the address of this memory location. Then the

EU will resume execution.

The second will occur when the instruction to be executed is a "jump" instruction. In this casecontrol is to be transferred to a new non-sequential address.

The third one will occur during the execution of an instruction that is slow to execute. At fourcycles per instruction fetch, the queue will be completely filled during the execution of this

single instruction.

Draw the internal architecture of 8086 microprocessor.

Internal Architecture of 8086 Microprocessor: The figure given below is the internal architecture of

8086 microprocessor

There are two components in 8086 microprocessor these are:

1. Execution Unit (EU)2. Bus Interface Unit (BIU)

Execution Unit (EU): The purpose of execution unit is to execute instructions. Its contain circuit called

Arithmetic and Logic Unit (ALU). The ALU unit can perform various arithmetic and logical operation, if

required, based on the instruction to be executed. It can perform arithmetical operations, such as add,


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subtract, increment, decrement, convert byte/word and compare etc and logical operations, such as

AND, OR, exclusive OR, shift/rotate and test etc. The data for the operations are store in a circuit called

register.

Bus Interface Unit (BIU): The Bus Interface Unit (BIU) provides communication between the execution

unit and the memory or input output circuits. As the EU has no connection with the system Busses, this

job is done by BIU. BIU and EU are connected with an internal bus. BIU connects EU with the memory or

I/O circuits. It is responsible for transmitting data, addresses and control signal on the busses. The BIU

has 4 segment busses, CS, DS, SS, ES.

8086 Register mainly divided into four types:

1. General Register2. Segment Register3. Index/ Pointer Register4. Flag Register

General Registers: All general registers of the 8086 microprocessor can be used for arithmetic and logic

operations. The general registers are:

AX (Accumulator): This is accumulator register. It gets used in arithmetic, logic and data

transfer instructions. In manipulation and division, one of the numbers involved must be in AX

or AL.

BX (Base Register): This is base register. BX register is an address register. It usually contain a

data pointer used for based, based indexed or register indirect addressing.

CX (Count Register): This is Count Register. This serves as a loop counter. Program loop

constructions are facilitated by it. Count register can also be used as a counter in string

manipulation and shift/rotate instruction.

DX (Data Register): This is data register. Data register can be used as a port number in I/O

operations. It is also used in multiplication and division.

Index/ Pointer Register: The Index/ pointer registers are:

SP (Stack Pointer): This is stack pointer register pointing to program stack. It is used in

conjunction with SS for accessing the stack segment.

BP (Base Pointer): This is base pointer register pointing to data in stack segment. Unlike SP, we

can use BP to access data in the other segments.

SI (Source Index): This is source index register which is used to point to memory locations in the

data segment addressed by DS. By incrementing the contents of SI one can easily access

consecutive memory locations.

DI (Destination Index): This is destination index register performs the same function as SI. There

is a class of instructions called string operations that use DI to access the memory locations

addressed by ES.


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Segment Register: These all 4 segment registers holds the addresses of instructions and data in

memory. These values are used by the processor to access memory locations. It also contains 1 pointer

register IP. IP contains the address of the next instruction to execute by the EU.

CS (Code Segment) : Code segment (CS) is a 16-bit register containing address of 64 KB segment

with processor instructions. The processor uses CS segment for all accesses to instructions

referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS

register

is automatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack.

By default, the processor assumes that all data referenced by the stack pointer (SP) and base

pointer (BP) registers is located in the stack segment. SS register can be changed directly using

POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program data.

By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX)and index register (SI, DI) is located in the data segment. DS register can be changed directly

using POP and LDS instructions.

Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with

program data. By default, the processor assumes that the DI register references the ES segment

in string manipulation instructions. ES register can be changed directly using POP and LES

instructions. It is possible to change default segments used by general and index registers by

prefixing instructions with a CS, SS, DS or ES prefix.

IP (Instruction Pointer) : To access instructions the 8086 uses the registers CS and IP. The CS

register contains the segment number of the next instruction and the IP contains the offset. IP isupdated each time an instruction is executed so that it will point to the next instruction. Unlike

other registers the IP cant be directly manipulated by an instruction, that is, an instruction may

not contain IP as its operand.

Instruction Queue: BIU also contain an instruction queue. When the EU executes instructions, the BIU

gets up to 6 bytes of the next instruction and stores them in the instruction queue and this process is

called instruction prefetch. This is a process to speed up the processor. Also when the EU needs to be

connected with memory or peripherals, BIU suspends instruction prefetch and performs the needed

operations.

Purpose of using Instruction Queue: BIU contains an instruction queue. When the EU executes

instructions, the BIU gets up to 6 bytes of the next instruction and stores them in the instruction queue

and this process is called instruction prefetch. This is a process to speed up the processor. A subtle

advantage of instruction queue is that, as next several instructions are usually in the queue, the BIU can

access memory at a somewhat "leisurely" pace. This means that slow-memory parts can be used

without affecting overall system performance.

FLAGS: 8086 has 16 flag registers among which 9 are active. The purpose of the FLAGS register is to

indicate the status of the processor. It does this by setting the individual bits called flags. There are two


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kinds of FLAGS; Status FLAGS and Control FLAGS. Status FLAGS reflect the result of an operation

executed by the processor. The control FLAGS enable or disable certain operations of the processor.

1. Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow. For example when youadd bytes 255 + 1 (result is not in range 0...255). When there is no overflow this flag is set to 0

2. Sign Flag (SF) - set to 1 when result is negative. When result is positive it is set to0. (This flagtakes the value of the most significant bit.)

3. Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this flag is set to 0.8086 Microprocessor Instruction Set and its Classification

1. Data transfer instructions : MOV, XCHG2. Input /Output Instruction : IN ,OUT3. Address Instruction : LEA, LDS4. Flag Register Instruction : PUSHF, POPF5. Arithmetic instructions : ADD, SUB, INS,DEC6. Logic, shift and rotate instruction : AND, OR,SHR, SAL, ROL, RCL7. String instructions : MOVS, LODS, REP, STOS8. Conditional Transfer : JC,JNC, JO, JS9. Unconditional Transfer : CALL, RET, JMP10.Loop Instruction : INT, INTO11. Interrupt Instruction :12.Control Instruction : CLD, STD, CLI,STI

8086 Microprocessor PIN:

GND Ground

AD0-AD15 Address lines A0-A15NMI Non maskable interrupt request

INTR Maskable interrupt request

CLK Generates clock signals

MN/MX 1: Minimum Mode: At a time one process executed.

0: Maximum Mode: At a time multiple processes executed.

BHE/S7 Bus High Enable/ Status Register

RD Read data from memory when RD=0

TEST Input Signal

ALE Address Latch Enable

DI/R Data transmit/ Receive

S5 Interrupt Enable (To detect interrupt)

8279 can be programmed to perform various functions through eight command words.

1. ModeSet


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2. Prescaler:

3. Read FIFO/Sensor RAM:

4. Display Read:

5. Display Write:

6. Display Write Inhibit:

7. Clear:

8.

8279 status registers:


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F= Full U= Under Flow O= Overflow S/E= 0, No pressed multiple Keys S/E= 1, Pressed multiple Keys

D= 1, Display unavailable

8259- Priority and Interrupts Controller: There are four registers in this controller those are:

Interrupt Request Register (IRR): The interrupt request register keeps tracks of whichinterrupt inputs are asking for service.

In-Service Register (ISR): In this register keeps the tracks of which interrupt inputs are beingcurrently in serviced.

Interrupt Mask Register (IMR): The interrupt mask register is used to disable or enableindividual interrupt request.

Priority Resolver: The priority resolver act as a judge that determines if and when aninterrupt request on one of the IR input gets serviced.

Initialization Command Word Flowchart


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Initialization Command Words (ICWs):

ICW2:

ICW3 (Master Device):

ICW3 (Slave Device):

CSE-267 Microprocessor and Interfacing

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