CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

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CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng

Transcript of CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Page 1: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

CSE 242A Integrated Circuit Layout

Automation

Lecture: Global Routing

Winter 2009

Chung-Kuan Cheng

Page 2: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Outline

Menu

Multi-Commodity Flow

Top-Down Approach

Steiner Tree

Page 3: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Global Routing Menu

(1) min spanning tree

1( , ) ( ) ( ) ( )[ ( ) ( ) ( ) ( )]

2

| |

( ) height of row r

(r) penalty of using a feedthrough in row r

#demand/capacity

( ) 1 if

i j

ij th i i j jr r r

ij i j

th th

C i j x r h r H x x r h r r h r

x x x

h r

H x x x x

0 otherwise

: Average space between feedthroughs

(2) Add Steiner Points

(3) Hip L Segments

(4) Assign feedthrough locations

thx

Page 4: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Global Routing MCF

LP & Duality

nt T

t passedge ef(n,t) 0

min S

(n) ( , )

( ) ( , )

n

e

f n t b

d e f n t sC

nn

e

e td(e) 0

(n) 0

min

( ) 1

( ) ( )

n

e

b

d e C

d e n

Page 5: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Net Ordering

**

*

*

Given an initial g route,

Select net n with max ( ) ( )

C= ln

2

Iterate until converges

Assign route t according to p=f(n,t)

d t d t

d

d

Page 6: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Global RoutingTop-Down Approach

Page 7: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

4

2

4

1

T(1)…T(4)

T(5)…T(6)

T(7)…T(10)

T(11)

P1 P2

P1 P2

P1 P2 P3

P1 P2P3 P4

Page 8: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Linear Programming

1

2

1

2

1,

2,

1,

1,

max S

( , )

( , )

( , )

( , )

( , )

: #type i nets

x(i,j): #type i nets using route

i j

i j

i j H

i j H

ij

i

j

x i j S V

x i j S V

x i j S h

x i j S h

x i j n

n

p

H1V1

H2

V2

Page 9: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Steiner tree

Opt: Dynamic Programming

(Dreyfus-Wagner Algorithm)

(1) Find shortest path ( , ) v,u V

(2) For k=2, k+=1, k |T|-1

For all K T, |K|=k

For each v V-K

P v u

S

' '

w K w K

( { } min{ ( { }) ( { })

For

For S(K {v})=min{min { ( , ) ( )},min { ( , ) ( { })}

v

w

K v s K v s K K v

p v w s K p v w s K w

Page 10: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Maze Routing

Breadth First Search: Map memory reduction

1 2 1

1 2 2 2 1

1 2 2 1

1 2 2 1 1 1

2 2 1 1 S 1 1

1 2 2 1 1 1

1 2 2 1 2 2

1 2 2 2

1 2 1

2( ) or gridsO N N N 1 3 1

1 3 2 3 1

1 3 2 1 2

1 3 2 1 S 1

1 3 2 1 2

1 3 2 3 1

1 3 1

1A sequence that guarantees the predecessor is different from its successor.

# states: 1, 2, Empty, Filled,

1, 2, 3

Page 11: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Speed-up

Limit to a bounding box * 120% Start from two ends Expand from the corners farthest from the

center Expand the frontier closer to the target first

s

t

Page 12: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Depth First Search

1

2

23 3

4

45

Line probe

Page 13: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

A* router

s

it

icost

: cost to connect s and i

: estimated cost to go from i to t

st it

st

it

w m

w

m

Page 14: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Ripup and Reroute

Net sequence ordering Penalty function on overlapping Route around existing wires Plowing or compaction Topological routing

A

B

C

Page 15: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Ripup and reroute with cost driven router

( ) exp( ( ) / )

I. Set = initially

II. Increase += for each iteration

III. Do ripup and reroute with cost driven router

IV. Iterate II & III until ( ) e E

or #iterations Const

e

e

d e f e C

f e C

Page 16: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Overlap Model

1 2 3 4 5 6 7 8

8 3 2 5 4 7 6 1

Right Nets i>qi {8,7,5,3}

Left Nets i qi {1,6,4,2}

1. Sort Right Nets in decreasing order of top terminals

2. Route Right Nets

3. Sort left Nets in increasing order of bottom

terminals

4. Route left Nets

Page 17: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

8 3 2 5 4 7 6 1

1 2 3 4 5 6 7 8

Page 18: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Hybrid Router

For i = 1 to n-1, i = i+1

Preroute i longest net by the overlap model

Route the rest nets with miniswap

Choose the best result

Page 19: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.
Page 20: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

River Routing

Net Ordering For each pin (circular order)

If it is a starting pin, push Else if is ending pin, pop into a queue.

Route nets to follow contour

324

4 2 35 5

6 6

Page 21: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Planar Routing Power & Ground Distribution Find a cut line that separates the chip into two regions Obj: min tree length P + treelength G

P

G

GP

P

G

Page 22: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Gate Matrix

A

BA

B

Vdd

1

2

3

4

5

A6

B

78 A

B

9

10

Z

Page 23: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

A B C Z

1

3

6

9

2

4

7

10

5

8

Page 24: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Cell GenerationVdd

A B

C

D

A

B

C D

Z

Vdd

A B

C

DZ

A

B

C D

Z

Page 25: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Z

D

D 1

1

22CCZ

A

4

A

4

Vdd

B3

B

3

Page 26: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Find an Euler path on graph G & its dual with same sequence of labels

Given serial & parallel graph, the operation is commutative

1

2

3

2

3

1

2 2

11

Page 27: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Compaction

St

1 1 2 3 4 5

6 7 89‘

1

11 1

12 1

3 2

min

longest path of an acyclic digraph

t

s

v

x

x x

x x w

x x s

x x w

Page 28: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Compaction with Wire Jogging

Page 29: CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

Compression ridge45 degree path