CSC ME1/1 UpgradeStatus of Electronics Design

Mikhail MatveevRice University

March 28, 2012

March 28, 2012 CMS CSC ME1/1 Upgrade ECR Follow-Up 2

Scope and Responsibilities

● Digital Cathode Front End Board (DCFEB): 72 chambers x 7 boards = 504 boards (OSU)● Optical Data Acquisition Motherboard (ODMB): 72 new boards 9Ux400 mm (UCSB, Northeastern University)● Trigger Motherboard (TMB): 72 new FPGA mezzanines (Texas A&M University) ● New FPGA Mezzanine for Anode Local Charged Track (ALCT) board: 72 boards (UCLA) ● Low Voltage Distribution Board (LVDB): 72 new boards (JINR Dubna, NCPHEP Minsk)● Low Voltage Mezzanine Board (LVMB): 72 new mezzanines (UC Davis)

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DCFEB First Prototype

● Same size as old CFEB board● Same input connections and 6 BUCKEYE amplifier-shaper ASICs● 12 Texas Instruments ADS5281 ADC (8-channel, 12-bit, 50 MSPS, serial LVDS output) ● 2 legacy skewclear connectors compatible with old TMB and DMB● 3.2Gbps optical links to new TMB and new DMB● Xilinx Virtex-6 XC6VLX130T-FFG1156 FPGA ● 20-layer PCB

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DCFEB Status

● Two initial prototypes under tests since spring 2011 - bench tests at OSU - on ME2/1 chamber in B904 in place of old CFEB - trigger optical path (comparator hits) tested with new TMB (3.2Gbps) - DAQ optical path (digitized samples) tested with another DCFEB (3.2Gbps)

● Production prototype: - remove excessive R&D options - few minor changes (add DAC for calibration references and FF_EMU ASIC for TTC signals, replace voltage regulator with rad hard Micrel) ● Schematics completed, PCB layout is being finalized (~2 weeks)

● Plan to fabricate 10 boards in April (preproduction run), most parts in hand

● Low level firmware and DCS software is ready and tested

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New TMB Mezzanine

● XC6VLX195T-2FFG1156 (x5 more room than the original XC2V4000● SNAP12 transmitter and receiver - 7 receivers for DCFEB optical links - embedded GTX links - transmitter not needed for production board

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Trigger Motherboard Status

● Two prototype boards in hand since spring 2011● Power and mechanical: OK (<8A @ 3.3V; FPGA core temperature under 65 C)● 8 communication paths: - VMEbus, Clock and Control Board, Muon Port Card: OK - Fiber links to DCFEB (SNAP12): PRBS data transmission tests OK - Backplane link to DMB: OK - CFEB copper link tests (for backward compatibility): OK - ALCT and RPC tests: still to do, preparing infrastructure● Radiation and SEU testing: OK so far, done in summer 2011 and more in 2012. Reactor TID this week, cyclotron SEUs in May. ● Firmware design: old Virtex-2 firmware has been ported to Virtex-6● Test stand for production TMB mezzanines is under development at TAMU (to be able to test all paths and all BGA connections). Loop-back test circuits developed, software test suite in progress.● Schematic design and layout of the pre-production board completed, sending out pre-production quotes this week (initially 4 boards)

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Optical DAQ Motherboard

● Copper cables (5) to CFEBs replaced by optical links (7) to DCFEBs for data readout and distribution of trigger and control signals● Trigger and control signals (encoded and serialized) to/from the custom rad- tolerant FF-EMU ASIC (IBM CMOS 130 nm) housed on the DCFEBs ● Control and readout (including FIFO buffers) handled by one FPGA (Virtex-6 XC6VLX130T-FFG1156)● Full compatibility with the custom backplane

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ODMB and FF_EMU Status

ODMB:● Preliminary schematics reviewed at Fermilab Upgrade workshop in November 2011● Layout completed at CERN in December 2011 – January 2012● Three boards fabricated in February● Assembly of 2 PCBs to be completed at CERN next week● Boards to be delivered to UCSB for tests in the coming two weeks ● Test firmware and testing setup are being developed at UCSB

FF_EMU ASIC:● Samples of FF_EMU received in May 2011 and tested in summer● Major problem discovered (DC balancing was not implemented)● Second prototype was submitted in November 2011 and samples delivered to UCSB in March● Tests in progress (no new test board needed)

New ALCT Mezzanine Card

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● Replacement for old Virtex-E mezzanines on ME1/1 and ME4/2 ALCTs ● Take advantage of new Spartan-6 family: - 10x logic resources - 1.5-2x speed - 0.5x cost of Virtex-E

ALCT Mezzanine Status

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● PCB routing in progress● Firmware already ported to XC6SLX150 FPGA● 10 boards will be built in April-May

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LVDB and LVMB boards

● LVDB board distributes LV powers to on-chamber electronics● LVMB mezzanine monitors voltages and currents on LVDB and communicates with the DMB● Both boards need to be redesigned for ME1/1 upgrade (7 DCFEBs, additional temperature sensors)

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LVDB Status

● Two new LVDB boards are in hand since December 2011● On-chamber tests with 7 CFEB (7 powered and 5 in readout via FASTDAQ): OK (noise studies, voltage and currents stability at 70C)● Pre-production prototypes manufacturing in March● Interface to LVMB has been finalized● Procurement of components for LVDB is finished

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Conclusion

● 1st prototypes of the TMB, DCFEB and LVDB boards have been built and successfully tested. Good progress towards pre-production boards.

● Dedugging of the ODMB will start in early April.

● Three processing boards (DCFEB, TMB, DMB) are based on Virtex-6LXT family and use other common parts (optical, voltage regulators etc)

● 2nd prototype of the FF_EMU ASIC has arrived and is under tests

● Plan to start integration tests of all new boards at CERN (B904) in summer 2012